DM74AS652WMX [FAIRCHILD]
Octal Bus Transceiver and Register; 八路总线收发器和寄存器
| 型号： | DM74AS652WMX |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Octal Bus Transceiver and Register |
| 文件： | 总8页 (文件大小：74K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
October 1986
Revised July 2003
DM74AS651 • DM74AS652
Octal Bus Transceiver and Register
General Description
Features
These devices incorporate an octal transceiver and an
octal D-type register configured to enable transmission of
data from bus to bus or internal register to bus. The
DM74AS651 offers 64-Industrial grade product guarantee-
ing performance from −40°C to +85°C.
■ Switching specifications at 50 pF
■ Switching specifications guaranteed over full tempera-
ture and VCC range
■ Advanced oxide-isolated, ion-implanted Schottky TTL
process
These bus transceivers feature totem-pole 3-STATE out-
puts designed specifically for driving highly-capacitive or
relatively low-impedance loads. The high-impedance state
and increased high-logic-level drive provide these devices
with the capability of being connected directly to and driv-
ing the bus lines in a bus-organized system without need
for interface or pull-up components. They are particularly
attractive for implementing buffer registers, I/O ports, bidi-
rectional bus drivers, and working registers.
■ 3-STATE buffer-type outputs drive bus lines directly
■ Guaranteed performance over industrial temperature
range (−40°C to +85°C) in 64-grade products
The registers in the DM74AS651 and DM74AS652 are
edge-triggered D-type flip-flops. On the positive transition
of the clock (CAB or CBA), the input data is stored.
The SAB and SBA control pins are provided to select
whether real-time data or stored data is transferred. A LOW
input level selects real-time data and a HIGH level selects
stored data. The select controls have a “make before
break” configuration to eliminate a glitch which would nor-
mally occur in a typical multiplexer during the transition
between stored and real-time data.
The Enable (GAB and GBA) control pins provide four
modes of operation; real-time data transfer from bus A-to-
B, real-time data transfer from bus B-to-A, real-time bus A
and/or B data transfer to internal storage, or internal stored
data transfer to bus A and/or B.
Ordering Code:
Order Number Package Number
Package Description
DM74AS651WM
DM74AS651NT
DM74AS652WM
DM74AS652NT
M24B
N24C
M24B
N24C
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 2003 Fairchild Semiconductor Corporation
DS006325
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Connection Diagram
Function Table
INPUTS
DATA I/O (Note 1)
OPERATION OR FUNCTION
DM74AS651 DM74AS652
GAB GBA CAB CBA SAB
SBA
A1
THRU
A8
B1
THRU
B8
L
L
H
H
H or L H or L
X
X
X
X
Isolation
Isolation
Input
Input
↑
↑
Store A and B Data
Store A and B Data
L
L
X
X
X
L
Real Time B Data to A
Bus
Real Time B Data to A
Bus
Output
Input
L
L
X
X
H or L
X
X
L
H
X
Stored B Data to A Bus
Stored B Data to A Bus
H
H
Real Time A Data to B
Bus
Real Time A Data to B
Bus
Input
Output
Output
H
H
H or L
X
H
X
Stored A Data to B Bus
Stored A Data to B Bus
Stored A Data to B Bus
Stored A Data to B Bus
H
X
L
H or L H or L
H
X
H
X
Output
Input
& Stored B Data to A Bus & Stored B Data to A Bus
H
↑
↑
H or L
Unspecified Store A, Hold B
(Note 1)
Store A, Hold B
H
H
↑
X
(Note
2)
X
X
Input
Output
Store A in both registers Store A in both registers
L
L
X
L
H or L
↑
↑
X
Unspecified
(Note 1)
Input
Input
Hold A, Store B
Hold A, Store B
↑
X
X
(Note
2)
Output
Store B in both registers Store B in both registers
H = HIGH Level
L = LOW Level
X = Irrelevant
↑ = LOW-to-HIGH Transition
Note 1: The data output functions may be enabled or disabled by various signals at the GAB and GBA inputs. Data input functions are always enabled,
i.e., data at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs.
Note 2: If the select control is LOW, the clocks can occur simultaneously. If the select control is HIGH, the clocks must be staggered in order to load both
registers.
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2
Logic Diagrams
DM74AS651
DM74AS652
Schematics of Inputs and Outputs
Equivalent of All Other Inputs
Typical of All DM74AS651, DM74AS652 Outputs
3
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Absolute Maximum Ratings(Note 3)
Supply Voltage
Input Voltage
Control Inputs
I/O Ports
7V
7V
5.5V
Operating Free Air Temperature Range
Storage Temperature Range
Typical θJA
0°C to +70°C
Note 3: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
−65°C to +150°C
N Package
41.1°C/W
81.5°C/W
M Package
Recommended Operating Conditions
Symbol
VCC
Parameter
Min
4.5
2
Nom
Max
Units
V
Supply Voltage
5
5.5
VIH
HIGH Level Input Voltage
LOW Level Input Voltage
HIGH Level Output Current
LOW Level Output Current
Clock Frequency
V
VIL
0.8
−15
48
V
IOH
mA
mA
MHz
IOL
fCLK
tWCLK
0
5
6
6
0
0
90
Width of Enable Pulse
HIGH
LOW
ns
tSU
tH
Data Setup Time
ns
ns
°C
Data Hold Time
TA
Operating Free Air Temperature
70
Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at VCC = 5V, TA = 25°C.
Symbol
VIK
Parameter
Input Clamp Voltage
HIGH Level
Conditions
CC = 4.5V, II = −18 mA
Min
Typ
Max
Units
V
V
−1.2
V
VOH
CC = 4.5V
I
I
I
OH = Max
2
Output Voltage
OH = −3 mA
OH = −2 mA
2.4
3.2
V
V
V
V
CC = 4.5V to 5.5V
V
CC − 2
VOL
II
LOW Level Output Voltage
Input Current at
Max Input Voltage
HIGH Level
CC = 4.5V, IOL = Max
0.35
0.5
0.1
V
CC = 5.5V
VI = 7V
VI = 5.5V
Control Inputs
A or B Ports
Control Inputs
A or B Ports
Control Inputs
A or B Ports
mA
0.1
IIH
V
V
V
V
V
V
CC = 5.5V,
IH = 2.7V
CC = 5.5V,
IL = 0.4V
20
µA
Input Current
70
IIL
LOW Level
−0.5
−0.75
−112
185
195
195
195
211
211
mA
mA
Input Current
IO
Output Drive Current
Supply Current
CC = 5.5V, VO = 2.25V
CC = 5.5V
−30
ICC
Outputs HIGH
Outputs LOW
110
120
130
120
130
130
DM74AS651
Outputs Disabled
Outputs HIGH
Outputs LOW
mA
DM74AS652
Outputs Disabled
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4
DM74AS651 Switching Characteristics
Symbol
fMAX
Parameter
Maximum Clock Frequency
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Output Enable Time
Conditions
From
To
Min
Max
Units
V
CC = 4.5V to 5.5V
90
MHz
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPZH
tPZL
tPHZ
tPLZ
R
1 = R2 = 500Ω
L = 50 pF
2
2
2
1
2
2
2
3
2
2
3
3
2
2
8.5
9
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
C
CBA or CAB
A or B
8
A or B
B or A
7
11
9
SBA or SAB
(Note 4)
A or B
10
16
9
to HIGH Level Output
Output Enable Time
to LOW Level Output
Enable GBA
A
Output Disable Time
from HIGH Level Output
Output Disable Time
9
from LOW Level Output
Output Disable Time
11
16
10
11
to HIGH Level Output
Output Disable Time
to LOW Level Output
Enable GAB
B
Output Disable Time
from HIGH Level Output
Output Disable Time
from LOW Level Output
Note 4: These parameters are measured with the internal output state of the storage register opposite to that of the bus input.
5
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DM74AS652 Switching Characteristics
Symbol
fMAX
Parameter
Maximum Clock Frequency
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Output Enable Time
Conditions
From
To
Min
Max
Units
V
CC = 4.5V to 5.5V
90
MHz
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPZH
tPZL
tPHZ
tPLZ
R
1 = R2 = 500Ω
L = 50 pF
2
2
2
1
2
2
2
3
2
2
3
3
2
2
8.5
9
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
C
CBA or CAB
A or B
9
A or B
B or A
A or B
7
11
9
SBA or SAB
(Note 5)
10
16
9
to HIGH Level Output
Output Enable Time
to LOW Level Output
Enable GBA
A
Output Disable Time
from HIGH Level Output
Output Disable Time
9
from LOW Level Output
Output Disable Time
11
16
10
11
to HIGH Level Output
Output Disable Time
to LOW Level Output
Enable GAB
B
Output Disable Time
from HIGH Level Output
Output Disable Time
from LOW Level Output
Note 5: These parameters are measured with the internal output state of the storage register opposite to that of the bus input.
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6
Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M24B
7
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N24C
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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8
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