DM74LS169AN [FAIRCHILD]
Synchronous 4-Bit Up/Down Binary Counter; 同步4位加/减二进制计数器
| 型号： | DM74LS169AN |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Synchronous 4-Bit Up/Down Binary Counter |
| 文件： | 总8页 (文件大小：217K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
April 1998
DM74LS169A
Synchronous 4-Bit Up/Down Binary Counter
the carry outputs. The carry output thus enabled will produce
a low-level output pulse with a duration approximately equal
to the high portion of the QA output when counting up, and
approximately equal to the low portion of the QA output when
counting down. This low-level overflow carry pulse can be
used to enable successively cascaded stages. Transitions at
the enable P or T inputs are allowed regardless of the level
of the clock input. All inputs are diode clamped to minimize
transmission-line effects, thereby simplifying system design.
General Description
This synchronous presettable counter features an internal
carry look-ahead for cascading in high-speed counting appli-
cations. Synchronous operation is provided by having all
flip-flops clocked simultaneously, so that the outputs all
change at the same time when so instructed by the
count-enable inputs and internal gating. This mode of opera-
tion helps eliminate the output counting spikes that are nor-
mally associated with asynchronous (ripple clock) counters.
A buffered clock input triggers the four master-slave flip-flops
on the rising edge of the clock waveform.
This counter features
a fully independent clock circuit.
Changes at control inputs (enable P, enable T, load, up/
down), which modify the operating mode, have no effect until
clocking occurs. The function of the counter (whether en-
abled, disabled, loading, or counting) will be dictated solely
by the conditions meeting the stable setup and hold times.
This counter is fully programmable; that is, the outputs may
each be preset either high or low. The load input circuitry al-
lows loading with the carry-enable output of cascaded
counters. As loading is synchronous, setting up a low level at
the load input disables the counter and causes the outputs to
agree with the data inputs after the next clock pulse.
Features
n Fully synchronous operation for counting and
programming.
n Internal look-ahead for fast counting.
n Carry output for n-bit cascading.
n Fully independent clock circuit
The carry look-ahead circuitry permits cascading counters
for n-bit synchronous applications without additional gating.
Both count-enable inputs (P and T) must be low to count.
The direction of the count is determined by the level of the
up/down input. When the input is high, the counter counts
up; when low, it counts down. Input T is fed forward to enable
Connection Diagram
Dual-In-Line Package
DS006401-1
Order Number 54LS169DMQB, 54LS169FMQB, 54LS169LMQB,
DM54LS169AJ, DM54LS169AW, DM74LS169AM or DM74LS169AN
See Package Number E20A, J16A, M16A, N16E or W16A
© 1998 Fairchild Semiconductor Corporation
DS006401
www.fairchildsemi.com
Absolute Maximum Ratings (Note 1)
DM54LS and 54LS
DM74LS
−55˚C to +125˚C
0˚C to +70˚C
Supply Voltage
7V
7V
Storage Temperature Range
−65˚C to +150˚C
Input Voltage
Operating Free Air Temperature Range
Recommended Operating Conditions
Symbol
Parameter
DM54LS169A
Nom
DM74LS169A
Units
Max
Min
4.5
2
Max
Min
4.75
2
Nom
VCC
VIH
VIL
Supply Voltage
5
5.5
5
5.25
V
V
High Level Input Voltage
Low Level Input Voltage
High Level Output Current
Low Level Output Current
Clock Frequency (Note 2)
Clock Frequency (Note 3)
Clock Pulse Width (Note 4)
0.7
−0.4
4
0.8
−0.4
8
V
IOH
IOL
mA
mA
MHz
MHz
ns
fCLK
0
25
0
25
0
20
0
20
tW
25
20
20
25
20
20
tSU
Setup Time
(Note 4)
Data
Enable
T or P
Load
ns
25
30
0
25
30
0
U/D
tH
Hold Time (Note 4)
ns
˚C
TA
Free Air Operating Temperature
−55
125
0
70
Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these
limits. The parametric values defined in the “Electrical Characteristics” table are not guaranteed at the absolute maximum ratings. The “Recommended Operating
Conditions” table will define the conditions for actual device operation.
=
=
=
=
=
=
=
=
=
Note 2:
Note 3:
Note 4:
C
C
15 pF, R
2 kΩ, T
2 kΩ, T
25˚C and V
5V.
5V.
L
L
L
L
A
CC
CC
50 pF, R
25˚C and V
A
=
5V.
T
25˚C and V
CC
A
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
(Note 5)
=
=
VI
VOH
Input Clamp Voltage
High Level Output
Voltage
VCC Min, II −18 mA
−1.5
V
V
=
=
VCC Min, IOH Max
DM54
2.5
2.7
3.4
3.4
=
=
VIL Max, VIH Min
DM74
=
=
VOL
Low Level Output
Voltage
VCC Min, IOL Max
DM54
0.25
0.35
0.25
0.4
0.5
=
=
VIL Max, VIH Min
DM74
V
=
=
IOL 4 mA, VCC Min
DM74
0.4
=
@
II
Input Current Max
VCC Max
Enable T
Others
Enable T
Others
Enable T
Others
DM54
0.2
mA
µA
=
Input Voltage
High Level Input
Current
VI 7V
0.1
=
IIH
VCC Max
40
=
VI 2.7V
20
=
IIL
Low Level Input
Current
VCC Max
−0.8
−0.4
−100
−100
34
mA
mA
mA
=
VI 0.4V
=
IOS
Short Circuit
Output Current
Supply Current
VCC Max
−20
−20
(Note 6)
DM74
=
ICC
VCC Max(Note 7)
20
=
=
25˚C.
Note 5: All typicals are at V
CC
5V and T
A
Note 6: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 7: is measured after a momentary 4.5V, then ground, is applied to the CLOCK with all other inputs grounded and all the outputs open.
I
CC
www.fairchildsemi.com
2
Switching Characteristic
=
=
at VCC 5V and TA 25˚C (for Test Waveforms and Output Load)
=
RL 2 kΩ
From (Input)
=
=
Symbol
fMAX
tPLH
Parameter
Maximum Clock
To (Output)
CL 15 pF
CL 50 pF
Units
MHz
ns
Min
25
Max
Min
20
Max
Frequency
Propagation Delay Time
Low to High Level Output
Propagation Delay Time
High to Low Level Output
Propagation Delay Time
Low to High Level Output
Propagation Delay Time
High to Low Level Output
Propagation Delay Time
Low to High Level Output
Propagation Delay Time
High to Low Level Output
Propagation Delay Time
Low to High Level Output
Propagation Delay Time
High to Low Level Output
Clock to
Ripple Carry
Clock to
35
35
20
23
18
18
25
29
39
44
24
32
24
28
30
38
tPHL
ns
Ripple Carry
Clock to
tPLH
ns
Any Q
tPHL
Clock to
ns
Any Q
tPLH
Enable T to
Ripple Carry
Enable T to
Ripple Carry
Up/Down to
Ripple Carry (Note 8)
Up/Down to
Ripple Carry (Note 8)
ns
tPHL
ns
tPLH
ns
tPHL
ns
Note 8: The propagation delay from UP/DOWN to RIPPLE CARRY must be measured with the counter at either a minimum or a maximum count. As the logic level
of the up/down input is changed, the ripple carry output will follow. If the count is minimum, the ripple carry output transition will be in phase. If the count is maximum,
the ripple carry output will be out of phase.
3
www.fairchildsemi.com
Logic Diagram
LS169A Binary Counter
DS006401-2
www.fairchildsemi.com
4
Timing Diagram
LS169A Binary Counters
Typical Load, Count, and Inhibit Sequences
DS006401-3
5
www.fairchildsemi.com
Physical Dimensions inches (millimeters) unless otherwise noted
Ceramic Leadless Chip Carrier Package (E)
Order Number 54LS169LMQB
Package Number E20A
16-Lead Ceramic Dual-In-Line Package (J)
Order Number 54LS169DMQB or DM54LS169AJ
Package Number J16A
www.fairchildsemi.com
6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Small Outline Molded Package (M)
Order Number DM74LS169AM
Package Number M16A
16-Lead Molded Dual-In-Line Package (N)
Order Number DM74LS169AN
Package Number N16E
7
www.fairchildsemi.com
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Ceramic Flat Package (W)
Order Number 54LS169FMQB or DM54LS169AW
Package Number W16A
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE-
VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMI-
CONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or sys-
tems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, and (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
Fairchild Semiconductor
Corporation
Fairchild Semiconductor
Europe
Fairchild Semiconductor
Hong Kong Ltd.
National Semiconductor
Japan Ltd.
Americas
Customer Response Center
Tel: 1-888-522-5372
Fax: +49 (0) 1 80-530 85 86
Email: europe.support@nsc.com
Deutsch Tel: +49 (0) 8 141-35-0
13th Floor, Straight Block,
Ocean Centre, 5 Canton Rd.
Tsimshatsui, Kowloon
Hong Kong
Tel: 81-3-5620-6175
Fax: 81-3-5620-6179
English Tel: +44 (0) 1 793-85-68-56
Italy
Tel: +39 (0) 2 57 5631
Tel: +852 2737-7200
Fax: +852 2314-0061
www.fairchildsemi.com
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
相关型号：
©2020 ICPDF网 联系我们和版权申明