DM74LS47N [FAIRCHILD]
BCD to 7-Segment Decoder/Driver with Open-Collector Outputs; BCD到7段解码器/驱动器，集电极开路输出
| 型号： | DM74LS47N |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | BCD to 7-Segment Decoder/Driver with Open-Collector Outputs |
| 文件： | 总6页 (文件大小：70K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
October 1988
Revised March 2000
DM74LS47
BCD to 7-Segment Decoder/Driver with
Open-Collector Outputs
General Description
Features
■ Open-collector outputs
The DM74LS47 accepts four lines of BCD (8421) input
data, generates their complements internally and decodes
the data with seven AND/OR gates having open-collector
outputs to drive indicator segments directly. Each segment
output is guaranteed to sink 24 mA in the ON (LOW) state
and withstand 15V in the OFF (HIGH) state with a maxi-
mum leakage current of 250 µA. Auxiliary inputs provided
blanking, lamp test and cascadable zero-suppression func-
tions.
■ Drive indicator segments directly
■ Cascadable zero-suppression capability
■ Lamp test input
Ordering Code:
Order Number Package Number
Package Description
DM74LS47M
DM74LS47N
M16A
N16E
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
V
= Pin 16
CC
GND = Pin 8
Pin Descriptions
Pin Names
Description
A0–A3
RBI
BCD Inputs
Ripple Blanking Input (Active LOW)
Lamp Test Input (Active LOW)
LT
BI/RBO
Blanking Input (Active LOW) or
Ripple Blanking Output (Active LOW)
Segment Outputs (Active LOW) (Note 1)
a –g
Note 1: OC—Open Collector
© 2000 Fairchild Semiconductor Corporation
DS009817
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Truth Table
Decimal
or
Inputs
Outputs
Note
Function
LT
H
RBI
H
A3
L
A2
L
A1
L
A0 BI/RBO
a
L
H
L
L
b
L
L
L
L
c
L
L
H
L
d
L
e
L
f
g
H
H
L
0
1
2
3
L
H
L
H
H
H
H
L
(Note 2)
(Note 2)
H
X
L
L
L
H
L
H
L
H
H
H
H
X
L
L
H
H
H
X
L
L
H
L
H
L
4
5
6
7
8
H
H
H
H
H
X
X
X
X
X
L
L
L
L
H
H
H
H
H
L
L
L
L
H
L
H
H
H
H
H
H
L
L
H
H
L
L
L
L
L
L
H
L
H
H
L
L
L
L
H
L
L
L
L
H
L
H
H
L
H
L
L
H
L
H
L
H
L
L
L
9
H
H
H
H
H
X
X
X
X
X
H
H
H
H
H
L
L
L
H
H
L
H
L
H
H
H
H
H
L
H
H
H
L
L
H
H
L
L
H
L
H
L
H
L
L
H
H
L
L
L
L
L
L
10
11
12
13
L
H
L
L
H
H
H
H
H
H
H
H
L
L
H
H
L
14
15
H
H
X
H
L
X
X
X
L
H
H
X
L
H
H
X
L
H
H
X
L
L
H
X
L
H
H
L
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
L
H
H
H
L
L
H
H
H
L
L
H
H
H
L
L
H
H
H
L
BI
(Note 3)
(Note 4)
(Note 5)
RBI
LT
L
X
X
X
X
X
H
Note 2: BI/RBO is wire-AND logic serving as blanking input (BI) and/or ripple-blanking output (RBO). The blanking out (BI) must be open or held at a HIGH
level when output functions 0 through 15 are desired, and ripple-blanking input (RBI) must be open or at a HIGH level if blanking or a decimal 0 is not
desired. X = input may be HIGH or LOW.
Note 3: When a LOW level is applied to the blanking input (forced condition) all segment outputs go to a HIGH level regardless of the state of any other input
condition.
Note 4: When ripple-blanking input (RBI) and inputs A0, A1, A2 and A3 are LOW level, with the lamp test input at HIGH level, all segment outputs go to a
HIGH level and the ripple-blanking output (RBO) goes to a LOW level (response condition).
Note 5: When the blanking input/ripple-blanking output (BI/RBO) is OPEN or held at a HIGH level, and a LOW level is applied to lamp test input, all segment
outputs go to a LOW level.
Functional Description
The DM74LS47 decodes the input data in the pattern indi-
cated in the Truth Table and the segment identification
illustration. If the input data is decimal zero, a LOW signal
applied to the RBI blanks the display and causes a multi-
digit display. For example, by grounding the RBI of the
highest order decoder and connecting its BI/RBO to RBI of
the next lowest order decoder, etc., leading zeros will be
suppressed. Similarly, by grounding RBI of the lowest order
decoder and connecting its BI/RBO to RBI of the next high-
est order decoder, etc., trailing zeros will be suppressed.
Leading and trailing zeros can be suppressed simulta-
neously by using external gates, i.e.: by driving RBI of a
intermediate decoder from an OR gate whose inputs are
BI/RBO of the next highest and lowest order decoders. BI/
RBO also serves as an unconditional blanking input. The
internal NAND gate that generates the RBO signal has a
resistive pull-up, as opposed to a totem pole, and thus BI/
RBO can be forced LOW by external means, using wired-
collector logic. A LOW signal thus applied to BI/RBO turns
off all segment outputs. This blanking feature can be used
to control display intensity by varying the duty cycle of the
blanking signal. A LOW signal applied to LT turns on all
segment outputs, provided that BI/RBO is not forced LOW.
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2
Logic Diagram
Numerical Designations—Resultant Displays
3
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Absolute Maximum Ratings(Note 6)
Note 6: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Supply Voltage
Input Voltage
7V
7V
Operating Free Air Temperature Range
Storage Temperature Range
0°C to +70°C
−65°C to +150°C
Recommended Operating Conditions
Symbol
Parameter
Min
4.75
2
Nom
Max
Units
VCC
VIH
VIL
Supply Voltage
5
5.25
V
V
V
HIGH Level Input Voltage
LOW Level Input Voltage
HIGH Level Output Current
a − g @ 15V = VOH (Note 7)
0.8
IOH
−250
µA
IOH
IOL
TA
HIGH Level Output Current BI /RBO
LOW Level Output Current
−50
24
µA
mA
°C
Free Air Operating Temperature
0
70
Note 7: OFF-State at a–g.
Electrical Characteristics
Over recommended operating free air temperature range (unless otherwise noted)
Typ
Symbol
Parameter
Conditions
= Min, I = −18 mA
Min
Max
Units
(Note 8)
V
V
Input Clamp Voltage
V
V
V
−1.5
V
V
I
CC
I
HIGH Level
= Min, I = Max,
OH
OH
CC
2.7
3.4
Output Voltage
= Max, BI /RBO
IL
I
Output HIGH Current Segment Outputs
LOW Level
V
V
V
= 5.5V, V = 15V a − g
250
0.5
µA
OFF
CC
O
V
= Min, I = Max,
OL
OL
CC
0.35
Output Voltage
= Min, a − g
IH
I
= 3.2 mA, BI /RBO
= 12 mA, a –g
0.5
0.4
0.4
V
OL
I
0.25
OL
I
= 1.6 mA, BI /RBO
OL
I
Input Current @ Max
Input Voltage
V
= Max, V = 7V
I
I
CC
CC
CC
CC
CC
100
µA
V
V
V
V
= Max, V = 10V
I
I
HIGH Level Input Current
LOW Level Input Current
Short Circuit
= Max, V = 2.7V
20
µA
IH
I
I
= Max, V = 0.4V
−0.4
mA
IL
I
I
= Max (Note 9),
OS
mA
mA
Output Current
I
at BI/RBO
−0.3
−2.0
OS
I
Supply Current
V
= Max
13
CC
CC
Note 8: All typicals are at V = 5V, T = 25°C.
CC
A
Note 9: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Switching Characteristics
at VCC = +5.0V, T = +25°C
A
R
= 665Ω
= 15 pF
L
Symbol
Parameter
Conditions
C
Units
L
Min
Max
t
Propagation Delay
100
100
100
100
PLH
ns
ns
t
t
t
An to a –g
PHL
PLH
PHL
Propagation Delay
RBI to a –g (Note 10)
Note 10: LT = HIGH, A0–A3 = LOW
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Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
Package Number M16A
5
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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6
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