DM74LS73AN [FAIRCHILD]
Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs; 双负边沿触发的主从JK FLIP- FLOPS明确和互补输出
| 型号： | DM74LS73AN |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs |
| 文件： | 总5页 (文件大小：56K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
August 1986
Revised March 2000
DM74LS73A
Dual Negative-Edge-Triggered Master-Slave
J-K Flip-Flops with Clear and Complementary Outputs
General Description
This device contains two independent negative-edge-trig-
gered J-K flip-flops with complementary outputs. The J and
K data is processed by the flip-flops on the falling edge of
the clock pulse. The clock triggering occurs at a voltage
level and is not directly related to the transition time of the
negative going edge of the clock pulse. The data on the J
and K inputs is allowed to change while the clock is HIGH
or LOW without affecting the outputs as long as setup and
hold times are not violated. A low logic level on the clear
input will reset the outputs regardless of the levels of the
other inputs.
Ordering Code:
Order Number Package Number
Package Description
DM74LS73AM
DM74LS73AN
M14A
N14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Function Table
Inputs
CLK
Outputs
CLR
L
J
X
L
K
X
L
Q
L
Q
X
↓
↓
↓
↓
H
H
Q0
H
Q0
L
H
H
L
L
H
H
H
L
H
H
H
Toggle
H
H
X
X
Q0
Q0
H = HIGH Logic Level
L = LOW Logic Level
X = Either LOW or HIGH Logic Level
↓ = Negative going edge of pulse.
Q
= The output logic level before the indicated input conditions were
0
established.
Toggle = Each output changes to the complement of its previous level on
each falling edge of the clock pulse.
© 2000 Fairchild Semiconductor Corporation
DS006372
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Absolute Maximum Ratings(Note 1)
Note 1: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Supply Voltage
Input Voltage
7V
7V
Operating Free Air Temperature Range
Storage Temperature Range
0°C to +70°C
−65°C to +150°C
Recommended Operating Conditions
Symbol
Parameter
Min
4.75
2
Nom
Max
Units
V
VCC
VIH
VIL
Supply Voltage
5
5.25
HIGH Level Input Voltage
LOW Level Input Voltage
HIGH Level Output Current
LOW Level Output Current
Clock Frequency (Note 2)
Clock Frequency (Note 3)
V
0.8
−0.4
8
V
IOH
IOL
mA
mA
MHz
MHz
fCLK
fCLK
tW
0
0
30
25
Pulse Width
(Note 2)
Clock HIGH
20
25
25
25
30
30
20↓
25↓
0↓
5↓
0
Preset LOW
Clear LOW
Clock HIGH
Preset LOW
Clear LOW
ns
ns
tW
Pulse Width
(Note 3)
tSU
tSU
tH
Setup Time (Note 2)(Note 4)
Setup Time (Note 3)(Note 4)
Hold Time (Note 2)(Note 4)
Hold Time (Note 3)(Note 4)
Free Air Operating Temperature
ns
ns
ns
ns
°C
tH
TA
70
Note 2: C = 15 pF, R = 2 kΩ, T = 25°C and V = 5V.
L
L
A
CC
Note 3: C = 50 pF, R = 2 kΩ, T = 25°C and V = 5V.
L
L
A
CC
Note 4: The symbol (↓) indicates the falling edge of the clock pulse is used for reference.
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2
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Typ
Symbol
Parameter
Conditions
= Min, I = −18 mA
Min
Max
Units
(Note 5)
V
V
Input Clamp Voltage
HIGH Level
V
V
V
V
V
−1.5
V
V
I
CC
I
= Min, I = Max
OH
CC
OH
2.7
3.4
Output Voltage
LOW Level
= Max, V = Min
IH
IL
V
= Min, I = Max
OL
OL
CC
0.35
0.25
0.5
Output Voltage
= Max, V = Min
V
IL
IH
I
= 4 mA, V = Min
0.4
0.1
0.3
0.4
20
OL
CC
I
I
I
Input Current @ Max
Input Voltage
V
= Max
J, K
I
CC
V = 7V
Clear
Clock
J, K
mA
µA
mA
I
HIGH Level
V
= Max
IH
IL
CC
Input Current
V = 2.7V
Clear
Clock
J, K
60
I
80
LOW Level
V
= Max
−0.4
−0.8
−0.8
−100
6
CC
Input Current
V = 0.4V
Clear
Clock
I
I
I
Short Circuit Output Current
Supply Current
V
V
= Max (Note 6)
= Max (Note 7)
−20
mA
mA
OS
CC
CC
4
CC
Note 5: All typicals are at V = 5V, T = 25°C.
CC
A
Note 6: Not more than one output should be shorted at a time, and the duration should not exceed one second. For devices, with feedback from the outputs,
where shorting the outputs to ground may cause the outputs to change logic state, an equivalent test may be performed where V = 2.125V with the mini-
O
mum and maximum limits reduced by one half from their stated values. This is very useful when using automatic test equipment.
Note 7: With all outputs OPEN, I is measured with the Q and Q outputs HIGH in turn. At the time of measurement, the clock is grounded.
CC
Switching Characteristics
at VCC = 5V and T = 25°C
A
R
= 2 kΩ
From (Input)
To (Output)
L
Symbol
Parameter
C
= 15 pF
C
= 50 pF
Units
L
L
Min
30
Max
Min
25
Max
f
Maximum Clock Frequency
Propagation Delay Time
HIGH-to-LOW Level Output
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
MHz
ns
MAX
t
Clear
to Q
PHL
20
20
20
20
28
24
24
28
t
Clear
PLH
ns
ns
ns
to Q
t
Clock to
Q or Q
Clock to
Q or Q
PLH
t
PHL
3
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Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
Package Number M14A
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4
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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5
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