DM93S41N [FAIRCHILD]
4-Bit Arithmetic Logic Unit; 4位算术逻辑单元
| 型号： | DM93S41N |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | 4-Bit Arithmetic Logic Unit |
| 文件： | 总7页 (文件大小：65K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
October 1988
Revised May 2000
DM93S41
4-Bit Arithmetic Logic Unit
General Description
The DM93S41 4-bit arithmetic logic units can perform all
the possible 16 logic operations on two variables and a
variety of arithmetic operations; the Add and Subtract
modes are the most important.
Ordering Code:
Order Number Package Number
Package Description
DM93S41N
N24A
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.600 Wide
Logic Symbols
Connection Diagram
Active LOW Operands
Pin Descriptions
Active HIGH Operands
Pin Name
Description
A0–A3, B0–B3 Operand Inputs (Active LOW)
S0–S3
M
Function Select Inputs
Mode Control Input
Cn
Carry Input
F0–F3
A = B
G
Function Outputs (Active LOW)
Comparator Output
Carry Generate Output (Active LOW)
Carry Propagate Output (Active LOW)
Carry Output
P
Cn+4
© 2000 Fairchild Semiconductor Corporation
DS009805
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Functional Description
The DM93S41 is a 4-bit high speed parallel arithmetic logic
unit (ALU). Controlled by the four Function Select inputs
(S0–S3) and the Mode Control input (M), it can perform all
the 16 possible operations or 16 different arithmetic opera-
tions on active HIGH or active LOW operands. The Func-
tion Table below lists these operations.
The A = B output from the DM93S41 goes HIGH when all
four Fn outputs are HIGH and can be used to indicate logic
equivalence over four bits when the unit is in the subtract
mode. The A = B output is open-collector and can be wired-
AND with the other A = B outputs to give a comparison for
more than four bits. The A = B signal can also be used with
the Cn+4 signal to indicate A > B and A < B.
When the Mode Control input (M) is HIGH, all internal car-
ries are inhibited and the device performs logic operations
on the individual bits as listed. When the Mode Control
input is LOW, the carries are enabled and the device per-
forms arithmetic operations on the two 4-bit words. The
device incorporates full internal carry lookahead and pro-
vides for either ripple carry between devices using the Cn+4
The Function Table lists the arithmetic operations that are
performed without a carry in. An incoming carry adds a one
to each operation. Thus select code LHHL generates A
minus B minus 1 (2s complement notation) without a carry
in and generates A minus B when a carry is applied.
Because subtraction is actually performed by complemen-
tary addition (1s complement), a carry out means borrow;
thus a carry is generated when there is no underflow and
no carry is generated when there is underflow.
output, or for carry lookahead between packages using the
signals P (Carry Propagate) and G (Carry Generate). P
and G are not affected by carry in. When speed require-
ments are not stringent, the DM93S41 can be used in a
simple ripple carry mode by connecting the Carry output
(Cn+4) signal to the Carry input (Cn) of the next unit. For
As indicated the '41 can be used with either active LOW
inputs producing active LOW outputs or with active HIGH
inputs producing active HIGH outputs. For either case the
table lists the operations that are performed to the oper-
ands labeled inside the logic symbol.
super high speed operation the Schottky DM93S41 should
be used in conjunction with the '42 carry lookahead circuit.
Function Table
Mode Select
Inputs
Active LOW Inputs
& Outputs
Logic Arithmetic (Note 2)
(M = H) (M = L) (Cn = L)
A minus 1
Active HIGH Inputs
& Outputs
Logic Arithmetic (Note 2)
S3
S2
S1
S0
(M = H)
(M = L) (Cn = H)
L
L
L
L
L
L
L
H
L
A
A
A
AB
AB minus 1
AB minus 1
minus 1
A + B
AB
A + B
L
L
H
H
L
A + B
Logic 1
A + B
B
A + B
L
L
H
L
Logic 0
AB
minus 1
L
H
H
H
H
L
A plus (A + B)
AB plus (A + B)
A minus B minus 1
A + B
A plus AB
L
L
H
L
B
(A +B) plus AB
A minus B minus 1
AB minus 1
A plus AB
L
H
H
L
A
B
A
B
L
H
L
A + B
AB
H
H
H
H
H
H
H
H
AB
A plus (A + B)
A plus B
A + B
L
L
H
L
A
B
A
B
A plus B
L
H
H
L
B
AB plus (A + B)
A + B
B
(A + B) plus AB
AB minus 1
A plus A (Note 1)
(A + B) plus A
(A + B) plus A
A minus 1
L
H
L
A + B
Logic 0
AB
AB
H
H
H
H
A plus A (Note 1)
AB plus A
Logic 1
A + B
A + B
A
L
H
L
H
H
AB
AB minus A
A
H
A
H = HIGH Voltage Level
L = LOW Voltage Level
Note 1: Each bit is shifted to the next more significant position
Note 2: Arithmetic operations expressed in 2s complement notation
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2
TABLE 1. SUM MODE TEST Function Inputs: S0 = S3 = 4.5V, S1 = S2 = M = 0V
Input
Under
Test
Other Input Same Bit
Other Data Input
Output
Under
Test
Symbol
Apply
4.5V
Apply
GND
Apply
4.5V
Apply
GND
tPLH, tPHL
tPLH, tPHL
tPLH, tPHL
tPLH, tPHL
tPLH, tPHL
tPLH, tPHL
tPLH, tPHL
tPLH, tPHL
tPLH, tPHL
tPLH, tPHL
tPLH, tPHL
Ai
Bi
Ai
Bi
A
Bi
Ai
None
None
None
None
None
None
B
Remaining A to B
Remaining A to B
Cn
Cn
Fi
Cn
Fi
Bi
Remaining A and B
Remaining A and B
Remaining A and B, Cn
Remaining A and B, Cn
Remaining A, Cn
Remaining A, Cn
Remaining A, Cn
Remaining A, Cn
All B
Fi + 1
Ai
Cn
Fi + 1
B
None
P
B
A
None
P
A
None
None
None
None
None
Remaining B
Remaining B
Remaining B
Remaining B
All A
G
G
B
A
A
B
Cn + 4
B
A
Cn + 4
Cn
None
Any F or Cn + 4
TABLE 2. DIFF MODE TEST Function Inputs: S1 = S2 = 4.5V,S0 = S3 = M = 0V
Input
Under
Test
Other Input Same Bit
Other Data Inputs
Output
Under
Test
Symbol
Apply
4.5V
Apply
GND
Apply
4.5V
Apply
GND
t
PLH, tPHL
A
B
None
A
B
None
Bi
Remaining A
Remaining A
Remaining B, Cn
Remaining B, Cn
None
Remaining B, Cn
Remaining B, Cn
Fi
Fi
tPLH, tPHL
tPLH, tPHL
tPLH, tPHL
tPLH, tPHL
tPLH, tPHL
tPLH, tPHL
tPLH, tPHL
tPLH, tPHL
Ai
Bi
A
None
Ai
Remaining A
Fi + 1
Fi + 1
P
None
B
Remaining A
None
A
Remaining A and B, Cn
Remaining A and B, Cn
Remaining A and B, Cn
Remaining A and B, Cn
Remaining B, Cn
B
None
None
A
None
P
A
B
None
G
B
None
None
A
None
G
A
B
Remaining A
Remaining A
None
A = B
A = B
t
PLH, tPHL
tPLH, tPHL
PLH, tPHL
B
None
None
A
Remaining B, Cn
A
B
Remaining A and B, Cn
Remaining A and B, Cn
None
C
C
C
n + 4
n + 4
n + 4
t
B
None
None
None
tPLH, tPHL
Cn
None
All A and B
TABLE 3. LOGIC MODE TEST Function Inputs: S1 = S2 = M = 4.5V, S0 = S3 = 0V
Input
Under
Test
Other Input Same Bit
Other Data Inputs
Output
Under
Test
Symbol
Apply
4.5V
Apply
GND
Apply
4.5V
Apply
GND
t
PLH, tPHL
A
B
B
A
None
None
None
None
Remaining A and B, Cn
Remaining A and B, Cn
Any F
Any F
tPLH, tPHL
3
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Logic Diagram
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4
Absolute Maximum Ratings(Note 3)
Note 3: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Supply Voltage
Input Voltage:
7V
5.5V
Operating Free Air Temperature Range
Storage Temperature Range
0°C to +70°C
−65°C to +150°C
Recommended Operating Conditions
Symbol
Parameter
Min
4.75
2
Nom
Max
Units
V
VCC
VIH
VIL
IOH
IOL
TA
Supply Voltage
5
5.25
HIGH Level Input Voltage
LOW Level Input Voltage
HIGH Level Output Current
LOW Level Output Current
Free Air Operating Temperature
V
0.8
−1
20
70
V
mA
mA
°C
0
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Typ
Symbol
Parameter
Conditions
Min
Max
Units
(Note 4)
VI
VOH
Input Clamp Voltage
V
V
V
V
V
V
V
V
V
V
CC = Min, II = − 18 mA
CC = Min, IOH = Max
IL = Max
−1.2
V
V
HIGH Level
2.7
3.4
Output Voltage
VOL
LOW Level
CC = Min, IOL = Max
IH = Min
0.35
0.5
V
Output Voltage
II
Input Current @ Max Input Voltage
HIGH Level Input Current
LOW Level Input Current
Short Circuit Output Current
Supply Current
CC = Max, VI = 5.5V
CC = Max, VI = 2.7V
CC = Max, VI = 0.5V
CC = Max (Note 5)
CC = Max
1
mA
µA
IIH
IIL
50
−1.6
−100
mA
mA
IOS
ICCL
−40
M, S0–S3 = 4.5V
150
140
mA
mA
All Other Inputs = 0V
ICCH
Supply Current
VCC = Max
Cn, B0–B3 = GND
All Other Inputs = 4.5V
Note 4: All typicals are at VCC = 5V, TA = 25°C.
Note 5: Not more than one output should be shorted at a time, and the duration should not exceed one second.
5
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Switching Characteristics
V
CC = +5.0V, TA = +25°C
CL = 15 pF
L = 280Ω
Max
Symbol
Parameter
Conditions
R
Units
Min
tPLH
Propagation Delay
M = GND
M = GND
12
12
12
12
14
14
15
15
14
14
15
15
20
20
21
21
24
24
25
25
20
20
18.5
18.5
23
23
23
23
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
Cn to Cn + 4
Propagation Delay
Cn to F
Propagation Delay
An or Bn to G
M, S1, S2 = GND
S0, S3 = 4.5V
M, S0, S3 = GND
S1, S2 = 4.5V
M, S1, S2 = GND
S0, S3 = 4.5V
M, S0, S3 = GND
S1, S2 = 4.5V
M, S1, S3 = GND
S0, S3 = 4.5V
M, S0, S3 = GND
S1, S2 = 4.5V
M, S1, S2 = GND
S0, S3 = 4.5V
M, S0, S3 = GND
S1, S2 = 4.5V
M = 4.5V
Propagation Delay
An or Bn to G
Propagation Delay
An or Bn to P
Propagation Delay
An or Bn to P
Propagation Delay
Ai or Bi to Fi
Propagation Delay
Ai or Bi to Fi
Propagation Delay
Ai or Bi to Fi + 1
Propagation Delay
Ai or Bi to Fi + 1
Propagation Delay
An or Bn to F
Propagation Delay
An or Bn to Cn + 1
Propagation Delay
An or Bn to Cn + 1
Propagation Delay
An or Bn to A = B
M, S1, S2 = GND
S0, S3 = 4.5V
M, S0, S3 = GND
S1, S2 = 4.5V
M, S0, S3 = GND
S1, S2 = 4.5V
ns
RL = 400Ω to 5.0V
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6
Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.600 Wide
Package Number N24A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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1. Life support devices or systems are devices or systems
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instructions for use provided in the labeling, can be rea-
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2. A critical component in any component of a life support
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7
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