ECWF2W154JAQ 概述
Dual BCM PFC Controller 双BCM PFC控制器
ECWF2W154JAQ 数据手册
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FEB388_002
FAN9611/FAN9612 400W Interleaved
Dual BCM PFC Controller
Evaluation Board User Guide
Featured Fairchild Product: FAN9611, FAN9612
Please contact a local Fairchild Sales representative
for an evaluation board.
© 2010 Fairchild Semiconductor Corporation
1
FEB388_FAN9611/12 • Rev. 0.0.2
www.fairchildsemi.com
Table of Contents
1. Overview of the Evaluation Board ............................................................................................. 3
2. Key Features ............................................................................................................................... 4
3. Specifications.............................................................................................................................. 5
4. Test Procedure ............................................................................................................................ 6
5. Schematic.................................................................................................................................... 7
6. Boost Inductor Specification....................................................................................................... 8
7. Line Filter Inductor Specifications ............................................................................................. 9
8. PCB Layout............................................................................................................................... 10
9. Bill of Materials (BOM) ........................................................................................................... 14
10.
Test Results....................................................................................................................... 16
10.1.
Startup..................................................................................................................... 16
Normal Operation ................................................................................................... 18
Line Transient ......................................................................................................... 20
Load Transient ........................................................................................................ 21
Brownout Protection ............................................................................................... 22
Phase Management ................................................................................................. 24
Efficiency................................................................................................................ 27
Harmonic Distortion and Power Factor .................................................................. 28
10.2.
10.3.
10.4.
10.5.
10.6.
10.7.
10.8.
11.
12.
13.
References......................................................................................................................... 30
Ordering Information ........................................................................................................ 30
Revision History ............................................................................................................... 30
© 2010 Fairchild Semiconductor Corporation
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FEB279_FAN9611/12 • Rev. 0.0.2
www.fairchildsemi.com
The following user guide supports the FAN9611/12 400W evaluation board for
interleaved boundary-conduction-mode power-factor-corrected supply. It should be used
in conjunction with the FAN9611/12 datasheet as well as the Fairchild application note
AN-6086 Design Considerations for Interleaved Boundary-Conduction Mode PFC using
FAN9612. Although marked FAN9612, the evaluation board can be interchangeably used
to evaluate either the FAN9611 (10V turn-on threshold) or FAN9612 controller (12.5V
turn-on threshold). Please visit Fairchild’s website at www.fairchildsemi.com for
additional information.
1. Overview of the Evaluation Board
The FAN9611/12 interleaved dual Boundary-Conduction-Mode (BCM) Power-Factor-
Correction (PFC) controllers operate two parallel-connected boost power trains 180º out
of phase. Interleaving extends the maximum practical power level of the control
technique from about 300W to greater than 800W. Unlike the continuous conduction
mode (CCM) technique often used at higher power levels, BCM offers inherent zero-
current switching of the boost diodes (no reverse-recovery losses), which permits the use
of less expensive diodes without sacrificing efficiency. Furthermore, the input and output
filters can be smaller due to ripple current cancellation between the power trains and
doubling of effective switching frequency.
The advanced line feedforward with peak detection circuit minimizes the output voltage
variation during line transients. To guarantee stable operation with less switching loss at
light load, the maximum switching frequency is clamped at 525kHz. Synchronization is
maintained under all operating conditions.
Protection functions include output over-voltage, over-current, open-feedback, under-
voltage lockout, brownout, and redundant latching over-voltage protection. The
FAN9611/12 is available in a lead-free 16-lead SOIC package.
This FAN9611/12 evaluation board is a four-layer board designed for 400W (400V/1A)
rated power. Thanks to the phase management, the efficiency is maintained above 96%
at low-line and high-line, even down to 10% of the rated output power. Efficiency is
96.4% at line voltage 115VAC and 98.2% at 230VAC under full-load conditions.
© 2010 Fairchild Semiconductor Corporation
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2. Key Features
Low Total Harmonic Distortion, High Power Factor
180° Out-of-Phase Synchronization
Automatic Phase Disable at Light Load
1.8A Sink, 1.0A Source, High-Current Gate Drivers
Transconductance (gM) Error Amplifier for Reduced Overshoot
Voltage-Mode Control with (VIN)2 Feed-forward
Closed-Loop Soft-Start with Programmable Soft-Start Time for Reduced Overshoot
Minimum Restart Timer Frequency to Avoid Audible Noise
Maximum Switching Frequency Clamp
Brownout Protection with Soft Recovery
Non-Latching OVP on FB Pin and Second-Level Latching Protection on OVP Pin
Open-Feedback Protection
Over-Current and Power-Limit Protection for Each Phase
Low Startup Current: 80µA Typical
Works with DC, 50Hz to 400Hz AC Inputs
Figure 1.
Block Diagram
© 2010 Fairchild Semiconductor Corporation
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FEB279_FAN9611/12 • Rev. 0.0.2
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3. Specifications
This board has been designed and optimized for the following conditions:
Output Voltage
(Rated Current)
Input Voltage Range
Rated Output Power
VIN Nominal : 85~264VAC
VDD Supply : 13VDC~18VDC
400W
400V-1A
Note:
1. Minimum output voltage during the 20ms hold-up time is 330VDC
.
VLINE = 85~264VAC
VOUT = 400V
fSW > 50kHz
Efficiency > 96% down to 20% load (115VAC)
Efficiency > 97% down to 20% load (230VAC)
PF > 0.99 at full load
The trip points for the built-in protections are set as below in the evaluation board.
The non-latching output OVP trip point is set at 108% of the nominal output voltage.
The latching output OVP trip point is set at 117% of the nominal output voltage.
The line UVLO (brownout protection) trip point is set at 68VAC (10VAC hysteresis).
The pulse-by-pulse current limit for each MOSFET is set at 9.1A.
The maximum power limit is set at ~120% of the rated output power. The phase
management function permits phase shedding/adding ~15% of the nominal output power
for high line (230VAC). This level can be programmed by modifying MOT resistor (R6).
© 2010 Fairchild Semiconductor Corporation
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FEB279_FAN9611/12 • Rev. 0.0.2
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4. Test Procedure
Before testing the board; DC voltage supply for VDD, AC voltage supply for line input,
and DC electric load for output should be connected to the board properly.
1. Supply VDD for the control chip first. It should be higher than 13V (refer to the
specification for VDD turn-on threshold voltage in Table 1).
Table 1.
Specification Excerpt from FAN9611/12 Datasheet
Symbol
Supply
ISTARTUP
IDD
Parameter
Conditions
Min. Typ. Max. Unit
Startup Supply Current
VDD = VON – 0.2V
80
3.7
4
110
5.2
6
µA
mA
mA
V
Operating Current
Output Not Switching
IDD_DYM
Dynamic Operating Current
UVLO Start Threshold, FAN9611
UVLO Start Threshold, FAN9612
UVLO Stop Threshold Voltage
UVLO Hysteresis, FAN9611
UVLO Hysteresis, FAN9612
fSW = 50kHz; CLOAD = 2nF
9.5
12.0
7.0
10.0
12.5
7.5
2.5
5.0
10.5
13.0
8.0
VON
VOFF
VHYS
VDD Increasing
VDD Decreasing
VON – VOFF
V
V
V
V
2. Connect the AC voltage (85~265VAC) to start the FAN9611/12 evaluation board.
Since FAN9611/12 has brownout protection, any input voltages lower than operation
range triggers the protection.
3. Change load current (0~1A) and check the operation.
© 2010 Fairchild Semiconductor Corporation
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5. Schematic
Figure 2.
FAN9611/12 400W Evaluation Board Schematic
© 2010 Fairchild Semiconductor Corporation
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6. Boost Inductor Specification
PA2075NL from Pulse Engineering (www.pulseeng.com)
•
•
•
Core: PQ3230 (Ae=161mm2)
Bobbin: PQ3230
Inductance : 200μH
Figure 3. Boost Inductor used in this FAN9611/12 Evaluation Board
Table 2.
Inductor Turns Specifications
Pin
Turns
N1
5 Æ 3
30
Insulation Tape
N2
2 Æ 4
3
Insulation Tape
© 2010 Fairchild Semiconductor Corporation
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7. Line Filter Inductor Specifications
A : 30mm (max)
B: 15 mm (max)
C: 11 mm
D: 13 mm
E: 15±1 mm
Electrical Specifications (1kHz, 1V)
-
-
-
Inductance: 9.0mH (min.) for each winding
DC resistance: 0.05Ω (max.) for each winding
Number of turns: 0.9mm×2/30.5 turns for each winding
Figure 4.
Line Filter Inductor Specification
Table 3.
Materials List
Material
Component
Manufacturer
UL File Number
Core
T22x14x08
THFN-216
Core T22x14x08, TOMITA
Ta Ya Electric Wire Co,. Ltd.
PACIFIC Wire and cable Co., Ltd.
Tai-1 Electric Wire & Cable Co., Ltd.
Jang Shing Wire Co., Ltd.
E197768
E201757
E85640
UEWN/U
Wire
UEWE
UWY
E174837
Solder
96.5%, Sn, 3%, Ag, 0.5% Cu
Xin Yuan Co., Ltd.
© 2010 Fairchild Semiconductor Corporation
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8. PCB Layout
Figure 5.
First Layer (Top Side)
Figure 6.
Second Layer (Plane Layer)
© 2010 Fairchild Semiconductor Corporation
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FEB388_FAN9611/12 • Rev. 0.0.2
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Figure 7.
Third Layer (Ground layer)
Figure 8.
Fourth Layer (Bottom Side)
© 2010 Fairchild Semiconductor Corporation
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Figure 9.
Top Solder Mask
Figure 10. Bottom Solder Mask
© 2010 Fairchild Semiconductor Corporation
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Figure 11. Top Silkscreen
Figure 12. Bottom Silkscreen
© 2010 Fairchild Semiconductor Corporation
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9. Bill of Materials (BOM)
Qty Reference Part Number
Value
Description
Package Type
Manufacturer
STD
2
1
C1 C6
C2
0.22µF
390nF
CAP, SMD, CERAMIC, 25V, X7R
CAP, SMD, CERAMIC, 25V, X7R
805
805
STD
ECWF2W154JA
Q
2
1
2
C4 C9
150nF
470nF
Cap, 400V, 5%, Polypropylene
CAP, SMD, CERAMIC,25V, X7R
Radial, Thru-Hole
805
Panasonic-ECG
STD
C5
C7 C11
C23
B32914A3474
470nF,330V
Cap, 330VAC, 10%, Polypropylene Box, Thru-Hole
EPCOS
2
2
C8 C13
EETUQ2W221E
220µF
2.2µF
Cap, Alum, Elect.
Radial, Thru-Hole
1206
Panasonic
STD
C10 C14
CAP, SMD, CERAMIC, 25V, X7R
Cap, X series 250VAC, 5%,
Polypropylene
Fuhjyyu Electronic
Industrial Co.
1
C12
HQX104K275R2
0.1µF, 275V
Box, Thru-Hole
1
1
1
C15
C16
C18
15n
0.1µF
1µF
CAP, SMD, CERAMIC,25V, X7R
CAP, SMD, CERAMIC, 25V, X7R
CAP, SMD, CERAMIC,50V, X5R
805
805
805
STD
STD
STD
PHE840MB
6100MB05R17
Cap, X Type, 275VAC, 10%,
Polypropylene
1
C19
0.1µF
Box, Axial
KEMET
CS85-
B2GA471KYNS
2
1
3
C20-21
C22
470pF
1nF
Cap, Ceramic, 250VAC, 10%, Y5P, Disc, Thru-hole
TDK Corporation
STD
CAP, SMD, CERAMIC, 25V, X7R
Diode, 600V, 3A, Std recovery
805
Fairchild
Semiconductor
D1 D3-4
S3J
MBR0540
GBU8J
SMC
Fairchild
Semiconductor
2
1
D2 D8
D5
Diode, Schottky,40V, 500mA
Bridge Rectifier, 600V, 8A
DIODE FAST REC 1A 600V
SOD-123
Thru-Hole
SMA
Fairchild
Semiconductor
Fairchild
Semiconductor
2
D6-7
D10
F1
ES1J
DIODE SCHOTTKY 30V 500MA
SOD-123
Fairchild
Semiconductor
1
MBR0530
31.8201
SOD-123
PCB mount, Thru-
hole
1
Fuseholder, 5x20mm, 250VAC, 10A
Schurter Inc
Heatsink, 13.4degC/W, TO-220 with
Tab-Koolclip for Q2-3
2
H1 H3
H2
534202B33453G
639BG
1"x0.475"x1.18"
1.65"x1.5"
Thru-hole
Aavid Thermalloy
Aavid Thermalloy
TO-220 Heat sink for D5, Bridge
Rectifier
1
On Shore
Technology, Inc.
1
J1
ED100/3DS
Terminal Block, 5MM Vert., 3 Pos.
J2 J8-18
J21-22
3103-1-00-15-00-
00-08-0
Probe-pin, Gold, 0.3" x 40mil dia.,
31mil mounting length
14
3
Thru-Hole
Thru-Hole
Thru-hole
Mill-Max
Custom
Deltron
Deltron
Jumper wire, #16, Insulated, for
current probe measurement
J3-5
Banana Jack, .175, Horizontal,
Insulated_RED
2
J6 J19
J7 J20
571-0500
571-0100
Banana Jack, .175, Horizontal,
Insulated_BLK
2
Thru-hole
SEN HUEI
INDUSTRIAL
CO.,LTD
2
L3-4
TRN-0197
Common Mode Choke
Thru-Hole
2
2
Q1 Q4
Q2-3
ZXTP25020DFL
FDPF18N50
Transistor, PNP, 20V, 1.5A
SOT-23
TO-220
Zetex
MOSFET, NCH, 500V, 18A, 0.265
Ohm
Fairchild
Semiconductor
Continued on following page…
© 2010 Fairchild Semiconductor Corporation
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BOM (Continued)
Qty Reference
Part Number
Value
Description
RES, SMD, 1/8W
Package Type Manufacturer
2
6
R1-2
47kΩ
805
805
STD
STD
R3 R9 R27-
28 R33-34
665kΩ
RES, SMD, 1/8W
1
1
1
2
2
2
1
1
1
1
1
R4
R5
332kΩ
68kΩ
100kΩ
340kΩ
100Ω
15Ω
RES, SMD, 1/8W
RES, SMD, 1/8W
RES, SMD, 1/8W
RES, SMD, 1/8W
RES, SMD, 1/8W
RES, SMD, 1/8W
RES, SMD, 1/8W
RES, SMD, 1/8W
RES, SMD, 1/2W
Thermister, 5Ω
805
STD
STD
STD
STD
STD
STD
STD
STD
STD
EPCOS
STD
805
R6
805
R7-8
R10 R20
R11-12
R15
805
805
805
DNP
49.9Ω
0
805
R16
805
R17
2010
Thru-Hole
805
R18
B57237S0509M000
5Ω
R19
14.7kΩ
RES, SMD, 1/8W
1 inserted
into each
corner of
PCB
LOCKING BOARD SUPPORT 3/4",
1 for each PCB corner
Richco Plastic
Company
4
LCBS-12-01
3103
Standoff
Washer
Nylon Shoulder Washer #4x0.187",
Black
Keystone
Electronics
1
1 at D5, H2
1
1
1 at D5, H2
1 at D5, H2
MLWZ 003
HNZ440
Split Lock Washer, Metric M 3 Zinc Washer
B&F Fastener
B&F Fastener
Nut Hex, #4-40 Zinc
Nut
Screw Machine Phillips, 4-40x1/2"
Zinc
1
1 at D5, H2
PMS 440 0050 PH
Screw
B&F Fastener
FAN9611/12
FEB388 Rev. 0.0.1
Fairchild
Semiconductor
1
2
6
PWB
R1-2
FEB388 PWB, 9.8" x 6.8"
PWB
805
47kΩ
RES, SMD, 1/8W
RES, SMD, 1/8W
STD
R3 R9 R27-
28 R33-34
665kΩ
805
STD
1
1
1
2
2
2
2
1
1
R4
R5
332kΩ
68kΩ
RES, SMD, 1/8W
RES, SMD, 1/8W
RES, SMD, 1/8W
RES, SMD, 1/8W
RES, SMD, 1/8W
RES, SMD, 1/8W
RES, SMD, 1/2W
RES, SMD, 1/8W
RES, SMD, 1/8W
805
805
805
805
805
805
1812
805
805
STD
STD
STD
STD
STD
STD
STD
STD
STD
R6
100kΩ
340kΩ
100Ω
15Ω
R7-8
R10 R20
R11-12
R13-14
R15
0.022Ω
DNP
R16
49.9Ω
Note:
2. DNP = Do not populate. STD = standard components
© 2010 Fairchild Semiconductor Corporation
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10. Test Results
10.1. Startup
Figure 13 and Figure 14 show the startup operation at 115VAC line voltage for no-load and
full-load condition, respectively. Due to the closed-loop soft-start, almost no overshoot is
observed for no-load startup and full-load startup.
Gate Drive 1
COMP
Voltage
Output
Voltage
Line
Current
CH1: Gate Drive 1 Voltage (20V/div), CH2: COMP Voltage (2V/div),
CH3: Output Voltage (200V/div), CH4: Line Current (5A/div), Time (100ms/div)
Figure 13. No-Load Startup at 115VAC
Gate Drive 1
COMP
Voltage
Output
Voltage
Line
Current
CH1: Gate Drive 1 Voltage (20V/div), CH2: COMP Voltage (2V/div),
CH3: Output Voltage (200V/div), CH4: Line Current (10A/div), Time (200ms/div)
Figure 14. Full-Load Startup at 115VAC
© 2010 Fairchild Semiconductor Corporation
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Figure 15 and Figure 16 show the startup operation at 230VAC line voltage for no-load and
full-load conditions, respectively. Due to the closed-loop soft-start, almost no overshoot is
observed for no-load startup and full-load startup.
Gate Drive 1
COMP
Voltage
Output
Voltage
Line
Current
CH1: Gate Drive 1 Voltage (20V/div), CH2: COMP Voltage (2V/div),
CH3: Output Voltage (200V/div), CH4: Line Current (5A/div), Time (100ms/div)
Figure 15. No-Load Startup at 230VAC
Gate Drive 1
COMP
Voltage
Output
Voltage
Line
Current
CH1: Gate Drive 1 Voltage (20V/div), CH2: COMP Voltage (2V/div),
CH3: Output Voltage (200V/div), CH4: Line Current (5A/div), Time (100ms/div)
Figure 16. Full-Load Startup at 230VAC
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10.2. Normal Operation
Figure 17 and Figure 18 show the two inductor currents and sum of two inductor currents
at 115VAC line voltage and full-load conditions. The sum of the inductor currents has
relatively small ripple due to the ripple cancellation of interleaving operation.
IL1
IL2
IL1 + IL2
CH3: Inductor L1 Current (5A/div), CH4: Inductor L2 Current (5A/div),
F1: Sum of Two Inductor Current (5A/div), Time (2ms/div)
Figure 17. Inductor Current Waveforms at Full-Load and 115VAC
IL1
IL2
IL1 + IL2
CH3: Inductor L1 Current (5A/div), CH4: Inductor L2 Current (5A/div),
F1: Sum of Two Inductor Current (5A/div), Time (5μs/div)
Figure 18.
Zoom of Inductor Current Waveforms of Figure 17 at Peak of Line Voltage
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Figure 19 and Figure 20 show the two inductor currents and sum of two
inductor currents at 230VAC line voltage and full-load conditions. The
sum of the inductor currents has relatively small ripple due to the ripple
cancellation of interleaving operation.
IL1
IL2
I
L1 + IL2
CH3: Inductor L1 Current (2A/div), CH4: Inductor L2 Current (2A/div),
F1: Sum of Two Inductor Current (2A/div), Time (2ms/div)
Figure 19. Inductor Current Waveforms at Full-Load and 230VAC
IL1
IL2
IL1 + IL2
CH3: Inductor L1 Current (2A/div), CH4: Inductor L2 Current (2A/div),
F1: Sum of Two Inductor Current (2A/div), Time (2μs/div)
Figure 20. Zoom of Inductor Current Waveforms of Figure 19 at Peak of Line Voltage
© 2010 Fairchild Semiconductor Corporation
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10.3. Line Transient
Figure 21 and Figure 22 show the line transient operation and minimal effect on output
voltage due to the line feed-forward function. When the line voltage changes from
230VAC to 115VAC, about 20V (5% of nominal output voltage) voltage undershoot is
observed. When the line voltage changes from 115VAC to 230VAC, almost no voltage
undershoot is observed.
Rectified
Line
Voltage
VCOMP
VOUT
Line
Current
CH1: Rectified Line Voltage (100V/div), CH2: COMP Voltage (2V/div),
CH3: Output Voltage (100V/div), CH4: Line Current (5A/div), Time (50ms/div)
Figure 21. Line Transient Response at Full-Load Condition (230VAC Æ115VAC
)
Rectified
Line
Voltage
VCOMP
VOUT
Line
Current
CH1: Rectified Line Voltage (100V/div), CH2: COMP Voltage (2V/div),
CH3: Output Voltage (100V/div), CH4: Line Current (5A/div), Time (50ms/div)
Figure 22. Line Transient Response at Full-Load Condition (115VAC Æ230VAC
)
© 2010 Fairchild Semiconductor Corporation
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10.4. Load Transient
Figure 23 and Figure 24 show the load-transient operation. When the output load changes
from 100% to 0%, 26V (6.5% of nominal output voltage) voltage overshoot is observed.
When the output load changes from 0% to 100%, 43V (11% of nominal output voltage)
voltage undershoot is observed.
VOUT
Rectified
Line
Voltage
Line
Current
CH2: Rectified line voltage (100V/div), CH3: Output voltage (100V/div),
CH4: Line current (5A/div), Time (50ms/div)
Figure 23. Load Transient Response at 230VAC (Full Load Æ No Load)
VOUT
Rectified
Line
Voltage
Line
Current
CH2: Rectified Line Voltage (100V/div), CH3: Output Voltage (100V/div),
CH4: Line Current (5A/div), Time (50ms/div)
Figure 24. Load Transient Response at 230VAC (No Load Æ Full Load)
© 2010 Fairchild Semiconductor Corporation
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10.5. Brownout Protection
Figure 25 and Figure 26 show the startup operation at slowly increasing line voltage.
The power supply starts up when the line voltage reaches around 78VAC
.
Line
Voltage
Gate
Drive 1
Line
Current
CH1: Line Voltage (100V/div), CH2: Gate Drive 1 Voltage (20V/div),
CH4: Line Current (5A/div), Time (200ms/div)
Figure 25. Startup Slowly Increasing the Line Voltage
Line
Voltage
Gate
Drive 1
Line
Current
CH1: Line Voltage (100V/div), CH2: Gate Drive 1 Voltage (20V/div),
CH4: Line Current (5A/div), Time (20ms/div)
Figure 26. Shutdown Slowly Decreasing the Line Voltage
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Figure 27 and Figure 28 show the shutdown operation at slowly decreasing line voltage.
The power shuts down when line voltage drops below 68VAC.
Line
Voltage
Gate
Drive 1
Line
Current
CH1: Line Voltage (100V/div), CH2: Gate Drive 1 Voltage (20V/div),
CH4: Line Current (5A/div), Time (200ms/div)
Figure 27. Startup Slowly Increasing the Line Voltage
Line
Voltage
Gate
Drive 1
Line
Current
CH1: Line Voltage (100V/div), CH2: Gate Drive 1 Voltage (20V/div),
CH4: Line Current (5A/div), Time (20ms/div)
Figure 28. Shutdown Slowly Decreasing the Line Voltage
© 2010 Fairchild Semiconductor Corporation
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FEB388_FAN9611/12 • Rev. 0.0.2
www.fairchildsemi.com
10.6. Phase Management
Figure 29 and Figure 30 show the phase-shedding waveforms. As observed, when the gate
drive signal of Channel 2 is disabled, the duty cycle of Channel 1 gate drive signal is
doubled to minimize the line current glitch and guarantee smooth transient.
Gate
Drive 1
Gate
Drive 2
IL1
IL2
CH1: Gate Drive 1 Voltage (20V/div), CH2: Gate Drive 2 Voltage (20V/div),
CH3: Inductor L1 Current (1A/div), CH4: Inductor L2 Current (1A/div), Time (5ms/div)
Figure 29. Phase-Shedding Operation
Gate
Drive 1
Gate
Drive 2
IL1
IL2
CH1: Gate Drive 1 Voltage (20V/div), CH2: Gate Drive 2 Voltage (20V/div),
CH3: Inductor L1 Current (1A/div), CH4: Inductor L2 Current (1A/div), Time (5µs/div)
Figure 30. Phase-Shedding Operation (Zoomed-in Timescale)
© 2010 Fairchild Semiconductor Corporation
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FEB388_FAN9611/12 • Rev. 0.0.2
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Figure 31 and Figure 32 show the phase-adding waveforms. As observed, just before the
channel 2 gate drive signal is enabled, the duty cycle of Channel 1 gate drive signal is
halved to minimize the line current glitch and guarantee smooth transient. In Figure 32,
the first pulse of gate drive 2 during the phase-adding operation is skipped to ensure 180
degree out-of-phase interleaving operation during transient.
Gate
Drive 1
Gate
Drive 2
IL1
IL2
CH1: Gate Drive 1 Voltage (20V/div), CH2: Gate Drive 2 Voltage (20V/div),
CH3: Inductor L1 Current (1A/div), CH4: Inductor L2 Current (1A/div), Time (5ms/div)
Figure 31. Phase-Adding Operation
Gate
Drive 1
Gate
Drive 2
IL1
IL2
CH1: Gate Drive 1 Voltage (20V/div), CH2: Gate Drive 2 Voltage (20V/div),
CH3: Inductor L1 Current (1A/div), CH4: Inductor L2 Current (1A/div), Time (5µs/div)
Figure 32. Phase-Adding Operation (Zoomed-in Timescale)
© 2010 Fairchild Semiconductor Corporation
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FEB388_FAN9611/12 • Rev. 0.0.2
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Figure 33 and Figure 34 show the sum of two-inductor current and line current for
phase shedding and adding, respectively. The small line-current glitch during phase
management exists because the actual average value of inductor current is less than half
of the peak value due to the negative portion of inductor current, as shown in Figure 30
and Figure 32. However, the phase management takes place at relatively light-load
condition and the effect of this phenomenon is negligible.
Gate
Drive 1
Gate
Drive 2
IL1 + IL1
Line
Current
CH1: Gate Drive 1 Voltage (20V/div), CH2: Gate Drive 2 Voltage (20V/div),
CH3: Sum of Two Inductor Currents (1A/div), CH4: Line Current (1A/div), Time (5ms/div)
Figure 33. Phase Shedding and Line Current
Gate
Drive 1
Gate
Drive 2
IL1 + IL1
Line
Current
CH1: Gate Drive 1 Voltage (20V/div), CH2: Gate Drive 2 Voltage (20V/div),
CH3: Sum of Two Inductor Currents (1A/div), CH4: Line Current (1A/div), Time (5ms/div)
Figure 34. Phase Adding Operation and Line Current
© 2010 Fairchild Semiconductor Corporation
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FEB388_FAN9611/12 • Rev. 0.0.2
www.fairchildsemi.com
10.7. Efficiency
Figure 35 through Figure 38 show the measured efficiency of the 400W evaluation board
with and without phase management at input voltages of 115VAC and 230VAC. Phase
management improves the efficiency at light load by up to 7%, depending on the line
voltage and load condition. The phase management thresholds on the test evaluation board
are around 15% of the nominal output power (Figure 35 and Figure 36). They can be
adjusted upwards to achieve a more desirable efficiency profile (Figure 37 and Figure 38)
by increasing the MOT resistor.
Since phase shedding reduces the switching loss by effectively decreasing the switching
frequency at light load, a greater efficiency improvement is achieved at 230VAC, where
switching losses dominate. Relatively less improvement is obtained at 115VAC since the
MOSFET is turned on with zero voltage and switching losses are negligible.
The efficiency measurements include the losses in the EMI filter as well as cable loss;
however, the power consumption of the control IC (<< 1W) is not included since an
external power supply is used for VDD.
FAN9612 Efficiency vs. Load
(230 VAC Input, 400 VDC Output, 400W)
100
95
With Phase Management
Without Phase Management
90
85
0
10
20
30
40
50
60
70
80
90
100
Output Power (%)
Figure 35. Measured Efficiency at 115VAC
(Default Thresholds)
Figure 36. Measured Efficiency at 230VAC
(Default Thresholds)
FAN9612 Efficiency vs. Load
FAN9612 Efficiency vs. Load
(115 VAC Input, 400 VDC Output, 400W)
(230 VAC Input, 400 VDC Output, 400W)
100
100
95
95
With Phase Management
With Phase Management
90
90
Without Phase Management
Without Phase Management
85
85
0
10
20
30
40
50
60
70
80
90
100
0
10
20
30
40
50
60
70
80
90
100
Output Power (%)
Output Power (%)
Figure 37.
Measured Efficiency at 115VAC
(Adjusted Thresholds)
Figure 38.
Measured Efficiency at 230VAC
(Adjusted Thresholds)
© 2010 Fairchild Semiconductor Corporation
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FEB388_FAN9611/12 • Rev. 0.0.2
www.fairchildsemi.com
10.8. Harmonic Distortion and Power Factor
Figure 39 and Figure 40 compare the measured harmonic current with EN61000 class D
and C, respectively, at input voltages of 115VAC and 230VAC. Class D is applied to TV and
PC power, while Class C is applied to lighting applications. As can be observed, both
regulations are met with sufficient margin.
EN61000 Class-D
1.4
1.2
1.0
EN61000-D
0.8
115VAC
0.6
230VAC
0.4
0.2
0.0
3
7
11
15
19
23
27
31
35
39
Harmonic order
Figure 39. Measured Harmonic Current and EN61000 Class-D Regulation
EN61000 Class-C
30%
25%
EN61000-C
20%
115VAC
15%
230VAC
10%
5%
0%
3
7
11
15
19
23
27
31
35
39
Harmonic order
Figure 40. Measured Harmonic Current and EN61000 Class-C Regulation
© 2010 Fairchild Semiconductor Corporation
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FEB388_FAN9611/12 • Rev. 0.0.2
www.fairchildsemi.com
Figure 41 shows the measured power factors at input voltage of 115VAC and 230VAC. As
observed, high power factor above 0.98 is obtained from 100% to 50% load. Table 4 shows
the total harmonic distortion at input voltages of 115VAC and 230VAC.
FAN9612 PowerFactorvs. Load
Figure 41. Measured Power Factor
Total Harmonic Distortion (THD)
Table 4.
Line Voltage
115VAC
100 % Load
9.68%
75 % Load
11.82%
50 % Load
25 % Load
24.08%
15.87%
15.30%
11.36%
12.95%
16.81%
230VAC
© 2010 Fairchild Semiconductor Corporation
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FEB388_FAN9611/12 • Rev. 0.0.2
www.fairchildsemi.com
11. References
Datasheet: FAN9611 / FAN9612 – Interleaved Dual BCM PFC Controllers
AN-6086 – “Design Consideration for interleaved Boundary Conduction Mode
(BCM) PFC using FAN9612”
12. Ordering Information
Orderable Part Number
FEB388
Description
FAN9611/FAN9612 400W Evaluation Board
13. Revision History
Date
Rev. #
0.0.1
Description
August 2010
August 2010
Initial release
0.0.2
Added PCB layout figures
© 2010 Fairchild Semiconductor Corporation
30
FEB388_FAN9611/12 • Rev. 0.0.2
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