ETQ-P6F6R4HFA_技术文档

March 2011

FAN5026

Dual DDR / Dual-Output PWM Controller

Features

Description

The FAN5026 PWM controller provides high efficiency

and regulation for two output voltages adjustable in the

range of 0.9V to 5.5V required to power I/O, chipꢀsets,

and memory banks in highꢀperformance computers,

setꢀtop boxes, and VGA cards. Synchronous

rectification and hysteretic operation at light loads

contribute to high efficiency over a wide range of loads.

Efficiency is enhanced by using MOSFET R_DS(ON)as a

currentꢀsense component.

ꢀ

Highly Flexible, Dual Synchronous Switching PWM

Controller that Includes Modes for:

-

DDR Mode with Inꢀphase Operation for

Reduced Channel Interference

90° Phaseꢀshifted, Twoꢀstage DDR Mode

for Reduced Input Ripple

Dual Independent Regulators, 180° Phase

Shifted

ꢀ

Complete DDR Memory Power Solution

Feedforward ramp modulation, averageꢀcurrent mode

control, and internal feedback compensation provide

fast response to load transients. Outꢀofꢀphase operation

with 180ꢀdegree phase shift reduces input current

ripple. The controller can be transformed into a

complete DDR memory power supply solution by

activating a designated pin. In DDR Mode, one of the

channels tracks the output voltage of another channel

and provides output current sink and source capability

— essential for proper powering of DDR chips. The

buffered reference voltage required by this type of

memory is also provided. The FAN5026 monitors these

outputs and generates separate PGx (power good)

signals when the softꢀstart is completed and the output

is within ±10% of the set point.

-

V_TTTracks V_DDQ/2

V_DDQ/2Buffered Reference Output

Lossless Current Sensing on LowꢀSide MOSFET or

Precision OverꢀCurrent Using Sense Resistor

ꢀ

V_CCUnderꢀVoltage Lockout

Wide Input Range: 3V to 16V

Excellent Dynamic Response with Voltage

Feedforward and Average CurrentꢀMode Control

ꢀ

PowerꢀGood Signal

Supports DDRꢀII and HSTL

28ꢀLead ThinꢀShrink SmallꢀOutline Package

Overꢀvoltage protection prevents the output voltage

from exceeding 120% of the set point. Normal operation

is automatically restored when overꢀvoltage conditions

cease. Underꢀvoltage protection latches the chip off

when output drops below 75% of the set value after the

softꢀstart sequence for this output is completed. An

adjustable overꢀcurrent function monitors the output

current by sensing the voltage drop across the lower

MOSFET. If precision currentꢀsensing is required, an

external currentꢀsense resistor may be used.

Applications

ꢀ

DDR V_DDQand V_TTVoltage Generation

PC Dual Power Supply

Server DDR Power

Desktop Computer

Graphics Cards

Related Resources

ꢀ

Application Note — AN-6002 Component

Calculations and Simulation Tools

Ordering Information

Operating

Part Number

Temperature

Range

Package

28ꢀLead ThinꢀShrink SmallꢀOutline Package (TSSOP)

Packing Method

Tape and Reel

FAN5026MTCX

ꢀ40 to +85°C

FAN5026 • Rev. 1.0.8

www.fairchildsemi.com

Block Diagrams

Figure 1. Dual-Output Regulator

Figure 2. Typical Application

FAN5026 • Rev. 1.0.8

www.fairchildsemi.com

2

Pin Configuration

Figure 3. TSSOP-28

Pin Definitions

Pin #

Name

Description

Analog Ground. This is the signal ground reference for the IC. All voltage levels are measured

with respect to this pin

1

AGND

2

27

3

LDRV1

LDRV2

PGND1

PGND2

SW1

Low-Side Drive. The lowꢀside (lower) MOSFET driver output. Connect to gate of lowꢀside

MOSFET.

Power Ground. The return for the lowꢀside MOSFET driver. Connect to source of lowꢀside

MOSFET.

26

4

Switching Node. Return for the highꢀside MOSFET driver and a current sense input. Connect

to source of highꢀside MOSFET and lowꢀside MOSFET drain.

25

5

SW2

HDRV1

HDRV2

BOOT1

BOOT2

ISNS1

ISNS2

High-Side Drive. Highꢀside (upper) MOSFET driver output. Connect to gate of highꢀside

MOSFET.

24

6

BOOT. Positive supply for the upper MOSFET driver. Connect as shown in Figure 4.

23

7

Current-Sense Input. Monitors the voltage drop across the lower MOSFET or external sense

resistor for current feedback.

22

8

21

9

EN1

EN2

Enable. Enables operation when pulled to logic HIGH. Toggling EN resets the regulator after a

latched fault condition. These are CMOS inputs whose state is indeterminate if left open.

GND

Ground

20

10

19

VSEN1

VSEN2

Output Voltage Sense. The feedback from the outputs; used for regulation as well as PG,

underꢀvoltage, and overꢀvoltage protection and monitoring.

Continued on the following page…

FAN5026 • Rev. 1.0.8

www.fairchildsemi.com

3

Pin Definitions

Pin #

Name

Description

11

12

17

ILIM1

SS1

Current Limit 1. A resistor from this pin to GND sets the current limit.

Soft Start. A capacitor from this pin to GND programs the slew rate of the converter during

initialization. During initialization, this pin is charged with a 5mA current source.

SS2

DDR Mode Control. HIGH = DDR Mode. LOW = two separate regulators operating 180

degrees out of phase.

13

14

15

DDR

VIN

Input Voltage. Normally connected to the battery, providing voltage feedforward to set the

amplitude of the internal oscillator ramp. When using the IC for twoꢀstep conversion from 5V

input, connect through 100Kꢀ resistor to ground, which sets the appropriate ramp gain and

synchronizes the channels 90° out of phase.

Power-Good Flag. An openꢀdrain output that pulls LOW when V_SENis outside a ±10% range of

the 0.9V reference.

PG1

Power-Good 2. When not in DDR Mode, openꢀdrain output that pulls LOW when the V_OUTis

out of regulation or in a fault condition.

PG2 /

REF2OUT

16

Reference Out 2. When in DDR Mode, provides a buffered output of REF2. Typically used as

the V_DDQ/2reference.

Current Limit 2. When not in DDR Mode, a resistor from this pin to GND sets the current limit.

ILIM2 /

REF2

18

28

Reference for reg #2 when in DDR Mode. Typically set to V_OUT1/2

.

VCC. This pin powers the chip as well as the LDRV buffers. The IC starts to operate when

voltage on this pin exceeds 4.6V (UVLO rising) and shuts down when it drops below 4.3V

(UVLO falling).

VCC

Block Diagram

Figure 4. IC Block Diagram

FAN5026 • Rev. 1.0.8

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4

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device

reliability. The absolute maximum ratings are stress ratings only.

Symbol

V_CC

Parameter

V_CCSupply Voltage

Min.

Max.

6.5

Unit

V

V_IN

V_INSupply Voltage

18

V

BOOT, SW, ISNS, HDRV

BOOTx to SWx

24

V

6.5

V

All Other Pins

ꢀ0.3

ꢀ40

ꢀ65

V_CC+0.3

+150

+300

V

T_J

T_STG

T_L

Junction Temperature

Storage Temperature

Lead Temperature (Soldering,10 Seconds)

ºC

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended

operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not

recommend exceeding them or designing to Absolute Maximum Ratings.

Symbol

V_CC

Parameter

V_CCSupply Voltage

Min.

Typ.

Max.

5.25

16

Unit

V

4.75

5.00

V_IN

V_INSupply Voltage

V

T_A

Ambient Temperature

ꢀ40

+85

90

°C

Θ_JA

Thermal Resistance, Junction to Ambient

°C/W

FAN5026 • Rev. 1.0.8

www.fairchildsemi.com

5

Electrical Characteristics

Recommended operating conditions, unless otherwise noted.

Symbol

Parameter

Conditions

Min. Typ. Max. Units

Power Supplies

LDRV, HDRV Open, V_SENForced

Above Regulation Point

2.2

3.0

ꢁA

I_VCC

I_SINK

V_CCCurrent

Shutdown (ENꢀ0)

V_IN= 15V

30

ꢁA

V

V_INCurrent, Sinking

10

I_SOURCEV_INCurrent, Sourcing

V_IN= 0V

ꢀ15

ꢀ30

1

I_SD

V_INCurrent, Shutdown

Rising V_CC

Falling

4.30

4.10

4.55

4.25

300

4.75

4.45

V_UVLO

UVLO Threshold

V

V_UVLOH

Oscillator

f_osc

UVLO Hysteresis

mV

Frequency

255

300

2

345

KHz

V

V_IN= 16V

V_IN= 5V

V_PP

V_RAMP

G

Ramp Amplitude

Ramp Offset

1.25

0.5

125

250

V

mV/V

V_IN≤ 3V

Ramp / V_INGain

1V < V_IN< 3V

Reference and Soft-Start

V_REFInternal Reference Voltage

I_SS

0.891 0.900 0.909

V

ꢁA

V

SoftꢀStart Current

At Startup

5

V_SS

SoftꢀStart Complete Threshold

1.5

PWM Converters

Load Regulation

V_SENBias Current

UVLO_TSDUnderꢀVoltage Shutdown

I_OUTXfrom 0 to 5A, V_INfrom 5 to 15V

ꢀ2

50

+2

120

80

%

nA

%

I_SEN

80

75

% of Set Point, 2ꢁs Noise Filter

70

UVLO

I_SNS

OverꢀVoltage Threshold

OverꢀCurrent Threshold

Minimum Duty Cycle

115

112

10

120

140

125

168

%

ꢁA

%

R_ILIM= 68.5Kꢀ, Figure 12

Output Drivers

Sourcing

Sinking

12

2.4

12

15

4.0

15

HDRV Output Resistance

ꢀ

Sourcing

Sinking

LDRV Output Resistance

1.2

2.0

Power-Good Output and Control Pins

Lower Threshold

% of Set Point, 2ꢁs Noise Filter

IPG = 4mA

ꢀ86

ꢀ94

116

0.5

1

%

V

Upper Threshold

108

PG Output Low

Leakage Current

V_PULLUP= 5V

ꢁA

%

V_REF2

PG2/REF2OUT Voltage

99.00

2

1.01

DDR = 1, 0 mA < I_REF2OUT≤10mA

DDR, EN Inputs

V_INH

V_INL

Input High

Input Low

V

0.8

FAN5026 • Rev. 1.0.8

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6

Typical Application

Figure 5. DDR Regulator Application

Table 1. DDR Regulator BOM

Description

Qty.

Ref.

Vendor

Part Number

1

2

1

2

1

2

3

1

2

1

2

1

2

1

C1

AVX

Any

AVX

Any

TPSV686*025#0150

Capacitor 68ꢁf, Tantalum, 25V, ESR 150mꢀ

Capacitor 10nf, Ceramic

C2, C3

C4

TAJB686*006

Capacitor 68ꢁf, Tantalum, 6V, ESR 1.8ꢀ

Capacitor 150nF, Ceramic

Capacitor 180ꢁf, Specialty Polymer 4V, ESR 15mꢀ

Capacitor 1000ꢁf, Specialty Polymer 4V, ESR 10mꢀ

Capacitor 0.1ꢁF, Ceramic

C5, C7

C6A, C6B⁽¹⁾Panasonic

EEFUE0G181R

C8

Kemet

T510E108(1)004AS4115

C9

Any

R1, R2, R3

R3

Any

1.82Kꢀ, 1% Resistor

Any

56.2Kꢀ, 1% Resistor

R4

Any

10Kꢀ, 5% Resistor

R5

Any

3.24Kꢀ, 1% Resistor

R7, R8

D1, D2

L1

Any

1.5Kꢀ, 1% Resistor

Schottky Diode 30V

Fairchild Semiconductor

Panasonic

BAT54

ETQꢀP6F6R4HFA

ETQꢀP6F0R8LFA

FDS6986AS⁽²⁾

FAN5026

Inductor 6.4ꢁH, 6A, 8.64mꢀ

Inductor 0.8ꢁH, 6A, 2.24mꢀ

Dual MOSFET with Schottky

DDR Controller

L2

Panasonic

Q1, Q2

U1

Fairchild Semiconductor

Notes:

1. C6 = 2 X 180ꢁF in parallel.

2. Suitable for typical notebook computer application of 4A continuous, 6A peak for V_DDQ. If continuous operation

above 6A is required, use single SOꢀ8 packages. For more information, refer to the Power MOSFET Selection

Section and use AN-6002 for design calculations.

FAN5026 • Rev. 1.0.8

www.fairchildsemi.com

7

Typical Applications (Continued)

Figure 6. Dual Regulator Application

Table 2. Dual Regulator BOM

Description

Qty.

Ref.

Vendor

Part Number

1

2

1

2

1

3

2

1

C1

AVX

Any

AVX

Any

Sanyo

Any

TPSV686*025#095

Capacitor 68ꢁf, Tantalum, 25V, ESR 95mꢀ

Capacitor 10nf, Ceramic

Capacitor 68ꢁf, Tantalum, 6V, ESR 1.8ꢀ

Capacitor 150nF, Ceramic

Capacitor 330ꢁf, Poscap, 4V, ESR 40mꢀ

Capacitor 0.1ꢁF, Ceramic

56.2Kꢀ, 1% Resistor

C2, C3

C4

TAJB686*006

4TPB330ML

C5, C7

C6, C8

C9

R1, R2

R3

10Kꢀ, 5% Resistor

R4

3.24Kꢀ, 1% Resistor

R5, R8, R9

R6, R7

D1, D2

L1, L2

Q1, Q2

U1

1.82Kꢀ, 1% Resistor

1.5Kꢀ, 1% Resistor

Schottky Diode 30V

Fairchild Semiconductor

Panasonic

BAT54

ETQꢀP6F6R4HFA

FDS6986AS⁽³⁾

FAN5026

Inductor 6.4ꢁH, 6A, 8.64mꢀ

Dual MOSFETs with Schottky

DDR Controller

Fairchild Semiconductor

Note:

3. If currents above 4A continuous are required, use single SOꢀ8 packages. For more information, refer to the

Power MOSFET Selection Section and AN-6002 for design calculations.

FAN5026 • Rev. 1.0.8

www.fairchildsemi.com

8

Circuit Description

Overview

CLK

The FAN5026 is a multiꢀmode, dualꢀchannel PWM

controller intended for graphic chipset, SDRAM, DDR

DRAM, or other lowꢀvoltage power applications in

modern notebook, desktop, and subꢀnotebook PCs.

The IC integrates control circuitry for two synchronous

buck converters. The output voltage of each controller

can be set in the range of 0.9V to 5.5V by an external

resistor divider.

V

DDQ

V

TT

Figure 7. Noise-Susceptible 180° Phasing

for DDR1

Inꢀphase operation is optimal to reduce interꢀconverter

interference when V_INis higher than 5V, (when V_INis

from a battery), as shown in Figure 8. Because the duty

cycle of PWM1 (generating V_DDQ) is short, the switching

point occurs far away from the decision point for the V_TT

regulator, whose duty cycle is nominally 50%.

The two synchronous buck converters can operate from

an unregulated DC source (such as a notebook

battery), with voltage ranging from 5.0V to 16V, or from

a regulated system rail of 3.3V to 5.0V. In either mode,

the IC is biased from a +5V source. The PWM

modulators use an average currentꢀmode control with

input voltage feedforward for simplified feedback loop

compensation and improved line regulation. Both PWM

controllers have integrated feedback loop compensation

that reduces the external components needed.

CLK

V

DDQ

The FAN5026 can be configured to operate as a

complete DDR solution. When the DDR pin is set HIGH,

the second channel provides the capability to track the

output voltage of the first channel. The PWM2 converter

is prevented from going into Hysteretic Mode if the DDR

pin is HIGH. In DDR Mode, a buffered reference voltage

(buffered voltage of the REF2 pin), required by DDR

memory chips, is provided by the PG2 pin.

V

TT

Figure 8. Optimal In-Phase Operation for DDR1

When V_IN≈ 5V, 180° phaseꢀshifted operation can be

rejected for the reasons demonstrated in Figure 7.

Inꢀphase operation with V_IN≈ 5V is even worse, since

the switch point of either converter occurs near the

switch point of the other converter, as seen in Figure 9.

In this case, as V_INis a little higher than 5V, it tends to

cause early termination of the V_TTpulse width.

Conversely, the V_TTswitch point can cause early

termination of the V_DDQpulse width when V_INis slightly

lower than 5V.

Converter Modes and Synchronization

Table 3. Converter Modes and Synchronization

PWM 2

w.r.t.

PWM1

VIN

DDR

Mode

V_IN

CLK

DDR1

DDR2

DUAL

Battery

+5V

V_IN

HIGH

LOW

IN PHASE

R to

GND

+90°

V_DDQ

ANY

V_IN

+180°

V

TT

When used as a dual converter, as shown in Figure 6,

outꢀofꢀphase operation with 180ꢀdegree phase shift

reduces input current ripple.

Figure 9. Noise-Susceptible In-Phase Operation

for DDR2

These problems are solved by delaying the second

converter’s clock by 90°, as shown in Figure 10. In this

way, all switching transitions in one converter take place

far away from the decision points of the other converter.

For “twoꢀstep” conversion (where the V_TTis converted

from V_DDQas in Figure 5) used in DDR Mode, the duty

cycle of the second converter is nominally 50% and the

optimal phasing depends on V_IN. The objective is to

keep noise generated from the switching transition in

one converter from influencing the "decision" to switch

in the other converter.

CLK

V_DDQ

When V_INis from the battery, it’s typically higher than

7.5V. As shown in Figure 7, 180° operation is

undesirable because the turnꢀon of the V_DDQconverter

occurs very near the decision point of the V_TTconverter.

V

TT

Figure 10. Optimal 90° Phasing for DDR2

FAN5026 • Rev. 1.0.8

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9

Since

Initialization and Soft Start

ꢄ_ꢅꢆꢇꢈ∙ ꢀ_{ꢈꢁ ꢆꢃ}

(

)

Assuming EN is HIGH, FAN5026 is initialized when V_CC

exceeds the rising UVLO threshold. Should V_CCdrop

below the UVLO threshold, an internal powerꢀon reset

function disables the chip.

ꢄꢁꢃꢁ =

(3b)

(3c)

(3d)

100 + ꢀ_{ꢁꢂꢃꢁꢂ}

and at the ILIM 0.9V threshold:

The voltage at the positive input of the error amplifier is

limited by the voltage at the SS pin, which is charged

with a 5ꢁA current source. Once C_SShas charged to

V_REF(0.9V) the output voltage is in regulation. The time

it takes SS to reach 0.9V is:

0.9

10.8

ꢄꢁꢃꢁ = 12 ∙

=

ꢀ_ꢄꢅꢄꢉꢀ_ꢄꢅꢄꢉ

therefore:

10.8 100 + ꢀ_{ꢁꢂꢃꢁꢂ}

ꢄ_ꢅꢆꢇꢈ

=

∙

0.9xC_SS

t_0.9

=

ꢀ_ꢄꢅꢄꢉ

ꢀ_{ꢈꢁ(ꢆꢃ)}

(1)

5

where t_0.9is in seconds if C_SSis in ꢁF.

Current limit (I_LIMIT) should be set high enough to allow

inductor current to rise in response to an output load

transient. Typically, a factor of 1.2 is sufficient. In

addition, since I_LIMITis a peak current cutꢀoff value,

multiply I_LOAD(MAX)by the inductor ripple current (e.g.

When SS reaches 1.5V, the powerꢀgood outputs are

enabled and Hysteretic Mode is allowed. The converter

is forced into PWM Mode during softꢀstart.

25%). For example, in Figure 6, the target for I_LIMIT

:

Current Processing Section

The following discussion refers to Figure 12.

I_LIMIT> 1.2 x 1.25 x 1.6 x 2A 5A

≈

The current through the R_SENSEresistor (I_SNS) is

sampled (typically 400ns) after Q2 is turned on, as

shown in Figure 12. That current is held and summed

with the output of the error amplifier. This effectively

creates a currentꢀmode control loop. The resistor

connected to ISNSx pin (R_SENSE) sets the gain in the

current feedback loop. For stable operation, the voltage

induced by the current feedback at the PWM

comparator input should be set to 30% of the ramp

amplitude at maximum load current and line voltage.

The following expression estimates the recommended

value of R_SENSEas a function of the maximum load

current (I_LOAD(MAX)) and the value of the MOSFET

(4)

10.8 100 + ꢀ_{ꢁꢂꢃꢁꢂ}

ꢀ_ꢄꢅꢄꢉ

=

∙

ꢄ_{ꢅꢄꢉꢄꢏ}

ꢀ_{ꢈꢁ(ꢆꢃ)}

Since the tolerance on the current limit is largely

dependent on the ratio of the external resistors, it is

fairly accurate if the voltage drop on the switchingꢀnode

side of R_SENSEis an accurate representation of the load

current. When using the MOSFET as the sensing

element, the variation of R_DS(ON)causes proportional

variation in the I_SNS. This value varies from device to

device and has

a

typical junction temperature

R_DS(ON)

:

coefficient of about 0.4%/°C (consult the MOSFET

datasheet for actual values), so the actual current limit

set point decreases proportional to increasing MOSFET

die temperature. A factor of 1.6 in the current limit set

point should compensate for MOSFET R_DS(ON)

variations, assuming the MOSFET heat sinking keeps

its operating die temperature below 125°C.

ꢄ_{ꢅꢆꢇꢈ (ꢉꢇꢊ )}∙ ꢀ_{ꢈꢁ(ꢆꢃ)}∙ 4.1ꢋ

ꢀ_{ꢁꢂꢃꢁꢂ}

=

− 100

(2a)

30% ∙ 0.125 ∙ ꢌ

ꢄꢃ(ꢉꢇꢊ )

R_SENSEmust, however, be kept higher than:

ꢄ_{ꢅꢆꢇꢈ (ꢉꢇꢊ )}∙ ꢀ_{ꢈꢁ(ꢆꢃ)}

ꢀ_{ꢁꢂꢃꢁꢂ}

=

− 100

Q2

(2b)

150ꢁꢇ

LDRV

R_SENSE

ISNS

The 100ꢂ is the internal resistor in series with the

ISNSx pins and has ±15% typical variation. Because

R_SENSEis in series with the internal 100ꢂ resistor, the

gain in the current feedback loop and the current limit

accuracy is affected if R_SENSEis close to 100ꢂ.

PGND

Setting the Current Limit

A ratio of I_SNSis compared to the current established

when a 0.9V internal reference drives the ILIM pin. The

threshold is determined as follows:

Figure 11. Improving Current-Sensing Accuracy

More accurate sensing can be achieved by using a

resistor (R1) instead of the R_DS(ON)of the FET, as shown

in Figure 11. This approach causes higher losses, but

yields greater accuracy in both V_DROOPand I_LIMIT. R1 is a

low value resistor (e.g. 10mꢀ).

ꢄꢁꢃꢁ

9

4

3

(3a)

=

ꢄꢅꢄꢉ ꢍꢎ ꢄꢁꢃꢁ = 12 ∙ ꢄꢅꢄꢉ

FAN5026 • Rev. 1.0.8

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10

voltage excursion is detected, limiting the maximum

duty cycle to:

Duty Cycle Clamp

During severe load increase, the error amplifier output

can go to its upper limit, pushing a duty cycle to almost

100% for significant amount of time. This could cause a

large increase of the inductor current and lead to a long

recovery from a transient, overꢀcurrent condition, or

even to a failure at especially high input voltages. To

prevent this, the output of the error amplifier is clamped

to a fixed value after two clock cycles if severe output

V













2.4

V_IN

OUT

DC

=

+

(5)

MAX

V

IN

This is designed to not interfere with normal PWM

operation. When FPWM is grounded, the duty cycle

clamp is disabled and the maximum duty cycle is 87%.

Figure 12. Current Limit / Summing Circuits

There must be a lowꢀresistance, lowꢀinductance path

between the driver pin and the MOSFET gate for the

adaptive deadꢀtime circuit to function properly. Any

delay along that path subtracts from the delay

generated by the adaptive deadꢀtime circuit and shootꢀ

through may occur.

Gate Driver Section

The adaptive gate control logic translates the internal

PWM control signal into the MOSFET gate drive

signals, providing necessary amplification, level shifting,

and shootꢀthrough protection. Also, it has functions that

optimize the IC performance over a wide range of

operating conditions. Since MOSFET switching time

can vary dramatically from type to type and with the

input voltage, the gate control logic provides adaptive

dead time by monitoring the gateꢀtoꢀsource voltages of

both upper and lower MOSFETs. The lower MOSFET

drive is not turned on until the gateꢀtoꢀsource voltage of

the upper MOSFET has decreased to less than

approximately 1V. Similarly, the upper MOSFET is not

turned on until the gateꢀtoꢀsource voltage of the lower

MOSFET has decreased to less than approximately 1V.

This allows a wide variety of upper and lower MOSFETs

Frequency Loop Compensation

Due to the implemented currentꢀmode control, the

modulator has a singleꢀpole response with ꢀ1 slope at

frequency determined by load:

1

f_PO

=

(6)

2π R_OC_O

where R_Ois load resistance; C_Ois load capacitance.

to be used without

a concern for simultaneous

conduction or shootꢀthrough.

FAN5026 • Rev. 1.0.8

www.fairchildsemi.com

11

For this type of modulator, a Typeꢀ2 compensation

circuit is usually sufficient. To reduce the number of

external components and simplify the design, the PWM

controller has an internally compensated error amplifier.

Figure 13 shows a Typeꢀ2 amplifier and its response

with the responses of a currentꢀmode modulator and

the converter. The Typeꢀ2 amplifier, in addition to the

pole at the origin, has a zeroꢀpole pair that causes a flat

gain region at frequencies between zero and the pole.

If a larger inductor value or lowꢀESR values are

required by the application, additional phase margin can

be achieved by putting a zero at the LC crossover

frequency. This can be achieved with a capacitor across

the feedback resistor (e.g. R5 from Figure 6), as shown

in Figure 14.

L(OUT)

V_OUT

R5 C(Z)

R6

C(OUT)

VSEN

1

f_Z=

f_P=

= 6kHz

(7)

(8)

2π R₂C₁

1

= 600kHz

Figure 14. Improving Phase Margin

The optimal value of C(Z) is:

2πR₂C₂

This region is also associated with phase “bump” or

reduced phase shift. The amount of phaseꢀshift

reduction depends on the width of the region of flat gain

and has a maximum value of 90°. To further simplify the

converter compensation, the modulator gain is kept

independent of the input voltage variation by providing

feedforward of V_INto the oscillator ramp.

L(OUT)×C(OUT)

(9)

C(Z) =

R

Protections

The converter output is monitored and protected

against extreme overload, shortꢀcircuit, overꢀvoltage,

and underꢀvoltage conditions.

The zero frequency, the amplifier highꢀfrequency gain,

and the modulator gain are chosen to satisfy most

typical applications. The crossover frequency appears

at the point where the modulator attenuation equals the

amplifier highꢀfrequency gain. The system designer

must specify the output filter capacitors to position the

load main pole somewhere within a decade lower than

the amplifier zero frequency. With this type of

compensation, plenty of phase margin is achieved due

to zeroꢀpole pair phase “boost.”

A sustained overload on an output sets the PGx pin

LOW and latchesꢀoff the regulator on which the fault

occurs. Operation can be restored by cycling the V_CC

voltage or by toggling the EN pin.

If V_OUTdrops below the underꢀvoltage threshold, the

regulator shuts down immediately.

C2

Over-Current Sensing

C1

R2

If the circuit’s currentꢀlimit signal (“ILIM det” in Figure

12) is HIGH at the beginning of a clock cycle, a pulseꢀ

skipping circuit is activated and HDRV is inhibited. The

circuit continues to pulse skip in this manner for the

next eight clock cycles. If, at any time from the ninth to

the sixteenth clock cycle, the ILIM det is again reached;

the overꢀcurrent protection latch is set, disabling the

regulator. If ILIM det does not occur between cycles

nine and sixteen, normal operation is restored and the

overꢀcurrent circuit resets itself.

R1

V_IN

EA Out

REF

C

o

n

v

e

r

e

r

o

r

t

a

e

m

r

p

modulator

18

14

0

f

P

P0

Z

Figure 13. Compensation

Conditional stability may occur only when the main load

pole is positioned too much to the left on the frequency

axis due to excessive output filter capacitance. In this

case, an ESR zero placed within the 10kHz to 50kHz

range gives some additional phase boost. Fortunately,

there is an opposite trend in mobile applications to keep

the output capacitor as small as possible.

Figure 15. Over-Current Protection Waveforms

FAN5026 • Rev. 1.0.8

www.fairchildsemi.com

12

Similarly, if an output shortꢀcircuit or severe load

transient causes the output to drop to less than 75% of

the regulation set point, the regulator shuts down.

Over-Voltage / Under-Voltage Protection

Should the V_SNSvoltage exceed 120% of V_REF(0.9V)

due to an upper MOSFET failure or for other reasons,

the overꢀvoltage protection comparator forces LDRV

HIGH. This action actively pulls down the output voltage

and, in the event of the upper MOSFET failure,

eventually blows the battery fuse. As soon as the output

voltage drops below the threshold, the OVP comparator

is disengaged.

Over-Temperature Protection

The chip incorporates an overꢀtemperature protection

circuit that shuts the chip down if a die temperature of

about 150°C is reached. Normal operation is restored at

die temperature below 125°C with internal powerꢀon

reset asserted, resulting in a full softꢀstart cycle.

This OVP scheme provides a ”soft” crowbar function,

which accommodates severe load transients and does

not invert the output voltage when activated

a common problem for latched OVP schemes.

—

Design and Component Selection Guidelines

As an initial step, define the operating input voltage

range, output voltage, and minimum and maximum load

currents for the controller.

for this example, use:

V_IN= 12,V_OUT= 2.5

ꢂI = 25% • 6A = 1.5A

f_SW= 300KHz

(14)

(15)

Setting the Output Voltage

The internal reference voltage is 0.9V. The output is

divided down by a voltage divider to the VSEN pin (for

example, R5 and R6 in Figure 5). The output voltage

therefore is:

therefore:

L ≈ 4.4ꢁH

V_OUT− 0.9V

0.9V

R6

Output Capacitor Selection

(10)

=

R5

The output capacitor serves two major functions in a

switching power supply. Along with the inductor, it filters

the sequence of pulses produced by the switcher and it

supplies the load transient currents. The requirements

are usually dictated by ESR, inductor ripple current (ꢂI),

and the allowable ripple voltage (ꢂV):

To minimize noise pickup on this node, keep the

resistor to GND (R6) below 2K; for example, R6 at

1.82Kꢀ. Then choose R5:

(

1.82Kꢀ

)

(

V

− 0.9

)

OUT

R5 =

= 3.24Kꢀ

(11)

0.9

ꢂV

ꢂI

(16)

ESR <

For DDR applications converting from 3.3V to 2.5V or

other applications requiring high duty cycles, the duty

cycle clamp must be disabled by tying the converter’s

FPWM to GND. When converter’s FPWM is at GND,

the converter’s maximum duty cycle is greater than

90%. When using as a DDR converter with 3.3V input,

set up the converter for inꢀphase synchronization by

tying the VIN pin to +5V.

In addition, the capacitor’s ESR must be low enough to

allow the converter to stay in regulation during a load

step. The ripple voltage due to ESR for the converter in

Figure 6 is 120mV_PP. Some additional ripple appears

due to the capacitance value itself:

ꢂI

ꢂV =

(17)

C

×8× f

SW

OUT

Output Inductor Selection

The minimum practical output inductor value keeps the

inductor current just on the boundary of continuous

conduction at some minimum load. Industry standard

practice is to choose the minimum current somewhere

from 15% to 35% of the nominal current. At light load,

the controller can automatically switch to Hysteretic

Mode to sustain high efficiency. The following equations

select the proper value of the output filter inductor:

which is only about 1.5mV for the converter in Figure 6

and can be ignored.

The capacitor must also be rated to withstand the RMS

current, which is approximately 0.3 X (ꢂI), or about

400mA, for the converter in Figure 6. Highꢀfrequency

decoupling capacitors should be placed as close to the

loads as physically possible

.

ꢂV

Input Capacitor Selection

The input capacitor should be selected by its ripple

current rating.

OUT

(12)

ꢂI = 2×1

=

MIN

ESR

where ꢂI is the inductor ripple current and ꢂV_OUTis the

maximum ripple allowed:

V

− V

V

OUT

IN

OUT

L =

×

(13)

f

× ꢂI

V

IN

SW

FAN5026 • Rev. 1.0.8

www.fairchildsemi.com

13

(Q_G). C_ISS= C_GD+ C_GSand it controls t1, t2, and t4

timing. C_GDreceives the current from the gate driver

during t3 (as V_DSis falling). The gate charge (Q_G)

parameters on the lower graph are either specified in or

can be derived from MOSFET datasheets.

Two-Stage Converter Case

In DDR Mode (Figure 5), the V_TTpower input is

powered by the V_DDQoutput; therefore all of the input

capacitor ripple current is produced by the V_DDQ

converter. A conservative estimate of the output current

required for the 2.5V regulator is:

Assuming switching losses are about the same for both

the rising edge and falling edge, Q1’s switching losses

occur during the shaded time when the MOSFET has

voltage across it and current through it.

I

VTT

(18)

I

= I

+

VDDQ

REGI

2

These losses are given by:

As an example, if the average I_VDDQis 3A and average

I_VTTis 1A, I_VDDQcurrent is about 3.5A. If average input

voltage is 16V, RMS input ripple current is:

P_UPPER= P_SW+ P_COND

(25)

V

×I

L











DS

I

= I

D − D²

2

P

=

× 2× t

f

SW

(26)

(27)

^s



SW

(19)

RMS

OUT(MAX)

where D is the duty cycle of the PWM1 converter and:

V_OUT

2

P_COND

=

×I_OUT×R_DS(ON)

V_OUT

2.5

V

IN

D <

=

(20)

(21)

where:

V_IN

12

P_UPPERis the upper MOSFET’s total losses and PSW

and P_CONDare the switching and conduction losses for a

given MOSFET;

therefore:





 ²



2.5

12

I_RMS= 3.5

−

= 1.42A

R_DS(ON)is at the maximum junction temperature (T_J);

and









12

t_Sis the switching period (rise or fall time), shown as t2

and t3 in Figure 16.

Dual Converter 180° Phased

In Dual Mode (shown in Figure 5), both converters

contribute to the capacitor input ripple current. With

each converter operating 180° out of phase, the RMS

currents add in the following fashion:

The driver’s impedance and C_ISSdetermine t2, while

t3’s period is controlled by the driver’s impedance and

Q_GD. Since most of t_Soccurs when V_GS= V_SP, use a

constant current assumption for the driver to simplify

the calculation of t_S:

2

I

= I

+ I

or

(22)

RMS

RMS(1)

RMS(2)

2

C

C_GD

C_ISS

ISS

V_DS

2

²D₁− D₁

)

+

(

I₂

)

(

²D₂− D₂

)

(23)

I_RMS

=

(I₁

)

(

which, for the dual 3A converters of Figure 6, calculates:

I_RMS= 1.51A

(24)

Power MOSFET Selection

I_D

Losses in a MOSFET are the sum of its switching (P_SW

and conduction (P_COND) losses.

)

Q_GS

Q_GD

In typical applications, the FAN5026 converter’s output

voltage is low with respect to its input voltage.

Therefore, the lower MOSFET (Q2) is conducting the

full load current for most of the cycle. Q2 should

therefore be selected to minimize conduction losses,

4.5V

V_SP

V_TH

Q_G(SW)

V_GS

thereby selecting a MOSFET with low R_DS(ON)

.

t1

t2

t3

t4

t5

In contrast, the highꢀside MOSFET (Q1) has a much

shorter duty cycle and it’s conduction loss has less

impact. Q1, however, sees most of the switching losses,

the primary selection criteria should be gate charge.

Figure 16. Switching Losses and Q_G

VIN

5V

C_GD

High-Side Losses

R_D

R_GATE

HDRV

SW

G

Figure 16 shows a MOSFET’s switching interval, with

the upper graph being the voltage and current on the

drainꢀtoꢀsource and the lower graph detailing V_GSvs.

time with a constant current charging the gate. The X

axis, therefore, is also representative of gate charge

C_GS

Figure 17. Drive Equivalent Circuit

FAN5026 • Rev. 1.0.8

www.fairchildsemi.com

14

Q

I

Q

Layout Considerations

G(SW)

G(SW )

t

=

s









V

− V

(28)

Switching converters, even during normal operation,

produce short pulses of current that could cause

substantial ringing and be a source of EMI if layout

constraints are not observed.

DRIVER

CC

SP





R

+ R

GATE

DRIVER





Most MOSFET vendors specify Q_GDand Q_GS.Q_G(SW)

can be determined as:

There are two sets of critical components in a DCꢀDC

converter. The switching power components process

large amounts of energy at high rates and are noise

generators. The lowꢀpower components responsible for

bias and feedback functions are sensitive to noise.

Q

= Q

+ Q

− Q

GS TH

G(SW)

GD

(29)

where Q_THis the gate charge required to get the

MOSFET to it’s threshold (V_TH).

A multiꢀlayer printed circuit board is recommended.

Dedicate one solid layer for a ground plane. Dedicate

another solid layer as a power plane and break this

plane into smaller islands of common voltage levels.

For the highꢀside MOSFET, V_DS= V_IN, which can be as

high as 20V in a typical portable application. Care

should be taken to include the delivery of the

MOSFET’s gate power (PGATE

) in calculating the

power dissipation required for the FAN5026:

Notice all the nodes that are subjected to highꢀdV/dt

voltage swing; such as SW, HDRV, and LDRV. All

surrounding circuitry tends to couple the signals from

these nodes through stray capacitance. Do not oversize

copper traces connected to these nodes. Do not place

traces connected to the feedback components adjacent

to these traces. It is not recommended to use highꢀ

density interconnect systems, or microꢀvias, on these

signals. The use of blind or buried vias should be

limited to the lowꢀcurrent signals only. The use of

normal thermal vias is at the discretion of the designer.

P

= Q × V × f

G CC SW

(30)

G

ATE

where Q_Gis the total gate charge to reach V_CC

.

Low-Side Losses

Q2, however, switches on or off with its parallel

Schottky diode conducting, therefore V_DS≈ 0.5V. Since

P_SWis proportional to V_DS, Q2’s switching losses are

negligible and Q2 is selected based on R_DS(ON)only.

Keep the wiring traces from the IC to the MOSFET gate

and source as short as possible and capable of

handling peak currents of 2A. Minimize the area within

the gateꢀsource path to reduce stray inductance and

eliminate parasitic ringing at the gate.

Conduction losses for Q2 are given by:

2

P

=

(

1− D

)

×I

×R

DS(ON)

(31)

COND

OUT

where R_DS(ON)is the R_DS(ON)of the MOSFET at the

highest operating junction temperature, and:

Locate small critical components, like the softꢀstart

capacitor and currentꢀsense resistors, as close as

possible to the respective pins of the IC.

V

OUT

D =

(32)

V

The FAN5026 utilizes advanced packaging technology

with lead pitch of 0.6mm. Highꢀperformance analog

semiconductors utilizing narrow lead spacing may

require special considerations in design and

manufacturing. It is critical to maintain proper

cleanliness of the area surrounding these devices.

IN

is the minimum duty cycle for the converter.

Since D_MIN< 20% for portable computers, (1ꢀD) ≈ 1

produces a conservative result, further simplifying the

calculation.

The maximum power dissipation (PD(MAX)) is a function of

the maximum allowable die temperature of the lowꢀside

MOSFET; the Θ_JA, and the maximum allowable ambient

temperature rise:

T

− T

A(MAX)

J(MAX)

P

=

(33)

D(MAX)

Θ_JA

Θ_JAdepends primarily on the amount of PCB area that

can be devoted to heat sinking (see Application Note

AN-1029, Maximum Power Enhancement Techniques

for SO-8 Power MOSFETs for SO-8 MOSFET thermal

information)

.

FAN5026 • Rev. 1.0.8

www.fairchildsemi.com

15

Physical Dimensions

Figure 18. 28-Lead, Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify

or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,

specifically the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

FAN5026 • Rev. 1.0.8

www.fairchildsemi.com

16

FAN5026 • Rev. 1.0.8

www.fairchildsemi.com

17


型号：	ETQ-P6F6R4HFA
厂家：	FAIRCHILD SEMICONDUCTOR
描述：	Dual DDR / Dual-Output PWM Controller 双通道DDR /双输出PWM控制器双倍数据速率控制器
文件：	总17页 (文件大小：752K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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