FAN1851AMX_NL [FAIRCHILD]
暂无描述;
| 型号： | FAN1851AMX_NL |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | 暂无描述 断路器 |
| 文件： | 总11页 (文件大小：123K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
www.fairchildsemi.com
FAN1851A
Ground Fault Interrupter
Features
Description
• Improved performance over industry equivalents
– Tight fault current range (Typ ±100µA)
– Temperature compensated fault current characteristics
– No external trimming required
• Direct interface to SCR
• Supply voltage derived from AC line—26V shunt
• Adjustable sensitivity
The FAN1851A is a controller for AC outlet ground fault
interrupters. These devices detect hazardous grounding con-
ditions (example: a pool of water or an electrical equipment
connected to opposite phases of the AC line) in consumer
and industrial environments. The output of the IC triggers an
external SCR, which in turn opens a relay circuit breaker to
prevent a harmful or lethal shock.
• Grounded neutral fault detection
• Meets UL943 standards
• 450µA quiescent current
• Ideal for 120V or 220V systems
• Package options: 8L DIP and 8L SOIC
Full advantage of the U.S. UL943 timing specification is
taken to ensure maximum immunity to false triggering due
to line noise. A special feature in the circuitry rapidly resets
the integrating timing capacitor in the event that noise pulses
introduce unwanted charging currents. Also, a flip-flop is
included that ensures firing of even a slow circuit breaker
relay on either of the two half-cycles of the line voltage
when external full wave rectification is used.
The application circuit can be configured to detect both
normal faults (hot wire to ground) and grounded neutral
faults.
Block Diagram
Timing
Capacitor
Sensitivity
Set Resistor
Sense Amplifier
Output
+V
S
I
TH
I
D3
2
I
for I > 0
F
TH
3I for I = 0
I =
Q2
D1
TH
F
SCR Trigger
I
F
Latch
Q3
Q1
Q5
+V
A1
S
Q4
D2
I
F
10V
Ground
Inverting Input
Non-Inverting Input
REV. 2.0.1 6/17/05
FAN1851A
PRODUCT SPECIFICATION
Pin Assignments
SCR Trigger
– Input
1
2
3
4
8
7
6
5
+V
S
C
R
T
+ Input
SET
Ground
Amp Out
Functional Description
The voltage at the supply pin is clamped to +26V by the
internal shunt regulator D3. This shunt regulator also
generates an artificial ground voltage for the noninverting
input of A1 (shown as a +10V source). A1, Q1, and Q2
together act as a current mirror for fault current signals
(which are derived from an external transformer). When a
fault signal is present, the mirrored current charges the
external timing capacitor until its voltage exceeds the latch
trigger threshold (typically 17.5V). When this threshold is
where I is the value of current set by the external R
TH SET
resistor. If fault signals are present at the input of A1 (which
is held at virtual ground, +10V), one of the two current
mirrors in the feedback path of A1 (Q4 and Q5) will become
active, depending on which half-cycle the fault occurs.
This action will raise the voltage at V , switching I to a
S
1
value equal to I , and reducing the discharge rate of C to
TH
T
better allow fault currents to charge it.
exceeded, the latch engages and Q3 turns off, allowing I to
2
Notice that I discharges C during both half-cycles of the
TH
T
drive the SCR connected to the "SCR Trigger" pin.
line, while I only charges C during the half-cycle in which
F T
I exits the "- Input" pin (since Q1 will only carry fault cur-
F
Extra Circuitry in the feedback path of A1 works with the
rent in one direction). Thus, during one half-cycle, I -I
F TH
switched current source I to remove any charge on C
charges C , while during the other half-cycle I discharges
TH
1
T
T
induced by noise in the transformer. If no fault current is
present, then I discharges C with a current equal to 3 I ,
TH
it.
1
T
Definition of Terms
Normal Fault:
Grounded Neutral Fault:
An unintentional electrical path, R , between the load termi-
B
nal of the hot line and the ground, as shown by the dashed
lines in Figure1.
An unintentional electrical path between the load terminal of
the neutral line and the ground, as shown by the dashed lines
in Figure 2.
Hot
Hot
Hot
Hot
Line
R
R
GFI
GFI
R
LOAD
LOAD
B
Line
Neutral
Neutral
Neutral
Neutral
R
IN
R
R
G
G
Figure 1. Normal Fault
Figure 2. Grounded Neutral Fault
2
REV. 2.0.1 6/17/05
PRODUCT SPECIFICATION
FAN1851A
Normal Fault Plus Grounded Neutral Fault:
The combination of the normal fault and the grounded
neutral fault, as shown by the dashed lines in Figure 3.
Hot
Hot
R
GFI
R
LOAD
B
Line
Neutral
Neutral
R
N
R
G
Figure 3. Normal Fault Plus Grounded Neutral Fault
Absolute Maximum Ratings
Parameter
Conditions
Min
Max
19
Units
mA
mW
°C
Supply Current
Power Dissipation
570
70
Operating Temperature
Lead Soldering Temperature, 60 seconds
-40
300
°C
Thermal Characteristics
Parameter
Conditions
Min
Max
125
468
85
Units
°C
Maximum Junction Temperature
Maximum P
T < 50°C
mW
°C/W
D
A
Thermal Resistance, θ
DIP
SOIC
JA
150
REV. 2.0.1 6/17/05
3
FAN1851A
PRODUCT SPECIFICATION
DC Electrical Characteristics
(T = +25°C, I
A
= 5 mA)
SHUNT
Parameters
Test Conditions
Min
Typ
Max
Units
Power Supply Shunt Regulator
Voltage
Pin 8, Average Value
22
26
30
V
Latch Trigger Voltage
Pin 7
15
6
17.5
7
20
8.2
2.4
240
V
V
Sensitivity Set Voltage
Output Drive Current
Pin 8 to Pin 6
Pin 1 With Fault
Pin 1 Without Fault
Pin 1 Without Fault
0.5
1
mA
mV
Ω
Output Saturation Voltage
Output Saturation Resistance
100
100
5
Output External Current Sinking
Capability1
Pin 1 Without Fault, V
to 0.3V
Held
2
mA
PIN1
Noise Integration Sink Current
Ratio
Pin 7, Ratio of Discharge Currents
Between No Fault and Fault
Conditions
2.0
2.8
3.6
µA/µA
Note:
1. This external applied current is in addition to the internal “output drive current” source.
AC Electrical Characteristics
(T = +25°C, I
A
= 5 mA)
SHUNT
Parameters
Normal Fault Current Sensitivity2
Conditions
Min
Typ
5
Max
Units
mA
See Figure 9
4.75
5.25
Normal Fault Trip Time1
500Ω Fault, see Figure 10
500Ω Normal Fault,
2Ω Neutral, see Figure 10 (Note 1)
18
18
mS
Normal Fault With Grounded
Neutral Fault Trip Time1
mS
Notes:
1. Average of ten trials.
2. Required UL System sensitivity tolerance is 4mA to 6mA.
4
REV. 2.0.1 6/17/05
PRODUCT SPECIFICATION
FAN1851A
Typical Performance Characteristics (T = +25°C)
A
100
10
1
1000
100
10
Circuit of
Figure 10
7V
(rms)* x (0.91)
R
=
SET
I
F
Sense Transformer 1000:1
UL943
Normal
Fault
0
0.01
0.1
1
10
100K
1M
10M
Trip Time (Seconds)
R
SET
(Ω)
Figure 4. Average Trip Time vs. Fault Current
Figure 5. Normal Fault Current Threshold vs. R
SET
1400
1200
1000
10
800
600
400
200
0
31V
1
5 mA
1
8
5 mA
31V
IL
8
1 mA
A
1
0.1
1 mA
VPIN1
4
V
4
0.01
0
5
10
15
20
25
30
35
0.1
1
10
100
Output Voltage @ V
(V)
External Load Current (mA)
Figure 7. Pin 1 Saturation Voltage vs.
PIN1
Figure 6. Output Drive Current vs. Output Voltage
External Load Current, I
L
REV. 2.0.1 6/17/05
5
FAN1851A
PRODUCT SPECIFICATION
The correct value for R
characteristic curve that plots equation (3). Note that this is
an approximate calculation; the exact value of R depends
on the specific sense transformer used and FAN1851A toler-
ances. Inasmuch as UL943 specifies a sensitivity “window”
can also be determined from the
SET
Application Information
A typical ground fault interrupter circuit is shown in
Figure 10. It is designed to operate on 120 VAC line voltage
with 5mA normal fault sensitivity.
SET
of 4mA to 6mA, a provision should be made to adjust R
with a potentiometer.
SET
A full-wave rectifier bridge and a 15kΩ/2W resistor are used
to supply the DC power required by the IC. A 1 µF capacitor
at the "+V " pin is used to filter the ripple of the supply volt-
S
Independent of setting sensitivity, the desired integration
time can be obtained through proper selection of the timing
age and is also connected across the SCR to allow firing of
the SCR on either half-cycle. When a fault causes the SCR to
trigger, the circuit breaker is energized and line voltage is
removed from the load.
capacitor, C . Due to the large number of variables involved,
T
proper selection of C is best done empirically. The follow-
T
ing design example should only be used as a guideline.
At this time no fault current flows and the C discharge cur-
rent increases from I to 3I (see Block Diagram). This
TH TH
T
Assume the goal is to meet UL943 timing requirements.
Also assume that worst case timing occurs during GFI
start-up (S1 closure) with both a heavy normal fault and a
2Ω grounded neutral fault present. This situation is shown in
Figure 8.
quickly resets both the timing capacitor and the output latch.
The circuit breaker can be reset and the line voltage again
supplied to the load, assuming the fault has been removed.
A 1000:1 sense transformer is used to detect the normal
fault. The fault current, which is basically the difference in
current between the hot and neutral lines, is stepped down by
1000 and fed into the input pin of the operational amplifier
through a 10µF capacitor. The 0.0033µF capacitor between
the "- Input" pin and the "+ Input" pin and the 200pF capaci-
tor between "+ Input" and "Ground" pins are added to obtain
better noise immunity. The normal fault sensitivity is deter-
S1
Hot
Hot
Line
GFI
Neutral
Neutral
R
0.4
R
B
500
N
mined by the timing capacitor discharging current, I . I
TH TH
can be calculated by:
(0.8)I
I
7V
ITH = ------------ ÷ 2
RSET
(1)
(2)
R
500
B
(0.2)I
At the decision point, the average fault current just equals
the threshold current, I
Figure 8. Example
.
TH
UL943 specifies ≤ 25ms average trip time under these condi-
tions. Calculation of C based upon charging currents due to
T
normal fault only is as follows:
IF(rms)
ITH = ------------------- × 0 . 9 1
2
Where I (rms) is the rms input fault current to the opera-
F
tional amplifier and the factor of 2 is due to the fact that I
charges the timing capacitor only during one half-cycle,
1. Start with a ≤ 25ms specification. Subtract 3ms GFI
turn-on time (15kΩ and 1µF). Subtract 8ms potential
loss of one half-cycle due to fault current sense of
half-cycles only.
F
while I discharges the capacitor continuously. The factor
TH
0.91 converts the rms value to an average value. Combining
equations (1) and (2) we have:
2. Subtract 4ms time required to open a sluggish circuit
breaker.
7V
RSET = ------------------------------------
(3)
3. This gives a total ≤ 10ms maximum integration time
IF(rms) × 0.91
that could be allowed.
For example, to obtain 5mA(rms) sensitivity for the circuit
in Figure 7 we have:
4. To generate 8ms value of integration time that accom-
modates component tolerances and other variables:
7V
5 mA × 0.91
-----------------------------
1000
RSET = ----------------------------- = 1 . 5 M Ω
(4)
I × T
CT = -----------
(5)
V
6
REV. 2.0.1 6/17/05
PRODUCT SPECIFICATION
FAN1851A
In practice, the actual value of C will have to be modified
T
where:
to include the effects of the neutral loop upon the net charg-
ing current. The effect of neutral loop induced currents is dif-
ficult to quantify, but typically they sum with normal fault
T = integration time
V = threshold voltage
I = average fault current into CT
currents, thus allowing a larger value of C . For UL943
T
requirements, 0.015µF has been found to be the best com-
promise between timing and noise.
120 VAC(rms)
RN
⎛
⎞
⎠
⎛
⎝
⎞
⎠
I = ------------------------------------
-----------------------
RG + RN
⎝
RB
For those GFI standards not requiring grounded neutral
detection, a still larger value capacity can be used and better
noise immunity obtained. The larger capacitor can be accom-
heavy fault
current generated
portion of fault
current shunted
around GFI
(swamps I
)
TH
modated because R and R are not present, allowing the
N
G
full fault current, I, to enter the GFI.
1 turn
1000 turns
1
⎝ ⎠
2
⎛
⎞
⎛ ⎞
× ------------------------
×
--
×
(0.91)
(6)
In Figure 10, grounded neutral detection is accomplished by
feeding the neutral coil with 120Hz energy continuously and
allowing some of the energy to couple into the sense trans-
former during conditions of neutral fault.
⎝
⎠
current
division of
input sense
transformer
CT
rms to
average
conversion
charging
on half-
cycles
only
Transformers may be obtained from Magnetic Metals, Inc.,
(http://www.magmet.com).
therefore:
120
500
0.4
1.6 + 0.4
1
1000
1
⎛ ⎞
⎛
⎝
⎞
⎛
⎞
⎛
⎞
-------- × -------------------- × ----------- × -- × (0.91)
⎠
⎝
⎠
⎝
⎠
⎝ ⎠
2
C
= ----------------------------------------------------------------------------------------------------------------- × 0.008
T
17.5
C
= 0.01 µF
(7)
T
REV. 2.0.1 6/17/05
7
FAN1851A
PRODUCT SPECIFICATION
Application Circuits
FAN1851A
100K
0.047 μF
7
1
2
3
-In
Timing
Cap
SCR
+In
Trigger
C
0.002
T
6
4
800 Hz
5
8
R
Op Amp
Output
SET
I
SHUNT
A
GND
+V
S
1K
300 mV
1.5M
31V
Figure 9. Normal Fault Sensitivity Test Circuit
Sense
Coil
Gnd/Neutral
Coil
Hot
Load
Neutral
MOV
200:1
Line
1000:1
High μ Coil
Circuit
Breaker
0.01/400V
1.0 μF Tant
FAN1851A
7
1
2
Timing
Cap
–In
15K/2W
0.0033
+In
SCR
Trigger
3
6
C
T
0.015
200 pF
R
Op Amp
Output
SET
SCR
5
8
4
GND
+V
S
0.01/400V
0.01
R
SET*
10 μF
Tant
*Adjust R
for desired sensitivity.
SET
Figure 10. 120 Hz Neutral Transformer Application
8
REV. 2.0.1 6/17/05
FAN1851A
PRODUCT SPECIFICATION
Mechanical Dimensions
8-Lead Plastic DIP Package
6.40 0.20
0.252 0.008
#1
#4
#8
#5
3.30 0.30
0.130 0.012
5.08
0.200
MAX
7.62
3.40 0.20
0.134 0.008
0.300
0.33
0.013
MIN
Dimensions in Millimeters
9
REV. 2.0.1 6/17/05
FAN1851A
PRODUCT SPECIFICATION
Mechanical Dimensions (continued)
8-Lead Plastic SOIC Package
Notes:
Inches
Millimeters
Symbol
Notes
1. Dimensioning and tolerancing per ANSI Y14.5M-1982.
Min.
Max.
Min.
Max.
2. "D" and "E" do not include mold flash. Mold flash or
protrusions shall not exceed .010 inch (0.25mm).
A
.053
.004
.013
.008
.189
.150
.069
.010
.020
.010
.197
.158
1.35
0.10
0.33
0.20
4.80
3.81
1.75
0.25
0.51
0.25
5.00
4.01
A1
B
3. "L" is the length of terminal for soldering to a substrate.
4. Terminal numbers are shown for reference only.
5. "C" dimension does not include solder finish thickness.
6. Symbol "N" is the maximum number of terminals.
C
D
E
5
2
2
e
.050 BSC
1.27 BSC
H
h
.228
.010
.016
.244
.020
.050
5.79
0.25
0.40
6.20
0.50
1.27
L
3
6
N
α
8
8
0°
8°
0°
8°
ccc
—
.004
—
0.10
8
5
E
H
1
4
h x 45°
D
C
A1
A
α
SEATING
PLANE
– C –
L
e
LEAD COPLANARITY
ccc C
B
10
REV. 2.0.1 6/17/05
FAN1851A
PRODUCT SPECIFICATION
Ordering Information
Part Number
FAN1851AN
FAN1851AMX
Package
Pb-Free Operating Temperature Range Packing Method
8-lead Plastic DIP
8-lead Plastic SOIC
Yes
Yes
-40°C to +70°C
-40°C to +70°C
Rail
Tape and Reel
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO
ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME
ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
REV. 2.0.1 6/17/05
© 2005 Fairchild Semiconductor Corporation
相关型号：
FAN1951D18X_NL
Fixed Positive LDO Regulator, 1.8V, 0.5V Dropout, PSSO5, LEAD FREE, PLASTIC, TO-252, DPAK-5
FAIRCHILD
©2020 ICPDF网 联系我们和版权申明