FAN3224TMX_F085_技术文档

April 2014

FAN3223 / FAN3224 / FAN3225

Dual 4-A High-Speed, Low-Side Gate Drivers

Features

Description

The FAN3223-25 family of dual 4 A gate drivers is

designed to drive N-channel enhancement-mode

MOSFETs in low-side switching applications by

providing high peak current pulses during the short

switching intervals. The driver is available with either

TTL or CMOS input thresholds. Internal circuitry

provides an under-voltage lockout function by holding

the output LOW until the supply voltage is within the

operating range. In addition, the drivers feature matched

internal propagation delays between A and B channels

for applications requiring dual gate drives with critical

timing, such as synchronous rectifiers. This also

enables connecting two drivers in parallel to effectively

double the current capability driving a single MOSFET.

.

Industry-Standard Pinouts

4.5-V to 18-V Operating Range

5-A Peak Sink/Source at V_DD= 12 V

4.3-A Sink / 2.8-A Source at V_OUT= 6 V

Choice of TTL or CMOS Input Thresholds

Three Versions of Dual Independent Drivers:

-

Dual Inverting + Enable (FAN3223)

Dual Non-Inverting + Enable (FAN3224)

Dual-Inputs (FAN3225)

.

Internal Resistors Turn Driver Off If No Inputs

MillerDrive™ Technology

The FAN322X drivers incorporate MillerDrive™

architecture for the final output stage. This bipolar-

MOSFET combination provides high current during the

Miller plateau stage of the MOSFET turn-on / turn-off

process to minimize switching loss, while providing rail-

to-rail voltage swing and reverse current capability.

12-ns / 9-ns Typical Rise/Fall Times (2.2-nF Load)

Under 20-ns Typical Propagation Delay Matched

within 1 ns to the Other Channel

.

Double Current Capability by Paralleling Channels

8-Lead 3x3 mm MLP or 8-Lead SOIC Package

Rated from –40°C to +125°C Ambient

The FAN3223 offers two inverting drivers and the

FAN3224 offers two non-inverting drivers. Each device

has dual independent enable pins that default to ON if

not connected. In the FAN3225, each channel has dual

inputs of opposite polarity, which allows configuration as

non-inverting or inverting with an optional enable

function using the second input. If one or both inputs are

left unconnected, internal resistors bias the inputs such

that the output is pulled LOW to hold the power

MOSFET OFF.

Automotive Qualified to AEC-Q100 (F085 Version)

Applications

.

Switch-Mode Power Supplies

High-Efficiency MOSFET Switching

Synchronous Rectifier Circuits

DC-to-DC Converters

Related Resources

AN-6069 — Application Review and Comparative

Evaluation of Low-Side Gate Drivers

Motor Control

Automotive-Qualified Systems (F085 version)

FAN3223

FAN3224

FAN3225

Figure 1. Pin Configurations

FAN3223 / FAN3224 / FAN3225 • Rev. 1.1.4

www.fairchildsemi.com

Ordering Information

Input

Threshold

Packing

Method

Quantity

per Reel

Part Number

Logic

Package

FAN3223CMPX

3x3 mm MLP-8

SOIC-8

Tape & Reel

3,000

2,500

3,000

2,500

3,000

2,500

3,000

2,500

3,000

2,500

3,000

2,500

FAN3223CMX

FAN3223CMX_F085⁽¹⁾

CMOS

TTL

SOIC-8

Dual Inverting Channels +

Dual Enable

FAN3223TMPX

3x3 mm MLP-8

SOIC-8

FAN3223TMX

FAN3223TMX_F085⁽¹⁾

FAN3224CMPX

FAN3224CMX

SOIC-8

3x3 mm MLP-8

SOIC-8

CMOS

TTL

FAN3224CMX_F085⁽¹⁾

SOIC-8

Dual Non-Inverting

Channels + Dual Enable

FAN3224TMPX

3x3 mm MLP-8

SOIC-8

FAN3224TMX

FAN3224TMX_F085⁽¹⁾

FAN3225CMPX

FAN3225CMX

SOIC-8

3x3 mm MLP-8

SOIC-8

CMOS

TTL

FAN3225CMX_F085⁽¹⁾

SOIC-8

Dual Channels of Two-

Input / One-Output Drivers

FAN3225TMPX

3x3 mm MLP-8

SOIC-8

FAN3225TMX

FAN3225TMX_F085⁽¹⁾

SOIC-8

All standard Fairchild Semiconductor products are RoHS compliant and many are also “Green” or going green. Green means the

products are RoHS compliant AND they have limits on additional substances of Chlorine, Bromine and Antimony. For additional

information on Fairchild’s “green” Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.

Note:

1. Qualified to AEC-Q100.

FAN3223 / FAN3224 / FAN3225 • Rev. 1.1.4

www.fairchildsemi.com

2

Package Outlines

Figure 2. 3x3 mm MLP-8 (Top View)

Figure 3. SOIC-8 (Top View)

Thermal Characteristics⁽²⁾

(3)

(4)

(5)

(6)

(7)

Package

Units

°C/W

_JL

_JT

_JA

_JB

_JT

1.2

64

42

2.8

0.7

8-Lead 3x3 mm Molded Leadless Package (MLP)

8-Pin Small Outline Integrated Circuit (SOIC)

Notes:

38

29

87

41

2.3

°C/W

2. Estimates derived from thermal simulation; actual values depend on the application.

3. Theta_JL (_JL): Thermal resistance between the semiconductor junction and the bottom surface of all the leads (including any

thermal pad) that are typically soldered to a PCB.

4. Theta_JT (_JT): Thermal resistance between the semiconductor junction and the top surface of the package, assuming it is

held at a uniform temperature by a top-side heatsink.

5. Theta_JA (Θ_JA): Thermal resistance between junction and ambient, dependent on the PCB design, heat sinking, and airflow.

The value given is for natural convection with no heatsink using a 2S2P board, as specified in JEDEC standards JESD51-2,

JESD51-5, and JESD51-7, as appropriate.

6. Psi_JB (_JB): Thermal characterization parameter providing correlation between semiconductor junction temperature and an

application circuit board reference point for the thermal environment defined in Note 5. For the MLP-8 package, the board

reference is defined as the PCB copper connected to the thermal pad and protruding from either end of the package. For the

SOIC-8 package, the board reference is defined as the PCB copper adjacent to pin 6.

7. Psi_JT (_JT): Thermal characterization parameter providing correlation between the semiconductor junction temperature and

the center of the top of the package for the thermal environment defined in Note 5.

FAN3223 / FAN3224 / FAN3225 • Rev. 1.1.4

www.fairchildsemi.com

3

FAN3223

FAN3224

FAN3225

Figure 4. Pin Assignments (Repeated)

Pin Definitions

Name

Pin Description

Enable Input for Channel A. Pull pin LOW to inhibit driver A. ENA has TTL thresholds for both TTL and

CMOS INx threshold.

ENA

Enable Input for Channel B. Pull pin LOW to inhibit driver B. ENB has TTL thresholds for both TTL and

CMOS INx threshold.

ENB

GND

INA

Ground. Common ground reference for input and output circuits.

Input to Channel A.

INA+ Non-Inverting Input to Channel A. Connect to VDD to enable output.

INA-

INB

Inverting Input to Channel A. Connect to GND to enable output.

Input to Channel B.

INB+ Non-Inverting Input to Channel B. Connect to VDD to enable output.

INB-

Inverting Input to Channel B. Connect to GND to enable output.

OUTA Gate Drive Output A: Held LOW unless required input(s) are present and V_DDis above UVLO threshold.

OUTB Gate Drive Output B: Held LOW unless required input(s) are present and V_DDis above UVLO threshold.

Gate Drive Output A (inverted from the input): Held LOW unless required input is present and V_DDis

OUTA

above UVLO threshold.

Gate Drive Output B (inverted from the input): Held LOW unless required input is present and V_DDis

above UVLO threshold.

OUTB

Thermal Pad (MLP only). Exposed metal on the bottom of the package; may be left floating or connected

to GND; NOT suitable for carrying current.

P1

VDD

Supply Voltage. Provides power to the IC.

Output Logic

FAN3223 (x=A or B)

FAN3224 (x=A or B)

FAN3225 (x=A or B)

ENx

INx

ENx

INx

OUTx

INx+

INx−

OUTx

0

1⁽⁸⁾

0

1

0

0⁽⁸⁾

0

1

0⁽⁸⁾

1

0

1⁽⁸⁾

0

1

0

1

1⁽⁸⁾

0⁽⁸⁾

1

0

1⁽⁸⁾

1

Note:

8. Default input signal if no external connection is made.

FAN3223 / FAN3224 / FAN3225 • Rev. 1.1.4

www.fairchildsemi.com

4

Block Diagrams

Figure 5. FAN3223 Block Diagram

Figure 6. FAN3224 Block Diagram

FAN3223 / FAN3224 / FAN3225 • Rev. 1.1.4

www.fairchildsemi.com

5

Block Diagrams

Figure 7. FAN3225 Block Diagram

FAN3223 / FAN3224 / FAN3225 • Rev. 1.1.4

www.fairchildsemi.com

6

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.

The absolute maximum ratings are stress ratings only.

Symbol

V_DD

Parameter

Min.

Max.

Unit

V

VDD to PGND

-0.3

20.0

V_EN

ENA and ENB to GND

GND - 0.3 V_DD+ 0.3

+260

V

V_IN

INA, INA+, INA–, INB, INB+ and INB– to GND

OUTA and OUTB to GND DC

V

V_OUT

T_L

V

Lead Soldering Temperature (10 Seconds)

Junction Temperature

ºC

T_J

-55

-65

+150

T_STG

Storage Temperature

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended

operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not

recommend exceeding them or designing to Absolute Maximum Ratings.

Symbol

V_DD

Parameter

Min.

4.5

0

Max.

18.0

Unit

V

Supply Voltage Range

V_EN

Enable Voltage ENA and ENB

V_DD

V

V_IN

Input Voltage INA, INA+, INA–, INB, INB+ and INB–

0

V_DD

V

V_OUT

T_A

OUTA and OUTB to GND

Repetitive Pulse < 200 ns

-2.0

-40

V_DD+ 0.3

+125

V

Operating Ambient Temperature

ºC

FAN3223 / FAN3224 / FAN3225 • Rev. 1.1.4

www.fairchildsemi.com

7

Electrical Characteristics

Unless otherwise noted, V_DD=12 V, T_J=-40°C to +125°C. Currents are defined as positive into the device and

negative out of the device.

Symbol

Supply

V_DD

Parameter

Conditions

Min.

Typ. Max. Unit

Operating Range

4.5

18.0

0.95

0.35

4.3

V

mA

V

All except FAN3225C

0.70

0.21

3.9

Supply Current, Inputs / EN Not

Connected

I_DD

FAN3225C⁽⁹⁾

V_ON

Turn-On Voltage

Turn-Off Voltage

INA=ENA=V_DD, INB=ENB=0 V

3.5

3.3

V_OFF

3.7

4.1

V

FAN322xTMX_F085, FAN322xCMX_F085 (Automotive-Qualified Versions)

V_DD

Operating Range

4.5

18.0

1.20

0.35

4.5

V

mA

V

All Except FAN3225C

FAN3225C⁽⁹⁾

0.70

0.21

3.9

Supply Current, Inputs / EN Not

Connected⁽¹⁴⁾

I_DD

V_ON

Turn-On Voltage⁽¹⁴⁾

Turn-Off Voltage⁽¹⁴⁾

INA=ENA=V_DD, INB=ENB=0 V

3.4

3.2

V_OFF

3.7

4.3

V

Inputs (FAN322xT)⁽¹⁰⁾

V_{INL_T}

V_{INH_T}

V_{HYS_T}TTL Logic Hysteresis Voltage

INx Logic LOW Threshold

0.8

1.2

1.6

0.4

V

INx Logic HIGH Threshold

2.0

0.2

-1

0.8

175

1

V

I_IN+

I_IN-

Non-Inverting Input Current

Inverting Input Current

IN from 0 to V_DD

µA

-175

FAN322xTMX_F085 (Automotive-Qualified Versions)

V_{INL_T}

V_{INH_T}

INx Logic LOW Threshold

INx Logic HIGH Threshold

0.8

1.2

1.6

0.4

V

2.0

0.9

1.5

175

-90

1.5

V_{HYS_T}TTL Logic Hysteresis Voltage

0.1

-1.5

90

V

I_{INx_T}

Non-inverting Input Current⁽¹⁴⁾

Inverting Input Current⁽¹⁴⁾

IN=0 V

IN=V_DD

IN=0 V

IN=V_DD

µA

120

-175

-1.5

-120

Inputs (FAN322xC)⁽¹⁰⁾

V_{INL_C}

V_{INH_C}

V_{HYS_C}CMOS Logic Hysteresis Voltage

INx Logic Low Threshold

30

38

55

17

%V_DD

INx Logic High Threshold

70

%V_DD

µA

I_IN+

I_IN-

Non-Inverting Input Current

Inverting Input Current

IN from 0 to V_DD

-1

175

1

-175

µA

Continued on the following page…

FAN3223 / FAN3224 / FAN3225 • Rev. 1.1.4

www.fairchildsemi.com

8

Electrical Characteristics

Unless otherwise noted, V_DD=12 V, T_J=-40°C to +125°C. Currents are defined as positive into the device and

negative out of the device.

Symbol

Parameter

Conditions

Min.

Typ. Max. Unit

FAN322xCMX_F085 (Automotive-Qualified Versions)

V_{INL_C}

V_{INH_C}

INx Logic Low Threshold

INx Logic High Threshold

30

38

55

17

%V_DD

µA

70

V_{HYS_C}CMOS Logic Hysteresis Voltage

I_{INx_T}

Non-Inverting Input Current⁽¹⁴⁾

Inverting Input Current⁽¹⁴⁾

IN=0 V

IN=V_DD

IN=0 V

IN=V_DD

-1.5

90

1.5

175

-90

1.5

120

µA

-175

-1.5

-120

µA

ENABLE (FAN3223C, FAN3223T, FAN3224C, FAN3224T)

V_ENL

V_ENH

Enable Logic Low Threshold

Enable Logic High Threshold

EN from 5 V to 0 V

EN from 0 V to 5 V

0.8

1.2

1.6

0.4

100

V

2.0

V_{HYS_T}TTL Logic Hysteresis Voltage⁽¹¹⁾

V

R_PU

Enable Pull-Up Resistance⁽¹¹⁾

kΩ

0 V to 5 V EN, 1 V/ns Slew

Rate

t_D3

9

17

18

26

28

ns

EN to Output Propagation Delay⁽¹²⁾

5 V to 0 V EN, 1 V/ns Slew

Rate

t_D4

11

FAN3223C/TMX_F085, FAN3224C/TMX_F085 (Automotive-Qualified Versions)

V_ENL

V_ENH

Enable Logic Low Threshold

Enable Logic High Threshold

EN from 5 V to 0 V

EN from 0 V to 5 V

0.8

1.2

1.6

0.4

100

V

2.0

V_{HYS_T}TTL Logic Hysteresis Voltage⁽¹¹⁾

V

R_PU

Enable Pull-Up Resistance⁽¹¹⁾

kΩ

0 V to 5V EN, 1 V/ns Slew

Rate

t_D3

9

17

19

34

31

ns

EN to Output Propagation Delay^(12,14)

5 V to 0V EN, 1 V/ns Slew

Rate

t_D4

Outputs

I_SINK

OUT at V_DD/2, C_LOAD=0.22 µF,

f=1 kHz

OUT Current, Mid-Voltage, Sinking⁽¹¹⁾

4.3

A

OUT Current, Mid-Voltage,

Sourcing⁽¹¹⁾

OUT at V_DD/2, C_LOAD=0.22 µF,

f=1 kHz

I_SOURCE

-2.8

I_{PK_SINK}OUT Current, Peak, Sinking⁽¹¹⁾

I_{PK_SOURCE}OUT Current, Peak, Sourcing⁽¹¹⁾

C_LOAD=0.22 µF, f=1 kHz

C_LOAD=2200 pF

5

-5

12

9

A

t_RISE

t_FALL

Output Rise Time⁽¹³⁾

Output Fall Time⁽¹³⁾

20

17

ns

C_LOAD=2200 pF

Propagation Matching Between

Channels

Output Reverse Current Withstand⁽¹¹⁾

INA=INB, OUTA and OUTB at

50% Point

t_DEL.MATCH

I_RVS

2

4

ns

mA

ns

500

18

Output Propagation Delay, CMOS

Inputs⁽¹³⁾

t_D1,t_D2

0 – 12 V_IN, 1 V/ns Slew Rate

0 – 5 V_IN, 1 V/ns Slew Rate

10

9

29

Output Propagation Delay, TTL

Inputs⁽¹³⁾

t_D1,t_D2

17

ns

Continued on the following page…

FAN3223 / FAN3224 / FAN3225 • Rev. 1.1.4

www.fairchildsemi.com

9

Electrical Characteristics

Unless otherwise noted, V_DD=12 V, T_J=-40°C to +125°C. Currents are defined as positive into the device and

negative out of the device.

Symbol

Parameter

Conditions

Min.

Typ. Max. Unit

All Except for FAN3225C/TMX_F085 (Automotive-Qualified Versions)

t_RISE

t_FALL

Output Rise Time⁽¹³⁾

Output Fall Time⁽¹³⁾

C_LOAD=2200 pF

12

9

20

17

ns

Propagation Matching Between

Channels

Output Reverse Current Withstand⁽¹¹⁾

INA=INB, OUTA and OUTB at

50% Point

t_DEL.MATCH

I_RVS

2

4

ns

mA

ns

500

18

Output Propagation Delay, CMOS

Inputs^(13,14)

t_D1,t_D2

0 – 12 V_IN, 1 V/ns Slew Rate

0 – 5 V_IN, 1 V/ns Slew Rate

9

6

34

30

Output Propagation Delay, TTL

Inputs^(13,14)

t_D1,t_D2

16

ns

V_OH

V_OL

High Level Output Voltage⁽¹⁴⁾

Low Level Output Voltage⁽¹⁴⁾

15

10

35

25

mV

V

_OH=V_DD–V_OUT, I_OUT=–1 mA

I_OUT= 1 mA

FAN3225C/TMX_F085 (Automotive-Qualificed Versions)

t_RISE

t_FALL

Output Rise Time⁽¹³⁾

Output Fall Time⁽¹³⁾

C_LOAD=2200 pF

12

9

28

26

ns

V_OH

High Level Output Voltage⁽¹⁴⁾

Low Level Output Voltage⁽¹⁴⁾

15

10

37

25

mV

V_OH=V_DD–V_OUT, I_OUT=–1 mA

V_OL

I_OUT= 1 mA

Notes:

9. Lower supply current due to inactive TTL circuitry.

10. EN inputs have TTL thresholds; refer to the ENABLE section.

11. Not tested in production.

12. See Timing Diagrams of Figure 10 and Figure 11.

13. See Timing Diagrams of Figure 8 and Figure 9.

14. Applies only to _F085 versions.

www.fairchildsemi.com

FAN3223 / FAN3224 / FAN3225 • Rev. 1.1.4

10

Timing Diagrams

Figure 8. Non-Inverting (EN HIGH or Floating)

Figure 9. Inverting (EN HIGH or Floating)

Figure 10. Non-Inverting (IN HIGH)

Figure 11. Inverting (IN LOW)

FAN3223 / FAN3224 / FAN3225 • Rev. 1.1.4

www.fairchildsemi.com

11

Typical Performance Characteristics

Typical characteristics are provided at 25°C and V_DD=12 V unless otherwise noted.

Figure 12. I_DD(Static) vs. Supply Voltage⁽¹⁵⁾

Figure 13. I_DD(Static) vs. Supply Voltage⁽¹⁵⁾

Figure 14. I_DD(Static) vs. Supply Voltage⁽¹⁵⁾

Figure 15. I_DD(No-Load) vs. Frequency

Figure 16. I_DD(No-Load) vs. Frequency

FAN3223 / FAN3224 / FAN3225 • Rev. 1.1.4

www.fairchildsemi.com

12

Typical Performance Characteristics

Typical characteristics are provided at 25°C and V_DD=12 V unless otherwise noted.

Figure 17. I_DD(2.2 nF Load) vs. Frequency

Figure 18. I_DD(2.2 nF Load) vs. Frequency

Figure 19. I_DD(Static) vs. Temperature⁽¹⁵⁾

Figure 20. I_DD(Static) vs. Temperature⁽¹⁵⁾

Figure 21. I_DD(Static) vs. Temperature⁽¹⁵⁾

FAN3223 / FAN3224 / FAN3225 • Rev. 1.1.4

www.fairchildsemi.com

13

Typical Performance Characteristics

Typical characteristics are provided at 25°C and V_DD=12 V unless otherwise noted.

Figure 22. Input Thresholds vs. Supply Voltage

Figure 23. Input Thresholds vs. Supply Voltage

Figure 24. Input Threshold % vs. Supply Voltage

Figure 25. Input Thresholds vs. Temperature

Figure 26. Input Thresholds vs. Temperature

FAN3223 / FAN3224 / FAN3225 • Rev. 1.1.4

www.fairchildsemi.com

14

Typical Performance Characteristics

Typical characteristics are provided at 25°C and V_DD=12 V unless otherwise noted.

Figure 27. UVLO Thresholds vs. Temperature

Figure 29. Propagation Delay vs. Supply Voltage

Figure 31. Propagation Delay vs. Supply Voltage

Figure 28. UVLO Threshold vs. Temperature

Figure 30. Propagation Delay vs. Supply Voltage

Figure 32. Propagation Delay vs. Supply Voltage

FAN3223 / FAN3224 / FAN3225 • Rev. 1.1.4

www.fairchildsemi.com

15

Typical Performance Characteristics

Typical characteristics are provided at 25°C and V_DD=12 V unless otherwise noted.

Figure 33. Propagation Delays vs. Temperature

Figure 34. Propagation Delays vs. Temperature

Figure 35. Propagation Delays vs. Temperature

Figure 36. Propagation Delays vs. Temperature

Figure 37. Fall Time vs. Supply Voltage

Figure 38. Rise Time vs. Supply Voltage

FAN3223 / FAN3224 / FAN3225 • Rev. 1.1.4

www.fairchildsemi.com

16

Typical Performance Characteristics

Typical characteristics are provided at 25°C and V_DD=12 V unless otherwise noted.

Figure 39. Rise and Fall Times vs. Temperature

Figure 40. Rise/Fall Waveforms with 2.2 nF Load

Figure 41. Rise/Fall Waveforms with 10 nF Load

Figure 42. Quasi-Static Source Current

with V_DD=12 V⁽¹⁶⁾

Figure 43. Quasi-Static Sink Current with V_DD=12 V⁽¹⁶⁾

FAN3223 / FAN3224 / FAN3225 • Rev. 1.1.4

www.fairchildsemi.com

17

Typical Performance Characteristics

Typical characteristics are provided at 25°C and V_DD=12 V unless otherwise noted.

Figure 44. Quasi-Static Source Current

Figure 45. Quasi-Static Sink Current with V_DD=8 V⁽¹⁶⁾

with V_DD=8 V⁽¹⁶⁾

Notes:

15. For any inverting inputs pulled low, non-inverting inputs pulled high, or outputs driven high, static I_DDincreases by

the current flowing through the corresponding pull-up/down resistor shown in the block diagram.

16. The initial spike in each current waveform is a measurement artifact caused by the stray inductance of the

current-measurement loop.

Test Circuit

Figure 46. Quasi-Static I_OUT/ V_OUTTest Circuit

FAN3223 / FAN3224 / FAN3225 • Rev. 1.1.4

www.fairchildsemi.com

18

Applications Information

Input Thresholds

MillerDrive™ Gate Drive Technology

Each member of the FAN322x driver family consists of

two identical channels that may be used independently

at rated current or connected in parallel to double the

individual current capacity. In the FAN3223 and

FAN3224, channels A and B can be enabled or disabled

independently using ENA or ENB, respectively. The EN

pin has TTL thresholds for parts with either CMOS or

TTL input thresholds. If ENA and ENB are not

connected, an internal pull-up resistor enables the driver

channels by default. ENA and ENB have TTL thresholds

in parts with either TTL or CMOS INx threshold. If the

channel A and channel B inputs and outputs are

connected in parallel to increase the driver current

capacity, ENA and ENB should be connected and

driven together.

FAN322x gate drivers incorporate the MillerDrive™

architecture shown in Figure 47. For the output stage, a

combination of bipolar and MOS devices provide large

currents over a wide range of supply voltage and

temperature variations. The bipolar devices carry the

bulk of the current as OUT swings between 1/3 to 2/3

V_DDand the MOS devices pull the output to the HIGH or

LOW rail.

The purpose of the MillerDrive™ architecture is to

speed up switching by providing high current during the

Miller plateau region when the gate-drain capacitance of

the MOSFET is being charged or discharged as part of

the turn-on / turn-off process.

For applications that have zero voltage switching during

the MOSFET turn-on or turn-off interval, the driver

supplies high peak current for fast switching even

though the Miller plateau is not present. This situation

often occurs in synchronous rectifier applications

because the body diode is generally conducting before

the MOSFET is switched ON.

The FAN322x family offers versions in either TTL or

CMOS input thresholds. In the FAN322xT, the input

thresholds meet industry-standard TTL-logic thresholds

independent of the V_DDvoltage, and there is a

hysteresis voltage of approximately 0.4 V. These levels

permit the inputs to be driven from a range of input logic

signal levels for which a voltage over 2 V is considered

logic HIGH. The driving signal for the TTL inputs should

have fast rising and falling edges with a slew rate of

6 V/µs or faster, so a rise time from 0 to 3.3 V should be

550 ns or less. With reduced slew rate, circuit noise

could cause the driver input voltage to exceed the

hysteresis voltage and retrigger the driver input, causing

erratic operation.

The output pin slew rate is determined by V_DDvoltage

and the load on the output. It is not user adjustable, but

a series resistor can be added if a slower rise or fall time

at the MOSFET gate is needed.

In the FAN322xC, the logic input thresholds are

dependent on the V_DDlevel and, with V_DDof 12V, the

logic rising edge threshold is approximately 55% of V_DD

and the input falling edge threshold is approximately

38% of V_DD. The CMOS input configuration offers a

hysteresis voltage of approximately 17% of V_DD. The

CMOS inputs can be used with relatively slow edges

(approaching DC) if good decoupling and bypass

techniques are incorporated in the system design to

prevent noise from violating the input voltage hysteresis

window. This allows setting precise timing intervals by

fitting an R-C circuit between the controlling signal and

the IN pin of the driver. The slow rising edge at the IN

pin of the driver introduces a delay between the

controlling signal and the OUT pin of the driver.

Figure 47. MillerDrive™ Output Architecture

Under-Voltage Lockout

The FAN322x startup logic is optimized to drive ground-

referenced N-channel MOSFETs with an under-voltage

lockout (UVLO) function to ensure that the IC starts up

in an orderly fashion. When V_DDis rising, yet below the

3.9 V operational level, this circuit holds the output

LOW, regardless of the status of the input pins. After the

part is active, the supply voltage must drop 0.2 V before

the part shuts down. This hysteresis helps prevent

chatter when low V_DDsupply voltages have noise from

the power switching. This configuration is not suitable

for driving high-side P-channel MOSFETs because the

low output voltage of the driver would turn the P-channel

MOSFET ON with V_DDbelow 3.9 V.

Static Supply Current

In the I_DD(static) typical performance characteristics

(Figure 12 - Figure 14 and Figure 19 - Figure 21), the

curve is produced with all inputs/enables floating (OUT

is low) and indicates the lowest static I_DDcurrent for the

tested configuration. For other states, additional current

flows through the 100 k resistors on the inputs and

outputs shown in the block diagram of each part (see

Figure 5 - Figure 7). In these cases, the actual static I_DD

current is the value obtained from the curves plus this

additional current.

FAN3223 / FAN3224 / FAN3225 • Rev. 1.1.4

www.fairchildsemi.com

19

For best results, make connections to all pins as

short and direct as possible.

V_DDBypass Capacitor Guidelines

To enable this IC to turn a device ON quickly, a local

high-frequency bypass capacitor, C_BYP, with low ESR

and ESL should be connected between the VDD and

GND pins with minimal trace length. This capacitor is

in addition to the bulk electrolytic capacitance of 10 µF

to 47 µF commonly found on the driver and controller

bias circuits.

.

The FAN322x is compatible with many other

industry-standard drivers. In single input parts with

enable pins, there is an internal 100 k resistor tied

to VDD to enable the driver by default; this should

be considered in the PCB layout.

The turn-on and turn-off current paths should be

minimized, as discussed in the following section.

A typical criterion for choosing the value of C_BYPis to

keep the ripple voltage on the V_DDsupply to ≤5%. This

is often achieved with a value ≥20 times the equivalent

Figure 48 shows the pulsed gate drive current path

when the gate driver is supplying gate charge to turn the

MOSFET ON. The current is supplied from the local

bypass capacitor, C_BYP, and flows through the driver to

the MOSFET gate and to ground. To reach the high

peak currents possible, the resistance and inductance in

the path should be minimized. The localized C_BYPacts

to contain the high peak current pulses within this driver-

MOSFET circuit, preventing them from disturbing the

sensitive analog circuitry in the PWM controller.

load capacitance C_EQV, defined here as Q_GATE/V_DD

.

Ceramic capacitors of 0.1 µF to 1 µF or larger are

common choices, as are dielectrics, such as X5R and

X7R with good temperature characteristics and high

pulse current capability.

If circuit noise affects normal operation, the value of

C_BYPmay be increased to 50-100 times the C_EQV, or

C_BYPmay be split into two capacitors. One should be a

larger value, based on equivalent load capacitance, and

the other a smaller value, such as 1-10 nF mounted

closest to the VDD and GND pins to carry the higher

frequency components of the current pulses. The

bypass capacitor must provide the pulsed current from

both of the driver channels and, if the drivers are

switching simultaneously, the combined peak current

sourced from the C_BYPwould be twice as large as when

a single channel is switching.

Layout and Connection Guidelines

The FAN3223-25 family of gate drivers incorporates

fast-reacting input circuits, short propagation delays,

and powerful output stages capable of delivering current

peaks over 4 A to facilitate voltage transition times from

under 10 ns to over 150 ns. The following layout and

connection guidelines are strongly recommended:

Figure 48. Current Path for MOSFET Turn-On

.

Keep high-current output and power ground paths

separate logic and enable input signals and signal

ground paths. This is especially critical when

dealing with TTL-level logic thresholds at driver

inputs and enable pins.

Figure 49 shows the current path when the gate driver

turns the MOSFET OFF. Ideally, the driver shunts the

current directly to the source of the MOSFET in a small

circuit loop. For fast turn-off times, the resistance and

inductance in this path should be minimized.

.

Keep the driver as close to the load as possible to

minimize the length of high-current traces. This

reduces the series inductance to improve high-

speed switching, while reducing the loop area that

can radiate EMI to the driver inputs and

surrounding circuitry.

.

If the inputs to a channel are not externally

connected, the internal 100 k resistors indicated

on block diagrams command a low output. In noisy

environments, it may be necessary to tie inputs of

an unused channel to VDD or GND using short

traces to prevent noise from causing spurious

output switching.

Many high-speed power circuits can be susceptible

to noise injected from their own output or other

external sources, possibly causing output re-

triggering. These effects can be obvious if the

circuit is tested in breadboard or non-optimal circuit

layouts with long input, enable, or output leads.

Figure 49. Current Path for MOSFET Turn-Off

FAN3223 / FAN3224 / FAN3225 • Rev. 1.1.4

www.fairchildsemi.com

20

Truth Table of Logic Operation

Operational Waveforms

The FAN3225 truth table indicates the operational states

using the dual-input configuration. In a non-inverting

driver configuration, the IN- pin should be a logic LOW

signal. If the IN- pin is connected to logic HIGH, a disable

function is realized, and the driver output remains LOW

regardless of the state of the IN+ pin.

At power-up, the driver output remains LOW until the

V_DDvoltage reaches the turn-on threshold. The

magnitude of the OUT pulses rises with V_DDuntil

steady-state V_DDis reached. The non-inverting

operation illustrated in Figure 52 shows that the output

remains LOW until the UVLO threshold is reached, then

the output is in-phase with the input.

IN+

0

IN-

0

OUT

0

1

0

1

0

1

In the non-inverting driver configuration in Figure 50, the

IN- pin is tied to ground and the input signal (PWM) is

applied to IN+ pin. The IN- pin can be connected to logic

HIGH to disable the driver and the output remains LOW,

regardless of the state of the IN+ pin.

Figure 52. Non-Inverting Startup Waveforms

For the inverting configuration of Figure 51, startup

waveforms are shown in Figure 53. With IN+ tied to

VDD and the input signal applied to IN–, the OUT

pulses are inverted with respect to the input. At power-

up, the inverted output remains LOW until the V_DD

voltage reaches the turn-on threshold, then it follows the

input with inverted phase.

Figure 50. Dual-Input Driver Enabled,

Non-Inverting Configuration

In the inverting driver application in Figure 51, the IN+

pin is tied HIGH. Pulling the IN+ pin to GND forces the

output LOW, regardless of the state of the IN- pin.

Figure 51. Dual-Input Driver Enabled,

Inverting Configuration

Figure 53. Inverting Startup Waveforms

FAN3223 / FAN3224 / FAN3225 • Rev. 1.1.4

www.fairchildsemi.com

21

Thermal Guidelines

Gate drivers used to switch MOSFETs and IGBTs at

high frequencies can dissipate significant amounts of

power. It is important to determine the driver power

dissipation and the resulting junction temperature in the

application to ensure that the part is operating within

acceptable temperature limits.

To give a numerical example, assume for a 12 V V_DD

(V_BIAS) system, the synchronous rectifier switches of

Figure 54 have a total gate charge of 60 nC at

V_GS= 7 V. Therefore, two devices in parallel would have

120 nC gate charge. At a switching frequency of

300 kHz, the total power dissipation is:

The total power dissipation in a gate driver is the sum of

P_GATE= 120 nC • 7 V • 300 kHz • 2 = 0.504 W

P_DYNAMIC= 3.0 mA • 12 V • 1 = 0.036 W

(5)

(6)

two components, P_GATEand P_DYNAMIC

:

P_TOTAL= P_GATE+ P_DYNAMIC

(1)

P

_TOTAL= 0.540 W

(7)

P_GATE(Gate Driving Loss): The most significant power

loss results from supplying gate current (charge per

unit time) to switch the load MOSFET on and off at

the switching frequency. The power dissipation that

results from driving a MOSFET at a specified gate-

The SOIC-8 has

characterization parameter of

a

junction-to-board thermal

_JB

= 42°C/W. In a

system application, the localized temperature around

the device is a function of the layout and construction of

the PCB along with airflow across the surfaces. To

ensure reliable operation, the maximum junction

temperature of the device must be prevented from

exceeding the maximum rating of 150°C; with 80%

derating, T_Jwould be limited to 120°C. Rearranging

Equation 4 determines the board temperature required

to maintain the junction temperature below 120°C:

source voltage, V_GS

, with gate charge, Q_G, at

switching frequency, f_SW, is determined by:

P_GATE= Q_G• V_GS• f_SW• n

(2)

where n is the number of driver channels in use (1 or 2).

P_DYNAMIC(Dynamic Pre-Drive Shoot-through

/

Current): A power loss resulting from internal current

consumption under dynamic operating conditions,

including pin pull-up / pull-down resistors. The internal

current consumption (I_DYNAMIC) can be estimated using

the graphs in Figure 15 and Figure 16 of the Typical

Performance Characteristics to determine the current

I_DYNAMICdrawn from V_DDunder actual operating

conditions:



•

(8)

(9)

T

_B,MAX= T_J- P_TOTAL

JB

T_B,MAX= 120°C – 0.54 W • 42°C/W = 97°C

P_DYNAMIC= I_DYNAMIC• V_DD• n

(3)

where n is the number of driver ICs in use. Note that n is

usually be one IC even if the IC has two channels,

unless two or more.driver ICs are in parallel to drive a

large load.

Once the power dissipated in the driver is determined,

the driver junction rise with respect to circuit board can

be evaluated using the following thermal equation,

_JB

assuming

was determined for a similar thermal

design (heat sinking and air flow):



(4)

T_J= P_TOTAL

•

_JB+ T_B

where:

T_J

= driver junction temperature;

_JB

= (psi) thermal characterization parameter

relating temperature rise to total power

dissipation; and

T_B

= board temperature in location as defined in

the Thermal Characteristics table.

FAN3223 / FAN3224 / FAN3225 • Rev. 1.1.4

www.fairchildsemi.com

22

Typical Application Diagrams

Figure 54. High Current Forward Converter

with Synchronous Rectification

Figure 55.

Center-Tapped Bridge Output with

Synchronous Rectifiers

Figure 56. Secondary Controlled Full Bridge with Current Doubler Output, Synchronous

Rectifiers (Simplified)

FAN3223 / FAN3224 / FAN3225 • Rev. 1.1.4

www.fairchildsemi.com

23

Table 1.

Type


型号：	FAN3224TMX_F085
厂家：	FAIRCHILD SEMICONDUCTOR
描述：	Full Bridge Based Peripheral Driver, PDSO8 驱动光电二极管接口集成电路驱动器
文件：	总27页 (文件大小：1533K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

FAN3224TMX_F085 [FAIRCHILD]

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