FAN4174IS5X [FAIRCHILD]
Single and Dual, Ultra-Low Cost, Rail-to-Rail I/O, CMOS Amplifier; 单路和双路,超低成本,轨至轨I / O, CMOS放大器型号: | FAN4174IS5X |
厂家: | FAIRCHILD SEMICONDUCTOR |
描述: | Single and Dual, Ultra-Low Cost, Rail-to-Rail I/O, CMOS Amplifier |
文件: | 总15页 (文件大小:1092K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
May 2008
FAN4174 / FAN4274
Single and Dual, Ultra-Low Cost, Rail-to-Rail I/O,
CMOS Amplifier
Features
Description
The FAN4174 (single) and FAN4274 (dual) are ultra-low
cost voltage feedback amplifiers with CMOS inputs that
consume only 200µA of supply current per amplifier,
while providing ±33mA of output short-circuit current.
These amplifiers are designed to operate from 2.5V to
5V supplies. The common mode voltage range extends
beyond the negative and positive rails.
200µA Supply Current per Amplifier
3.7MHz Bandwidth
Output Swing to Within 10mV of Either Rail
Input Voltage Range Exceeds the Rails
3V/µs Slew Rate
The FAN4174 and FAN4274 are designed on a CMOS
process and provide 3.7MHz of bandwidth and 3V/μs of
slew rate at a supply voltage of 5V. The combination of
low power, rail-to-rail performance, low-voltage
operation, and tiny package options make this amplifier
family well suited for use in many general-purpose and
battery-powered applications.
25nV/√Hz Input Voltage Noise
Replaces KM4170 and KM4270
FAN4174 Competes with OPA340 and TLV2461;
Available in SC70-5 and SOT23-5 Packages
FAN4274 Competes with OPA2340 and TLV2462;
Available in MSOP-8 Package
Fully Specified at +2.7V and +5V Supplies
Applications
Portable / Battery-powered Applications
PCMCIA, USB
Mobile Communications, Cellular Phones, Pagers
Notebooks and PDAs
Sensor Interface
A/D Buffer
Active Filters
Signal Conditioning
Portable Test Instruments
Figure 1. Frequency vs. Gain
Ordering Information
Operating
Temperature Range
Packing
Method
Part Number
Package
Eco Status
Tape and Reel
(3000)
FAN4174IP5X
FAN4174IS5X
FAN4274IMU8X
-40 to +85°C
5-Lead SC70 Package
RoHS
Tape and Reel
(3000)
-40 to +85°C
-40 to +85°C
5-Lead SOT23 Package
RoHS
RoHS
Tape and Reel
(3000)
8-Lead Molded Small Outline Package
For Fairchild’s definition of “green” Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.
© 2004 Fairchild Semiconductor Corporation
FAN4174/FAN4274 • Rev. 1.0.4
www.fairchildsemi.com
Typical Application
Figure 2. Pin Configuration
© 2004 Fairchild Semiconductor Corporation
FAN4174/FAN4274 • Rev. 1.0.4
www.fairchildsemi.com
2
Pin Configurations
Figure 3. FAN4174 SOT23
Figure 4. FAN4147 SC70
Figure 5. FAN4274 MSOP
FAN4174 Pin Assignments
Pin #
Name
OUT
-VS
Description
Output
1
2
3
4
5
Negative Supply
Positive Supply
Negative Input
Positive Supply
+IN
-IN
+VS
FAN4274 Pin Assignments
Pin #
Name
OUT1
-IN1
Description
1
2
3
4
5
6
7
8
Output, Channel 1
Negative Input, Channel 1
Positive Input, Channel 1
Negative Supply
+IN1
-VS
+IN2
-IN2
Positive Input, Channel 2
Negative Input, Channel 2
Output, Channel 2
OUT2
+VS
Positive Supply
© 2004 Fairchild Semiconductor Corporation
FAN4174/FAN4274 • Rev. 1.0.4
www.fairchildsemi.com
3
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device
reliability. The absolute maximum ratings are stress ratings only. Functional operation under any of these conditions
is NOT implied. Performance and reliability are guaranteed only if operating conditions are not exceeded.
Symbol
VCC
Parameter
Supply Voltage
Min.
0
Max.
6
Unit
V
VIN
Input Voltage Range
-VS-0.5
+VS+0.5
+150
+150
+300
256
V
TJ
Junction Temperature
Storage Temperature
Lead Soldering, 10 Seconds
°C
°C
°C
TSTG
TL
-65
5-Lead SOT23
Thermal Resistance(1)
°C/W
ΘJA
5-Lead SC70
8-Lead MSOP
331
206
Note:
1. Package thermal resistance JEDEC standard, multi-layer test boards, still air.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
Min.
Typ.
Max.
Unit
TA
Operating Temperature Range
-40
+85
°C
© 2004 Fairchild Semiconductor Corporation
FAN4174/FAN4274 • Rev. 1.0.4
www.fairchildsemi.com
4
Electrical Specifications at +2.7V
VS=+2.7V, G=2, RL=10kΩ to VS/2, RF=5kΩ; unless otherwise noted.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
Frequency Domain Response
UGBW
G=+1
4
2.5
4
MHz
MHz
MHz
-3dB Bandwidth
BWSS
GBWP
Gain Bandwidth Product
Time Domain Response
tR, fF
OS
Rise and Fall Time
VO=1.0V Step
300
5
ns
%
Overshoot
Slew Rate
VO=1.0V Step
SR
VO=3V Step, G=-1
3
V/µs
Distortion and Noise Response
HD2
2nd Harmonic Distortion
VO=1VPP, 10kHz
VO=1VPP, 10kHz
VO=1VPP, 10kHz
-66
-67
0.1
dBc
dBc
HD3
3rd Harmonic Distortion
Total Harmonic Distortion
Input Voltage Noise
THD
%
en
26
nV/√Hz
dB
XTALK
Crosstalk (FAN4274)
100kHZ
-100
DC Performance
VIO
dVIO
Ibn
Input Offset Voltage(2)
-6
0
2.1
5
+6
mV
µV/°C
pA
Average Drift
Input Bias Current
PSRR
AOL
IS
Power Supply Rejection Ratio(2)
DC
DC
50
73
98
200
dB
Open-loop Gain
Supply Current per Amplifier(2)
dB
300
µA
Input Characteristics
RIN
CIN
Input Resistance
10
GΩ
Input Capacitance
1.4
pF
-0.3 to
2.6
FAN4174 (Typical)
FAN4274 (Typical)
Input Common Mode Voltage
Range
CMIR
V
-0.3 to
3.0
FAN4174
FAN4274
DC, VCM=OV to 2.2V
DC, VCM=OV to 2.2V
50
50
65
65
Common Mode
CMRR
dB
Rejection Ratio(2)
Output Characteristics
0.01 to
2.69
0.03
2.65
RL=10kΩ to VS/2
RL=1kΩ to VS/2
VO
Output Voltage Swing(2)
V
0.05 to
2.55
ISC
VS
Short Circuit Output Current
Power Supply Operating Range
+34/-12
mA
V
2.5 to
5.5
Note:
2. 100% tested at 25°C.
© 2004 Fairchild Semiconductor Corporation
FAN4174/FAN4274 • Rev. 1.0.4
www.fairchildsemi.com
5
Electrical Specifications at +5V
VS=+5V, G=2, RL=10kΩ to VS/2, RF= 5kΩ; unless otherwise noted.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
Frequency Domain Response
UGBW
G=+1
3.7
2.3
3.7
MHz
MHz
MHz
-3dB Bandwidth
BWSS
GBWP
Gain Bandwidth Product
Time Domain Response
tR, fF
OS
Rise and Fall Time
VO=1.0V Step
300
5
ns
%
Overshoot
Slew Rate
VO=1.0V Step
SR
VO=3V Step, G=-1
3
V/µs
Distortion and Noise Response
HD2
2nd Harmonic Distortion
VO=1VPP, 10kHz
VO=1VPP, 10kHz
VO=1VPP, 10kHz
-80
-80
dBc
dBc
HD3
3rd Harmonic Distortion
Total Harmonic Distortion
Input Voltage Noise
THD
0.02
25
%
en
nV/√Hz
dB
XTALK
Crosstalk (FAN4274)
100kHZ
-100
DC Performance
VIO
dVIO
Ibn
Input Offset Voltage(3)
-8
0
+8
mV
µV/°C
pA
Average Drift
2.9
5
Input Bias Current
PSRR
AOL
IS
Power Supply Rejection Ratio(3)
DC
DC
50
73
dB
Open-loop Gain
Supply Current per Amplifier(3)
102
200
dB
300
µA
Input Characteristics
RIN
CIN
Input Resistance
10
GΩ
Input Capacitance
1.2
pF
Input Common Mode Voltage
Range
-0.3 to
5.3
CMIR
Typical
V
CMRR
Common Mode Rejection Ratio(3) DC, VCM=0V to VS
58
73
dB
Output Characteristics
0.01 to
4.99
0.03
4.95
RL=10kΩ to VS/2
RL=1kΩ to VS/2
VO
Output Voltage Swing(3)
V
0.1 to
4.9
ISC
VS
Short Circuit Output Current
±33
mA
V
2.5 to
5.5
Power Supply Operating Range
Note:
3. 100% tested at 25°C.
© 2004 Fairchild Semiconductor Corporation
FAN4174/FAN4274 • Rev. 1.0.4
www.fairchildsemi.com
6
Typical Performance Characteristics
VS=+2.7, G=2, RL=10kΩ to VS/2, RF=5kΩ; unless otherwise noted.
Figure 6. Non-Inverting Frequency Response (+5)
Figure 8. Non-Inverting Frequency Response
Figure 10. Frequency Response vs. CL
Figure 7. Inverting Frequency Response (+5V)
Figure 9. Inverting Frequency Response
Figure 11. Frequency Response vs. RL
Figure 12. Large Signal Frequency Response (+5V)
Figure 13. Open-loop Gain and Phase vs. Frequency
© 2004 Fairchild Semiconductor Corporation
FAN4174/FAN4274 • Rev. 1.0.4
www.fairchildsemi.com
7
Typical Performance Characteristic
VS=+2.7, G=2, RL=10kΩ to VS/2, RF=5kΩ; unless otherwise noted.
Figure 14. 2nd and 3rd Harmonic Distortion
Figure 16. 3rd Harmonic Distortion vs. VO
Figure 18. PSRR VS=5V
Figure 15. 2nd Harmonic Distortion vs. VO
Figure 17. CMRR VS=5V
Figure 19. Output Swing vs. Load
Figure 20. Pulse Response vs. Common Mode
Voltage
Figure 21. Input Voltage Noise
© 2004 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN4174/FAN4274 • Rev. 1.0.4
8
Application Information
General Description
Overdrive Recovery
The FAN4174 amplifier includes single-supply, general-
purpose, voltage-feedback amplifiers, fabricated on a
bi-CMOS process. The family features a rail-to-rail input
and output and is unity gain stable. The typical non-
inverting circuit schematic is shown in Figure 22.
Overdrive of an amplifier occurs when the output and/or
input ranges are exceeded. The recovery time varies
based on whether the input or output is overdriven and
by how much the range is exceeded. The FAN4174
typically recovers in less than 500ns from an overdrive
condition. Figure 24 shows the FAN4174 amplifier in an
overdriven condition.
Figure 24. Overdrive Recovery
Figure 22. Typical Non-inverting Configuration
Driving Capacitive Loads
Input Common Mode Voltage
Figure 10 illustrates the response of the FAN4174
amplifier family. A small series resistance (RS) at the
output of the amplifier, illustrated in Figure 25, improves
stability and settling performance. RS values in Figure
10 were chosen to achieve maximum bandwidth with
less than 2dB of peaking. For maximum flatness, use a
larger RS. Capacitive loads larger than 500pF require
the use of RS.
The common mode input range extends to 300mV
below ground and to 100mV above VS in single supply
operation. Exceeding these values does not cause
phase reversal; however, if the input voltage exceeds
the rails by more than 0.5V, the input ESD devices
begin to conduct. The output stays at the rail during this
overdrive condition. If the absolute maximum input VIN
(700mV beyond either rail) is exceeded, externally limit
the input current to ±5mA, as shown in Figure 23.
Figure 23. Circuit for Input Current Protection
Figure 25. Typical Topology for Driving a
Capacitive Load
Power Dissipation
Driving a capacitive load introduces phase-lag into the
output signal, which reduces phase margin in the
amplifier. The unity gain follower is the most sensitive
configuration. In a unity gain follower configuration, the
The maximum internal power dissipation allowed is
directly related to the maximum junction temperature. If
the maximum junction temperature exceeds 150°C,
performance degradation occurs. If the maximum
junction temperature exceeds 150°C for an extended
time, device failure may occur.
FAN4174 amplifier family requires
resistor to drive a 100pF load.
a
300Ω series
© 2004 Fairchild Semiconductor Corporation
FAN4174/FAN4274 • Rev. 1.0.4
www.fairchildsemi.com
9
Layout Considerations
General layout and supply bypassing play major roles
in high-frequency performance. Fairchild evaluation
boards help guide high-frequency layout and aid in
device testing and characterization. Follow the steps
below as a basis for high-frequency layout:
1.
2.
Include 6.8μF and 0.01μF ceramic capacitors.
Place the 6.8μF capacitor within 0.75 inches
of the power pin.
3.
4.
Place the 0.01μF capacitor within 0.1 inches
of the power pin.
Remove the ground plane under and around
the part, especially near the input and output
pins, to reduce parasitic capacitance.
Minimize all trace lengths to reduce series
inductances.
Refer to the evaluation board layouts shown in
Figures 28-31 for more information.
When evaluating only one channel, complete the
following on the unused channel:
1.
2.
Ground the non-inverting input.
Figure 26. FAN4174 Evaluation Board Schematic
(KEV002/KEB011)
Short the output to the inverting input.
Evaluation Board Information
The following evaluation boards are available to aid in
the testing and layout of this device:
Evaluation
Description
Products
Board
Single Channel,
Dual Supply, 5
KEB002
FAN4174IS5X
and 6-Lead SOT23
Dual Channel,
Dual Supply
8-Lead MSOP
KEB010
KEB011
FAN4274IMU8X
FAN4174IP5X
Single Channel,
Dual Supply, 5
and 6-Lead SC70
Evaluation board schematics are shown in Figure 26
and Figure 27; layouts are shown in Figures 28-31.
Figure 27. FAN4274 Evaluation Board Schematic
(KEB010)
© 2004 Fairchild Semiconductor Corporation
FAN4174/FAN4274 • Rev. 1.0.4
www.fairchildsemi.com
10
Board Layout Information
Figure 28. KEB002 (Top Side)
Figure 29. KEB002 (Bottom Side)
Figure 30. KEB010 (Top Side)
Figure 31. KEB010 (Bottom Side)
© 2004 Fairchild Semiconductor Corporation
FAN4174/FAN4274 • Rev. 1.0.4
www.fairchildsemi.com
11
Physical Dimensions
SYMM
C
L
3.00
2.80
0.95
0.95
A
5
4
B
3.00
2.60
1.70
1.50
2.60
1
2
3
(0.30)
1.00
0.50
0.30
0.95
0.20
C A B
1.90
0.70
TOP VIEW
LAND PATTERN RECOMMENDATION
SEE DETAIL A
1.30
0.90
1.45 MAX
C
0.15
0.05
0.22
0.08
0.10 C
NOTES: UNLESS OTHEWISE SPECIFIED
A) THIS PACKAGE CONFORMS TO JEDEC
MO-178, ISSUE B, VARIATION AA,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
GAGE PLANE
0.25
C) MA05Brev5
8°
0°
0.55
0.35
SEATING PLANE
0.60 REF
Figure 32. 5-Lead SOT-23 Package
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically
the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
© 2004 Fairchild Semiconductor Corporation
FAN4174/FAN4274 • Rev. 1.0.4
www.fairchildsemi.com
12
Physical Dimensions
Figure 33. 5-Lead SC70 Package
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically
the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
© 2004 Fairchild Semiconductor Corporation
FAN4174/FAN4274 • Rev. 1.0.4
www.fairchildsemi.com
13
Physical Dimensions
(0.45)
(1.30)
0.65
3.00±0.10
A
B
(5.50) (4.20)
4.90±0.15
3.00±0.10
PIN #1 ID
QUADRANT
LAND PATTERN RECOMMENDATION
SEE DETAIL A
TOP VIEW
1.10MAX
0.23
0.13
0.150
0.050
0.380
0.270
0.65
END VIEW
C
12° TOP & BOTTOM
SIDE VIEW
0.10
A B C
NOTES:
A. CONFORMS TO JEDEC MO-187
B, DIMENSIONS ARE IN MM
C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD
FLASH, AND TIE BAR EXTRUSIONS
D. DIMENSIONS AND TOLERANCES ARE PER
ASME Y14.5M, 1994
Gauge
Plane
Seating
Plane
E LANDPATTERN AS PER IPC7351 #TSOP65P490X110-8BL
8°
0°
0.25
MKT-MUA08AREVB
0.70
0.40
0.95
DETAIL A
Figure 34. 8-Lead Molded Small Outline Package (MSOP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically
the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
© 2004 Fairchild Semiconductor Corporation
FAN4174/FAN4274 • Rev. 1.0.4
www.fairchildsemi.com
14
© 2004 Fairchild Semiconductor Corporation
FAN4174/FAN4274 • Rev. 1.0.4
www.fairchildsemi.com
15
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