FAN4800C_技术文档

April 2009

FAN4800A/C, FAN4801/1S/2/2L

PFC/PWM Controller Combination

Features

Description

The

highly

integrated

FAN4800A/C

and

Pin-to-Pin Compatible with ML4800 and FAN4800

and CM6800 and CM6800A

FAN4801/1S/2/2L are specially designed for power

supplies that consist of boost PFC and PWM. They

require very few external components to achieve

versatile protections / compensation. They are available

in 16-pin DIP and SOP packages.

PWM Configurable for Current-Mode or

Feed-Forward Voltage-Mode Operation

Internally Synchronized Leading-Edge PFC and

Trailing-Edge PWM in one IC

The PWM can be used in either current or voltage

mode. In voltage mode, feed-forward from the PFC

output bus can reduce the secondary output ripple.

Low Operating Current

Innovative Switching-Charge Multiplier Divider

Average-Current-Mode for Input-Current Shaping

PFC Over-Voltage and Under-Voltage Protections

PFC Feedback Open-Loop Protection

Peak Current Limiting for PFC

Compared with older productions, ML4800 and

FAN4800, FAN4800A/C and FAN4801/1S/2/2L have

lower operation current that save power consumption in

external devices. FAN4800A/C and FAN4801/1S/2/2L

have accurate 49.9% maximum duty of PWM that

makes the hold-up time longer. Specifically, the

brownout protection and PFC soft-start functions are not

in ML4800 and FAN4800.

Cycle-by-Cycle Current Limiting for PWM

Power-On Sequence Control and Soft-Start

Brownout Protection

To start evaluating FAN4800A/C, FAN4801/1S/2/2L for

replacing existing FAN4800 and ML4800 boards, five

things must be done before the fine-tuning procedure:

Interleaved PFC/PWM Switching

1. Change R_ACresister from the old value to a higher

FAN4801/1S/2/2L Improve Efficiency at Light Load

resister: between 6MΩ to 8MΩ.

f_RTCT=4•f_PFC=4•f_PWMfor FAN4800A and

FAN4801/1S

2. Change RT/CT pin from the existing values to

R_T=6.8KΩ and C_T=1000pF to have f_PFC=64KHz,

_PWM=64KHz.

f

f_RTCT=4•f_PFC=2•f_PWMfor FAN4800C and

FAN4802/2L

3. VRMS pin needs to be 1.224V at V_IN=85 V_ACfor

universal input application from line input from

85V_ACto 270 V_AC. Both poles for the V_rmsof

FAN4801/1S/2/2L don’t need to substantially

slower than FAN4800; about 5 to 10 times.

Applications

Desktop PC Power Supply

4. At full load, the average V_EAneeds to ~4.5V and

the ripple on the V_EAneeds to be less than 400mV.

Internet Server Power Supply

LCD TV, Monitor Power Supply

UPS

5. Soft-Start pin, the soft-start current has been

reduced to half from the FAN4800 capacitor.

Battery Charger

DC Motor Power Supply

Monitor Power Supply

Telecom System Power Supply

Distributed Power

Related Resources

Complete design instructions are detailed in application

note AN-6078SC (available in Chinese only).

FAN4800A/C, FAN4801/1S/2/2L • Rev. 1.0.2

www.fairchildsemi.com

1

Ordering Information

Operating

Temperature Range

Packing

Method

Eco

Status

Part Number

Package

FAN4800ANY

FAN4800CNY

FAN4800AMY

FAN4800CMY

FAN4801NY

FAN4801SNY

FAN4802NY

FAN4802LNY

FAN4801MY

FAN4801SMY

FAN4802MY

FAN4802LMY

-40°C to +105°C

Green

16-pin Dual In-Line Package (DIP)

16-pin Small Out-Line Package (SOP)

16-pin Dual In-Line Package (DIP)

16-pin Small Out-Line Package (SOP)

Tube

Tape and Reel

Tube

Tape and Reel

For Fairchild’s definition of “green” Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.

Part Number

FAN4800ANY

FAN4800AMY

FAN4800CNY

FAN4800CMY

FAN4801NY

FAN4801SNY

FAN4802NY

FAN4802LNY

FAN4801MY

FAN4801SMY

FAN4802MY

FAN4802LMY

PFC:PWM Frequency Ratio

Brown Out / In

1.05V / 1.9V

0.9V / 1.65V

1.05V / 1.9V

0.9V / 1.65V

Range In / Out

NA

1:1

1:2

1:1

1:2

1:1

1:2

NA

1.95V / 2.45V

2.8V / 3.35V

1.95V / 2.45V

2.8V / 3.35V

1.95V / 2.45V

FAN4800A/C, FAN4801/1S/2/2L • Rev. 1.0.2

www.fairchildsemi.com

2

Application Diagram

VEA

FBPFC

VREF

VDD

IEA

IAC

ISENSE

VDD

VRMS

SS

OPFC

OPWM

GND

FBPWM

RT/CT

RAMP

ILIMIT

VREF

FAN4800A/C

FAN4801/1S/2/2L

Secondary

Figure 1. Typical Application Current Mode

FAN4800A/C, FAN4801/1S/2/2L • Rev. 1.0.2

www.fairchildsemi.com

3

Application Diagram

VEA

FBPFC

VREF

VDD

IEA

IAC

ISENSE

VDD

VRMS

SS

OPFC

OPWM

GND

FBPWM

RT/CT

RAMP

ILIMIT

VREF

FAN4800A/C

FAN4801/1S/2/2L

VREF

Secondary

Figure 2. Typical Application Voltage Mode

FAN4800A/C, FAN4801/1S/2/2L • Rev. 1.0.2

www.fairchildsemi.com

4

Block Diagram

Figure 3.

FAN4800A/C Function Block Diagram

Figure 4.

FAN4801/1S/2/2L Function Block Diagram

FAN4800A/C, FAN4801/1S/2/2L • Rev. 1.0.2

www.fairchildsemi.com

5

Marking Information

F – Fairchild Logo

Z – Plant Code

X – 1-Digit Year Code

Y – 1-Digit Week Code

TT – 2-Digit Die Run Code

T – Package Type (N:DIP, M:SOP)

P – Y: Green Package

M – Manufacture Flow Code

Figure 5.

Top Mark

FAN4800A/C, FAN4801/1S/2/2L • Rev. 1.0.2

www.fairchildsemi.com

6

Pin Configuration

Figure 6.

Pin Configuration (Top View)

Pin Definitions

Pin #

Name

Description

Output of PFC Current Amplifier. The signal from this pin is compared with an internal

sawtooth to determine the pulse width for PFC gate drive.

1

IEA

Input AC Current. For normal operation, this input provides current reference for the multiplier.

The suggested maximum IAC is 100µA.

2

IAC

PFC Current Sense. The non-inverting input of the PFC current amplifier and the output of

multiplier and PFC ILIMIT comparator.

3

4

ISENSE

VRMS

Line-Voltage Detection. Line voltage detection. The pin is used for PFC multiplier.

PWM Soft-Start. During startup, the SS pin charges an external capacitor with a 10µA

constant current source. The voltage on FBPWM is clamped by SS during startup. In the event

of a protection condition occurring and/or PWM disabled, the SS pin is quickly discharged.

5

SS

6

7

FBPWM

RT/CT

PWM Feedback Input. The control input for voltage-loop feedback of PWM stage.

Oscillator RC Timing Connection. Oscillator timing node; timing set by R_Tand C_T.

PWM RAMP Input. In current mode, this pin functions as the current sense input; when in

voltage mode, it is the feed forward sense input from PFC output 380V (feedforward ramp).

8

RAMP

9

ILIMIT

GND

Peak Current Limit Setting for PWM. The peak current limits setting for PWM.

Ground.

10

PWM Gate Drive. The totem-pole output drive for PWM MOSFET. This pin is internally

clamped under 15V to protect the MOSFET.

11

12

OPWM

OPFC

PFC Gate Drive. The totem pole output drive for PWM MOSFET. This pin is internally clamped

under 15V to protect the MOSFET.

Supply. The power supply pin. The threshold voltages for startup and turn-off are 11V and

9.3V, respectively. The operating current is lower than 10mA.

13

14

15

VDD

VREF

FBPFC

Reference Voltage. Buffered output for the internal 7.5V reference.

Voltage Feedback Input for PFC. The feedback input for PFC voltage loop. The inverting

input of PFC error amplifier. This pin is connected to the PFC output through a divider network.

Output of PFC Voltage Amplifier. The error amplifier output for PFC voltage feedback loop.

A compensation network is connected between this pin and ground.

16

VEA

FAN4800A/C, FAN4801/1S/2/2L • Rev. 1.0.2

www.fairchildsemi.com

7

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device

reliability. The absolute maximum ratings are stress ratings only.

Symbol

V_DD

Parameter

Min.

Max.

30

Unit

V

DC Supply Voltage

V_H

SS, FBPWM, RAMP, OPWM, OPFC

IAC, VRMS, RT/CT, ILIMIT, FBPFC, VEA

VREF

-0.3

30.0

7.0

V

V_L

V

V_VREF

V_IEA

7.5

V

IEA

0

V_VREF+0.3

0.7

V

V_N

ISENSE

-5.0

V

I_AC

Input AC Current

1

mA

A

I_REF

V_REFOutput Current

5

I_PFC-OUT

I_PWM-OUT

P_D

Peak PFC OUT Current, Source or Sink

Peak PWM OUT Current, Source or Sink

Power Dissipation T_A< 50°C

0.5

A

800

mW

°C/W

°C

kV

V

DIP

SOP

80.80

104.10

+125

+150

+260

4.5

R_{Θ j-a}

Thermal Resistance (Junction-to-Air)

T_J

T_STG

T_L

Operating Junction Temperature

Storage Temperature Range

Lead Temperature(Soldering)

-40

-55

Human Body Model, JESD22-A114

Charged Device Model, JESD22-C101

Electrostatic Discharge

Capability

ESD

1000

Notes:

1. All voltage values, except differential voltage, are given with respect to GND pin.

2. Stresses beyond those listed under “absolute maximum ratings “may cause permanent damage to the device.

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended

operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not

recommend exceeding them or designing to Absolute Maximum Ratings.

Symbol

Parameter

Min.

Typ.

Max.

Unit

T_A

Operating Ambient Temperature

-40

+105

°C

FAN4800A/C, FAN4801/1S/2/2L • Rev. 1.0.2

www.fairchildsemi.com

8

Electrical Characteristics

V_DD=15V, T_A=25°C, R_T=6.8kΩ, C_T=1000pF unless noted operating specifications.

Symbol

Parameter

Conditions

Min. Typ. Max. Units

VDD Section

I_{DD ST}

Startup Current

V_DD=V_TH-ON-0.1V; OPFC OPWM Open

V_DD=13V; OPFC OPWM Open

30

80

µA

I_DD-OP

Operating Current

2.0

10

2.6

5.0

mA

Turn-On Threshold

Voltage

V_TH-ON

11

12

V

Hysteresis

V_DDOVP

1.5

27

1.9

29

V

ΔV_TH

V_DD-OVP

28

1

V_DDOVP Hysteresis

ΔV_DD-OVP

Oscillator

f_OSC-RT/CT

RT/CT Frequency

R_T=6.8kΩ, C_T=1000pF

240

60

256

64

268

67

kHz

PFC & PWM Frequency

f_OSC

FAN4800C,FAN4802/02L

PWM Frequency

120

128

134

11V ≦ V_DD≦ 22V

f_DV

f_DT

Voltage Stability

2

%

Temperature Stability

-40°C ~ +105°C

Total Variation

f_TV

Line, Temperature

58

70

kHz

(PFC & PWM)⁽³⁾

f_RV

I_Discharge

f_RANGE

t_PFCD

Ramp Voltage⁽³⁾

Discharge Current

Frequency Range⁽³⁾

PFC Dead Time

Valley to Peak

2.8

V

V_RAMP=0V, V_RT/CT=2.5V

6.5

50

15

75

mA

kHz

ns

R_T=6.8kΩ, C_T=1000pF

400

600

800

VREF

V_VREF

Reference Voltage

I_REF=0mA, C_REF=0.1µF

7.4

7.5

30

7.6

50

V

Load Regulation of

Reference Voltage

C_REF=0.1µF, I_REF=0mA to 3.5mA

mV

ΔV_VREF1

ΔV_VREF2

V_VDD=14V, Rise/Fall Time > 20µs

Line Regulation of

Reference Voltage

C_REF=0.1µF, V_VDD=11V to 22V

25

mV

(3)

Temperature Stability

Total Variation

-40°C ~ +105°C

0.4

0.5

7.65

25

%

V

ΔV_VREF-DT

(3)

Line, Load, Temp

T_J=125°C, 0 ~ 1000HRs

V_VREF> 7.35V

7.35

5

ΔV_VREF-TV

(3)

Long-Term Stability

Maximum Current

Output Short Circuit

mV

mA

ΔV_VREF-LS

I_REF-MAX

.

5

(3)

I_OS

25

PFC OVP Comparator

V_PFC-OVP

Over-Voltage Protection

PFC OVP Hysteresis

2.70

200

2.75

250

2.80

300

V

mV

ΔV_PFC-OVP

Low-Power Detect Comparator

V_EAOFF

VEA Voltage OFF OPFC

0.2

0.3

0.4

V

V_INOK Comparator

Voltage Level on FBPFC

V_RD-FBPFC

to Enable OPWM During

Startup

2.3

2.4

2.5

V

Hysteresis

1.15

1.25

1.35

ΔV_RD-FBPFC

FAN4800A/C, FAN4801/1S/2/2L • Rev. 1.0.2

www.fairchildsemi.com

9

Electrical Characteristics (Continued)

V_DD=15V, T_A=25°C, R_T=6.8kΩ, C_T=1000pF unless noted operating specifications.

Symbol

Parameter

Conditions

Min. Typ. Max. Units

Voltage Error Amplifier

FBPFC

V_ref

Input Voltage Range⁽³⁾

0

2.45

35

6

V

Reference Voltage

Open-Loop Gain⁽³⁾

Transconductance

at T=25°C

2.50

42

2.55

A_V

dB

Gm_v

V_NONINV=V_INV, V_VEA=3.75V at T=25°C

50

70

90

µmho

µA

I_FBPFC-L

I_FBPFC-H

I_BS

Maximum Source Current V_FBPFC=2V, V_VEA=1.5V

40

50

Maximum Sink Current

Input Bias Current

V_FBPFC=3V, V_VEA=6V

-50

-40

1

µA

-1

µA

Output High Voltage on

VVEA

V_VEA-H

V_VEA-L

5.8

6.0

0.1

V

Output Low Voltage on

VVEA

0.4

0.7

Current Error Amplifier

Input Voltage Range

V_ISENSE

-1.5

V

(ISENSE Pin)⁽³⁾

Gm_I

V_OFFSET

V_IEA-H

V_IEA-L

I_L

Transconductance

Input Offset Voltage

Output High Voltage

Output Low Voltage

Source Current

V_NONINV=V_INV, V_IEA=3.75V

V_VEA=0V, IAC Open

78

-10

6.8

88

100

10

µmho

mV

V

7.4

0.1

50

8.0

0.4

V

V_ISENSE=-0.6V, V_IEA=1.5V

V_ISENSE=+0.6V, V_IEA=4.0V

35

40

µA

dB

I_H

Sink Current

Open-Loop Gain⁽³⁾

-50

50

-35

A_I

Tri-Fault Detect

V_FBPFC=V_PFC-UVPto FBPFC OPEN,

470pF from FBPFC to GND

t_{FBPFC_OPEN}Time to FBPFC Open⁽³⁾

2

4

ms

V

PFC Feedback Under-

V_PFC-UVP

0.4

0.5

0.6

Voltage Protection

Gain Modulator

I_AC

Input for AC Current⁽³⁾

GAIN Modulator⁽⁴⁾

Bandwidth⁽³⁾

Multiplier Linear Range

0

100

µA

I_AC=17.67µA, V_RMS=1.080V

7.50

9.00

7.00

4.20

1.05

10.50

V_FBPFC=2.25V, at T=25°C

I_AC=20µA, V_RMS=1.224V V_FBPFC=2.25V,

at T=25°C

6.30

3.80

0.95

0.66

7.70

4.60

1.16

0.80

I_AC=25.69µA, V_RMS=1.585V

GAIN

V

_FBPFC=2.25V, at T=25°C

I_AC=51.62µA, V_RMS=3.169V

_FBPFC=2.25V, at T=25°C

_AC=62.23µA, V_RMS=3.803V

_FBPFC=2.25V, at T=25°C

V

I

V

0.73

2

BW

I_AC=40µA

kHz

V

Output Voltage=5.7kΩ ×

I_AC=20µA, V_RMS=1.224V V_FBPFC=2.25V,

at T=25°C

V_o(gm)

0.74

0.82

0.90

(3)

(I_SENSE-I_OFFSET

)

FAN4800A/C, FAN4801/1S/2/2L • Rev. 1.0.2

www.fairchildsemi.com

10

Electrical Characteristics (Continued)

V_DD=15V, T_A=25°C, R_T=6.8kΩ, C_T=1000pF unless noted operating specifications.

Symbol

PFC ILIMIT Comparator

Peak Current Limit

Parameter

Conditions

Min. Typ. Max. Units

V_PFC-ILIMITThreshold Voltage,

Cycle-by-Cycle Limit

-1.25 -1.15 -1.05

200

V

PFC ILIMIT-Gain

ΔV_pk

I

_AC=17.67µA, V_RMS=1.08V

mV

Modulator Output

V_FBPFC=2.25V, at T=25°C

PFC Output Driver

Gate Output Clamping

V_GATE-CLAMP

Voltage

V_DD=22V

13

15

17

V

V_GATE-L

V_GATE-H

t_r

Gate Low Voltage

Gate High Voltage

Gate Rising Time

Gate Falling Time

Maximum Duty Cycle

Minimum Duty Cycle

V_DD=15V; I_O=100mA

V_DD=13V; I_O=100mA

V_DD=15V; C_L=4.7nF; O/P=2V to 9V

V_DD=15V; C_L=4.7nF; O/P=9V to 2V

V_IEA<1.2V

1.5

V

8

40

94

70

60

97

120

110

ns

%

t_f

D_PFC-MAX

D_PFC-MIN

Brown Out

V_IEA>4.5V

0

FAN4800A/C, FAN4801/1S/2

FAN4802L

1.00

0.85

1.85

1.60

750

1.05

0.90

1.90

1.65

850

1.10

0.95

1.95

1.70

950

V

V_RMS-UVP

V_RMSThreshold Low

V_RMSThreshold High

Hysteresis

FAN4800A/C, FAN4801/1S/2

FAN4802L

V

V_RMS-UVP

V

FAN4800A/C, FAN4801/1S/2

FAN4802L

mV

ΔV_RMS-UVP

650

750

850

Under-Voltage

Protection Delay Time

t_UVP

340

9.5

410

480

ms

Soft-Start

V_SS-MAX

I_SS

Maximum Voltage

Soft-Start Current

V_DD=15V

10.0

10

10.5

V

µA

PWM ILIMIT Comparator

V_PWM-ILIMITThreshold Voltage

t_PD

0.95

170

1.00

250

1.05

350

V

Delay to Output

ns

Leading-Edge Blanking

Time

t_PWM-Bnk

250

ns

Range (FAN4801/1S/2/2L)

V_RMS-LRMS AC Voltage LOW

V_RMS-H

When V_RMS=1.95V at 132V_RMS

1.90

2.40

1.90

2.75

2.40

3.30

18

1.95

2.45

1.95

2.80

2.45

3.35

20

2.00

2.50

2.00

2.85

2.50

3.40

22

V

RMS AC Voltage HIGH When V_RMS=2.45V at 150V_RMS

VEA LOW

When V_VEA=1.95V at 30% Loading,

When V_VEA=2.80V at 60% Loading

V_EA-L

V

VEA LOW (FAN4801S)

VEA HIGH

When V_VEA=2.45V at 40% Loading,

When V_VEA=3.35V at 70% Loading

V_EA-H

I_tc

V

VEA HIGH (FAN4801S)

Two-Level Current

FBPFC Two-Level Current

µA

FAN4800A/C, FAN4801/1S/2/2L • Rev. 1.0.2

www.fairchildsemi.com

11

Electrical Characteristics (Continued)

V_DD=15V, T_A=25°C, R_T=6.8kΩ, C_T=1000pF unless noted operating specifications.

Symbol

Parameter

Conditions

Min. Typ. Max. Units

PWM Output Driver

V_GATE-CLAMPGate Output Clamping Voltage V_DD=22V

13

15

17

V

V_GATE-L

V_GATE-H

t_r

Gate Low Voltage

V_DD=15V; I_O=100mA

V_DD=13V; I_O=100mA

V_DD=15V; C_L=4.7nF

1.5

Gate High Voltage

8

30

V

Gate Rising Time

60

50

120

110

50.0

1.8

ns

%

V

t_f

Gate Falling Time

30

D_PWM-MAX

V_PWM-LS

Notes:

Maximum Duty Cycle

PWM Comparator Level Shift

49.0

1.3

49.5

1.5

3. This parameter, although guaranteed by design, is not 100% production tested.

4. Gain=K × 5.3 × (V_RMS²)^-1; K=( I_SENSE－ I_OFFSET) × [I_AC× (V_EA－ 0.7V)]^-1; V_{EA (MAX.)}=5.6V.

www.fairchildsemi.com

FAN4800A/C, FAN4801/1S/2/2L • Rev. 1.0.2

12

Typical Characteristics

20.0

18.0

16.0

14.0

12.0

10.0

8.0

2.96

2.94

2.92

2.90

2.88

2.86

2.84

2.82

2.80

2.78

6.0

4.0

2.0

0.0

-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃

Figure 7. I_DD-STvs. Temperature

Figure 8.

I_DD-OPvs. Temperature

11.4

11.3

11.2

11.1

11.0

10.9

10.8

2.0

1.9

1.8

1.7

1.6

1.5

1.4

1.3

-40℃ -25℃ -10℃ 5℃

20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃

-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃

Figure 9. V_TH-ONvs. Temperature

Figure 10. ΔV_THvs. Temperature

28.04

28.02

28.00

27.98

27.96

27.94

27.92

27.90

27.88

27.86

65.0

64.9

64.8

64.7

64.6

64.5

64.4

64.3

64.2

-40

℃

-25

℃

-10

℃

5

℃

20

℃

35

℃

50

℃

65

℃

80

℃

95

℃

110

℃

125

℃

-40

℃

-25

℃

-10

℃

5

℃

20

℃

35

℃

50

℃

65

℃

80

℃

95

℃

110 125

℃ ℃

Figure 11.

V_DD-OVPvs. Temperature

Figure 12. f_{OSC-FAN4801/1S}vs. Temperature

130.0

655

650

645

640

635

630

625

620

615

129.8

129.6

129.4

129.2

129.0

128.8

128.6

128.4

-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃

Figure 13. f_{OSC-FAN4802/2L}vs. Temperature

Figure 14. t_PFCDvs. Temperature

FAN4800A/C, FAN4801/1S/2/2L • Rev. 1.0.2

www.fairchildsemi.com

13

Typical Characteristics

7.520

7.515

7.510

7.505

7.500

7.495

7.490

7.485

7.480

7.475

6

5

4

3

2

1

0

-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃

Figure 15. V_VREFvs. Temperature

Figure 16. ΔV_VREF1vs. Temperature

0.20

0.18

0.16

0.14

0.12

0.10

0.08

0.06

0.04

0.02

0.00

-0.02

21.5

21.0

20.5

20.0

19.5

19.0

18.5

18.0

-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃

Figure 18.

I_REF-MAX.vs. Temperature

Figure 17. ΔV_VREF2vs. Temperature

2.742

252.2

252.0

251.8

251.6

251.4

251.2

251.0

250.8

2.740

2.738

2.736

2.734

2.732

2.730

-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃

Figure 19. V_PFC-OVPvs. Temperature

Figure 20. ΔV_PFC-OVPvs. Temperature

2.400

1.275

1.270

1.265

1.260

1.255

1.250

1.245

1.240

2.398

2.396

2.394

2.392

2.390

2.388

-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃

Figure 21. V_RD-FBPFCvs. Temperature

Figure 22. ΔV_RD-FBPFCvs. Temperature

FAN4800A/C, FAN4801/1S/2/2L • Rev. 1.0.2

www.fairchildsemi.com

14

Typical Characteristics

74

73

72

71

2.502

2.500

2.498

2.496

2.494

2.492

2.490

2.488

-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃

-40

℃

-25

℃

-10

℃

5

℃

20

℃

35

℃

50

℃

65

℃

80

℃

95

℃

110 125

℃ ℃

Figure 23. V_REFvs. Temperature

Figure 24. Gm_Vvs. Temperature

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

94

92

90

88

86

84

82

80

78

-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃

Figure 25. V_OFFSETvs. Temperature

Figure 26. Gm_Ivs. Temperature

7.10

6.1

7.05

7.00

6.95

6.90

6.85

6.80

6.75

6.70

6.0

5.9

5.8

5.7

5.6

5.5

5.4

-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃

Figure 27. GAIN2 vs. Temperature

Figure 28. Rmul vs. Temperature

-1.1775

295

-1.1780

-1.1785

-1.1790

-1.1795

-1.1800

-1.1805

-1.1810

-1.1815

-1.1820

-1.1825

290

285

280

275

270

265

260

255

250

-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃

Figure 29. V_PFC-ILIMITvs. Temperature

Figure 30. ΔV_pkvs. Temperature

FAN4800A/C, FAN4801/1S/2/2L • Rev. 1.0.2

www.fairchildsemi.com

15

Typical Characteristics

1.010

1.009

1.008

1.007

1.006

1.005

1.004

1.003

1.002

10.1

10.0

9.9

9.8

9.7

9.6

9.5

9.4

9.3

9.2

9.1

-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃

Figure 31. V_PWM-ILIMITvs. Temperature

Figure 32. I_SSvs. Temperature

1.048

867.5

867.0

866.5

866.0

865.5

865.0

864.5

864.0

863.5

863.0

862.5

862.0

1.047

1.046

1.045

1.044

1.043

1.042

1.041

1.040

1.039

1.038

-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃

Figure 33.

V_RMS-UVPvs. Temperature

Figure 34. ΔV_RMS-UVPvs. Temperature

2.446

1.940

2.445

2.444

2.443

2.442

2.441

2.440

2.439

2.438

2.437

2.436

2.435

1.939

1.938

1.937

1.936

1.935

1.934

1.933

1.932

1.931

-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃

Figure 35. V_RMS-Lvs. Temperature

Figure 36. V_RMS-Hvs. Temperature

1.942

2.436

2.434

2.432

2.430

2.428

2.426

2.424

1.940

1.938

1.936

1.934

1.932

1.930

1.928

110 125

-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃

-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃

℃

Figure 37. V_EA-Lvs. Temperature

Figure 38. V_EA-Hvs. Temperature

FAN4800A/C, FAN4801/1S/2/2L • Rev. 1.0.2

www.fairchildsemi.com

16

Typical Characteristics

14.4

14.3

14.2

14.1

14.0

13.9

13.8

13.7

13.6

14.7

14.6

14.5

14.4

14.3

14.2

14.1

14.0

13.9

℃

110 125

℃

-40

-25

-10

5

20

35

50

65

80

95

-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃

Figure 39. V_{GATE-CLAMP-PFC}vs. Temperature

Figure 40. V_{GATE-CLAMP-PWM}vs. Temperature

96.06

96.04

96.02

96.00

95.98

95.96

95.94

95.92

95.90

95.88

49.80

49.75

49.70

49.65

49.60

49.55

49.50

110 125

-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃

-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃

℃

Figure 41. D_PFC-MAXvs. Temperature

Figure 42. D_PWM-MAXvs. Temperature

21.0

1.460

20.8

20.6

20.4

20.2

20.0

19.8

19.6

19.4

1.455

1.450

1.445

1.440

1.435

1.430

-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃

Figure 43. I_tcvs. Temperature

Figure 44. V_PWM-LSvs. Temperature

FAN4800A/C, FAN4801/1S/2/2L • Rev. 1.0.2

www.fairchildsemi.com

17

Functional Description

The FAN4800A/C and FAN4801/1S/2/2L consist of an

average current controlled, continuous boost Power

Factor Correction (PFC) front-end and a synchronized

Pulse Width Modulator (PWM) back-end. The PWM

can be used in current or voltage mode. In voltage

mode, feed forward from the PFC output bus can be

used to improve the line regulation of PWM. In either

mode, the PWM stage uses conventional trailing-edge,

duty-cycle modulation. This proprietary leading/trailing

edge modulation results in a higher usable PFC error

amplifier bandwidth and can significantly reduce the

size of the PFC DC bus capacitor.

I_AC×(V_EA− 0.7)

I_GAINMOD

=

×K

(1)

2

V_RMS

Note that the output current of the gain modulator is

limited around 159μA and the maximum output voltage

of the gain modulator is limited to 159μA

5.7K=0.906V. This 0.906V also determines the

maximum input power.

x

However, I_GAINMODcannot be measured directly from

_SENSE. I_SENSE=I_GAINMOD– I_OFFSETand I_OFFSETcan only be

I

measured when V_EAis less than 0.5V and I_GAINMODis 0A.

Typical IOFFSET is around 31μA ~ 48μA.

The synchronization of the PWM with the PFC

simplifies the PWM compensation due to the controlled

ripple on the PFC output capacitor (the PWM input

capacitor). The PWM section of the FAN4800A,

FAN4801/1S operates at the same frequency as the

PFC; and FAN4800C, FAN4802/2L operates at double

with PFC.

Selecting R_ACfor IAC Pin

The IAC pin is the input of the gain modulator and also

a current mirror input and requires current input.

Selecting a proper resistor R_ACprovides a good sine

wave current derived from the line voltage and helps

program the maximum input power and minimum input

line voltage. R_AC=V_INpeak x 56KΩ. For example, if the

minimum line voltage is 75V_AC, the R_AC=75 x 1.414 x

56KΩ=6MΩ.

In addition to power factor correction, a number of

protection features are built into this series. They

include soft-start, PFC over-voltage protection, peak

current limiting, brownout protection, duty cycle limiting,

and under-voltage lockout (UVLO).

Current Amplifier Error, IEA

Gain Modulator

The current error amplifier’s output controls the PFC

duty cycle to keep the average current through the

boost inductor a linear function of the line voltage. At

the inverting input to the current error amplifier, the

output current of the gain modulator is summed with a

current, which results in a negative voltage being

impressed upon the ISENSE pin.

The gain modulator is the heart of the PFC, as the

circuit block controls the response of the current loop to

line voltage waveform and frequency, RMS line voltage,

and PFC output voltages. There are three inputs to the

gain modulator:

1. A current representing the instantaneous input

voltage (amplitude and wave shape) to the PFC.

The rectified AC input sine wave is converted to a

proportional current via a resistor and is fed into the

gain modulator at IAC. Sampling current in this way

minimizes ground noise, required in high-power,

switching-power conversion environments. The gain

modulator responds linearly to this current.

The negative voltage on ISENSE represents the sum of

all currents flowing in the PFC circuit and is typically

derived from a current sense resistor in series with the

negative terminal of the input bridge rectifier.

The inverting input of the current error amplifier is a

virtual ground. Given this fact, and the arrangement of

the duty cycle modulator polarities internal to the PFC,

an increase in positive current from the gain modulator

causes the output stage to increase its duty cycle until

the voltage on ISENSE is adequately negative to

cancel this increased current. Similarly, if the gain

modulator’s output decreases, the output duty cycle

decreases to achieve a less negative voltage on the

ISENSE pin.

2. A voltage proportional to the long-term RMS AC line

voltage, derived from the rectified line voltage after

scaling and filtering. This signal is presented to the

gain modulator at VRMS. The output of the gain

modulator is inversely proportional to V_RMS(except at

unusually low values of VRMS, where special gain

contouring takes over to limit power dissipation of

the circuit components under brownout conditions).

3. The output of the voltage error amplifier, V_EA. The

gain modulator responds linearly to variations in this

voltage.

PFC Cycle-By-Cycle Current Limiter

As well as being a part of the current feedback loop,

the ISENSE pin is a direct input to the cycle-by-cycle

current limiter for the PFC section. If the input voltage

at this pin is less than -1.15V, the output of the PFC is

disabled until the protection flip-flop is reset by the

clock pulse at the start of the next PFC power cycle.

The output of the gain modulator is a current signal, in

the form of a full wave rectified sinusoid at twice the

line frequency. This current is applied to the virtual

ground (negative) input of the current error amplifier. In

this way, the gain modulator forms the reference for the

current error loop and ultimately controls the

instantaneous current draw of the PFC from the power

line. The general form of the output of the gain

modulator is:

FAN4800A/C, FAN4801/1S/2/2L • Rev. 1.0.2

www.fairchildsemi.com

18

TriFault Detect™

Error Amplifier Compensation

To improve power supply reliability, reduce system

component count, and simplify compliance to UL 1950

safety standards, the FAN4800A/C, FAN4801/1S/2/2L

includes TriFault Detect. This feature monitors FBPFC

for certain PFC fault conditions.

The PWM loading of the PFC can be modeled as a

negative resistor because an increase in the input

voltage to the PWM causes a decrease in the input

current.

This

response

dictates

the

proper

compensation of the two transconductance error

amplifiers. Figure 45 shows the types of compensation

networks most commonly used for the voltage and

current error amplifiers, along with their respective

return points. The current-loop compensation is

returned to V_REFto produce a soft-start characteristic

on the PFC: As the reference voltage increases from

0V, it creates a differentiated voltage on I_EA, which

prevents the PFC from immediately demanding a full

duty cycle on its boost converter. Complete design is

referred in application note AN-6078SC.

In a feedback path failure, the output of the PFC could

exceed safe operating limits. With such a failure,

FBPFC exceeds its normal operating area. Should

FBPFC go too LOW, too HIGH, or OPEN, TriFault

Detect senses the error and terminates the PFC output

drive.

TriFault detect is an entirely internal circuit. It requires

no external components to serve its protective function.

PFC Over-Voltage Protection

There is an RC filter between R_SENSEand ISENSE pin.

There are two reasons to add a filter at the ISENSE pin:

In the FAN4800A/C, FAN4801/1S/2/2L, the PFC OVP

comparator serves to protect the power circuit from

being subjected to excessive voltages if the load

changes suddenly. A resistor divider from the high-

voltage DC output of the PFC is fed to FBPFC. When

the voltage on FBPFC exceeds 2.75V, the PFC output

driver is shut down. The PWM section continues to

operate. The OVP comparator has 250mV of hysteresis

and the PFC does not restart until the voltage at

FBPFC drops below 2.50V. V_DDOVP can also serve as

a redundant PFC OVP protection. V_DDOVP threshold is

28V with 1V hysteresis.

1. Protection: During startup or inrush current conditions,

there is a large voltage across R_SENSE, which is the

sensing resistor of the PFC boost converter. It

requires the I_SENSEfilter to attenuate the energy.

2. To reduce L, the boost inductor: The I_SENSEfilter also

can reduce the boost inductor value since the I_SENSE

filter behaves like an integrator before the ISENSE pin,

which is the input of the current error amplifier, I_EA.

The I_SENSEfilter is an RC filter. The resistor value of the

I

_SENSEfilter is between 100Ω and 50Ω because I_OFFSETx

R_FILTERcan generate a negative offset voltage of IEA.

Selecting an R_FILTERequal to 50Ω keeps the offset of

the I_EAless than 3mV. Design the pole of I_SENSEfilter at

Selecting PFC R_sense

R_SENSEis the sensing resistor of the PFC boost

converter. During the steady state, line input current x

f

_PFC/6, one sixth of the PFC switching frequency, so the

boost inductor can be reduced six times without

disturbing the stability. The capacitor of the I_SENSEfilter,

R_SENSEequals I_GAINMODx 5.7KΩ.

At full load, the average V_EAneeds to around 4.5V and

ripple on the V_EAneeds to be less than 400mV. Choose

the resistance of the sensing resistor:

C_FILTER, is approximately 100nF.

V

REF

(4.5 − 0.7)× 5.7KΩ × I

2× (5.6 − 0.7)× Line Input Power

where 5.6 is V_EAmaximum output.

×Gain ×V

× 2

AC

IN

R

=

(2)

C_V2

R_V1

C_I2

R_I1

SENSE

C_V1

C_I1

PFC Output

IEA

VEA

1

16

PFC Soft-Start

PFC startup is controlled by V_EAlevel. Before FBPFC

voltage reaches 2.4V, the V_EAlevel is around 2.8V. At

90V_AC, the PFC soft-start time is 90ms.

R_F1

R_F2

Rmul

GMi

GMv

FBPFC

IAC

15

2.5V

2

4

3

I_MO

Gain

V(t)

Rmul

Modulator

VRMS

R_FILTER

ISENSE

PFC Brownout

R_SENSE

The AC UVP comparator monitors the AC input voltage.

The FAN4800A/C, FAN4801/1S/2 disables OPFC when

the VRMS is less than 1.05V and continues 500ms. The

VRMS threshold low voltage of FAN4802L is 0.9V, which

is different from the FAN4802.

C_FILTER

Figure 45.

Compensation Network Connection

for the Voltage and Current Error Amplifiers

FAN4800A/C, FAN4801/1S/2/2L • Rev. 1.0.2

www.fairchildsemi.com

19

Two-Level PFC Function

Pulse Width Modulator (PWM)

To improve the efficiency, the system can reduce PFC

switching loss at low line and light load by reducing the

PFC output voltage. The two-level PFC output of

FAN4801/1S/2/2L can be programmable.

The operation of the PWM section is straightforward,

but there are several points that should be noted.

Foremost among these is the inherent synchronization

of PWM with the PFC section of the device, from which

it also derives its basic timing. The PWM is capable of

current-mode or voltage-mode operation. In current-

mode applications, the PWM ramp (RAMP) is usually

derived directly from a current sensing resistor or

current transformer in the primary of the output stage. It

is thereby representative of the current flowing in the

converter’s output stage. I_LIMIT, which provides cycle-by-

cycle current limiting, is typically connected to RAMP in

such applications. For voltage-mode operation and

certain specialized applications, RAMP can be

connected to a separate RC timing network to generate

a voltage ramp against which FBPWM is compared.

Under these conditions, the use of voltage feed-forward

from the PFC bus can assist in line regulation accuracy

and response. As in current-mode operation, the I_LIMIT

input is used for output stage over-current protection.

No voltage error amplifier is included in the PWM

stage, as this function is generally performed on the

output side of the PWM’s isolation boundary. To

facilitate the design of opto-coupler feedback circuitry,

an offset has been built into the PWM’s RAMP input

that allows FBPWM to command a 0% duty cycle for

input voltages below typical 1.5V.

As Figure 46 shows, FAN4801/1S/2/2L detect VEA pin

and VRMS pin to determine the system operates low

line and light load or not. At the second-level PFC,

there is a current of 20µA through R_F2from FBPFC pin.

So the second-level PFC output voltage can be

calculated as.

R

+ R

F2

F1

Output ≅

×(2.5V − 20μA × R )

F2

(3)

R

F2

For example, if the second-level PFC output voltage is

expected as 300V and normal voltage is 387V,

according to the equation, R_F2is 28kΩ R_F1is 4.3MΩ.

The programmable range of second level PFC output

voltage is 340V ~ 300V.

VEA

PFC Output

16

V_DD

R_F1

20µA

gmv

FBPFC

15

2.5V

PWM Cycle-By-Cycle Current Limiter

R_F2

The ILIMIT pin is a direct input to the cycle-by-cycle

current limiter for the PWM section. Should the input

voltage at this pin ever exceed 1V, the output flip-flop is

reset by the clock pulse at the start of the next PWM

power cycle. When the I_LIMITtriggers the cycle-by-cycle

bi-cycle current, it limits the PWM duty cycle mode and

the power dissipation is reduced during the dead-short

condition.

Range

4

VRMS

Figure 46.

Two-Level PFC Scheme

Oscillator (R_T/C_T)

The oscillator frequency is determined by the values of

R_Tand C_T, which determine the ramp and off-time of

the oscillator output clock:

V_INOK Comparator

The V_INOK comparator monitors the DC output of the

PFC and inhibits the PWM if the voltage on FBPFC is

less than its nominal 2.4V. Once the voltage reaches

2.4V, which corresponds to the PFC output capacitor

being charged to its rated boost voltage, the soft-start

begins.

1

f_{RT /CT}

=

(4)

t_{RT /CT}+ t_DEAD

The dead time of the oscillator is derived from the

following equation:

PWM Soft-Start (SS)

⎛

⎜

⎝

⎞

⎟

⎠

V

−1

REF

− 3.8

t

= C × R × In

T T

(5)

RT /CT

PWM startup is controlled by selection of the external

capacitor at soft-start. A current source of 10µA

supplies the charging current for the capacitor and

startup of the PWM begins at 1.5V.

V

REF

at V_REF=7.5V and t_RT/CT=C_Tx R_Tx 0.56.

The dead time of the oscillator is determined using:

2.8V

t_DEAD

=

×C_T= 360×C_T

(6)

7.78mA

The dead time is so small (t_RT/CT>>t_DEAD) that the

operating frequency can typically be approximated by:

1

f_{RT /CT}

=

(7)

t_{RT /CT}

FAN4800A/C, FAN4801/1S/2/2L • Rev. 1.0.2

www.fairchildsemi.com

20

PWM Control (RAMP)

Leading/Trailing Modulation

When the PWM section is used in current mode, RAMP

is generally used as the sampling point for a voltage,

representing the current in the primary of the PWM’s

output transformer. The voltage is derived either from a

current sensing resistor or a current transformer. In

voltage mode, RAMP is the input for a ramp voltage

generated by a second set of timing components

(R_RAMP, C_RAMP) that have a minimum value of 0V and a

peak value of approximately 6V. In voltage mode, feed

forward from the PFC output bus is an excellent way to

derive the timing ramp for the PWM stage.

Conventional PWM techniques employ trailing-edge

modulation, in which the switch turns on right after the

trailing edge of the system clock. The error amplifier

output is then compared with the modulating ramp up.

The effective duty cycle of the trailing edge modulation

is determined during the on-time of the switch.

In the case of leading-edge modulation, the switch is

turned off exactly at the leading edge of the system

clock. When the modulating ramp reaches the level of

the error amplifier output voltage, the switch is turned

on. The effective duty-cycle of the leading-edge

modulation is determined during off-time of the switch.

Generating V_DD

After turning on the FAN4800A/C, FAN4801/1S/2/2L at

11V, the operating voltage can vary from 9.3V to 28V.

The threshold voltage of the V_DDOVP comparator is

28V and its hysteresis is 1V. When V_DDreaches 28V,

OPFC is LOW, and the PWM section is not disturbed.

There are two ways to generate V_DD: use auxiliary

power supply around 15V or use bootstrap winding to

self-bias the FAN4800A/C, FAN4801/1S/2/2L system.

The bootstrap winding can be taped from the PFC

boost choke or the transformer of the DC-to-DC stage.

FAN4800A/C, FAN4801/1S/2/2L • Rev. 1.0.2

www.fairchildsemi.com

21

Physical Dimensions

A

19.68

18.66

9

16

6.60

6.09

1

8

(0.40)

TOP VIEW

0.38 MIN

5.33 MAX

8.13

7.62

3.42

3.17

3.81

2.92

15

0

0.35

0.20

2.54

0.58

0.35

A

1.78

1.14

8.69

17.78

SIDE VIEW

NOTES: UNLESS OTHERWISE SPECIFIED

A

THIS PACKAGE CONFORMS TO

JEDEC MS-001 VARIATION BB

B) ALL DIMENSIONS ARE IN MILLIMETERS.

C) DIMENSIONS ARE EXCLUSIVE OF BURRS,

MOLD FLASH, AND TIE BAR PROTRUSIONS

D) CONFORMS TO ASME Y14.5M-1994

E) DRAWING FILE NAME: N16EREV1

Figure 47.

16-Pin Dual In-Line Package (DIP)

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify

or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically

the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

FAN4800A/C, FAN4801/1S/2/2L • Rev. 1.0.2

www.fairchildsemi.com

22

Physical Dimensions (Continued)

Figure 48.

16-Pin Small Outline Package (SOIC)

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify

or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically

the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

FAN4800A/C, FAN4801/1S/2/2L • Rev. 1.0.2

www.fairchildsemi.com

23

FAN4800A/C, FAN4801/1S/2/2L • Rev. 1.0.2

www.fairchildsemi.com

24


型号：	FAN4800C
厂家：	FAIRCHILD SEMICONDUCTOR
描述：	PFC/PWM Controller Combination PFC / PWM控制器组合功率因数校正控制器
文件：	总24页 (文件大小：641K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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