FAN5099_技术文档

Decemeber 2006

FAN5099 Wide Frequency Synchronous Buck

PWM & LDO Controller

Features

Description

■ General Purpose PWM Regulator and LDO Controller

■ Input Voltage Range: 3V to 24V

■ Output Voltage Range: 0.8V to 15V

■ V_CC

The FAN5099 combines a high-efficiency pulse-width

modulated (PWM) controller and an LDO (Low DropOut)

linear regulator controller. The PWM controller is

designed to operate over a wide frequency range (50kHz

to 600kHz) to accommodate a variety of applications.

Synchronous rectification provides high efficiency over a

wide range of load currents. Efficiency is further

enhanced by using the low-side MOSFET’s R_DS(ON)to

sense current. In addition, the capability to operate at low

switching frequencies provides opportunities to boost

power supply efficiency by reducing switching losses and

gain cost savings using low-cost materials, such as pow-

dered iron cores, on the output inductor.

– 5V

– Shunt Regulator for 12V Operation

■ Support for Ceramic Cap on PWM Output

■ Programmable Current Limit for PWM Output

■ Wide Programmable Switching Frequency Range

(50kHz to 600kHz)

■ R_DS(ON)Current Sensing

■ Internal Synchronous Boot Diode

■ Soft-Start for both PWM and LDO

■ Multi-Fault Protection with Optional Auto-restart

■ 16-Pin TSSOP Package

Both the linear and PWM regulator soft-start are con-

trolled by a single external capacitor, to limit in rush cur-

rent from the supply when the regulators are first

enabled. Current limit for PWM is also programmable.

Applications

■ High-Efficiency (80+) Computer Power Supplies

■ PC/Server Motherboard Peripherals

The FAN5099’s ability to handle wide input voltage

ranges makes this controller suitable for power solutions

in a wide range of applications involving conversion input

voltages from Silver box, battery, and adapters. The

PWM regulator employs a summing-current-mode con-

trol with external compensation to achieve fast load tran-

sient response and provide system design optimization.

– V_CC_MCH (1.5V), V_DDQ(1.5V) and

V_{TT_GTL}(1.25V)

■ Power Supply for

– FPGA, DSP, Embedded Controllers, Graphic Card

Processor, and Communication Processors

■ High-Power DC-to-DC Converters

FAN5099 is offered in both industrial temperature grade

(-40°C to +85°C) as well as commercial temperature

grade (-10°C to +85°C).

Related Application Notes

■ AN-6020 FAN5099 Component Calculation and

Simulation Tools

■ AN-6005 Synchronous Buck MOSFET Loss

Calculations with Excel Model

Ordering Information

Part Number Operating Temp. Range Pb-Free

Package

Packing Method

Tape and Reel

Qty/Reel

2500

FAN5099MTCX

FAN5099EMTCX

FAN5099MX

-10°C to +85°C

-40°C to +85°C

-10°C to +85°C

-40°C to +85°C

Yes

16-Lead TSSOP

16-Lead SOIC

2500

FAN5099EMX

2500

Note: Contact Fairchild sales for availability of other package options.

FAN5099 Rev. 1.1.3

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Typical Application

Figure 1. Typical Application Diagram

FAN5099 Rev. 1.1.3

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2

Pin Assignment

Figure 2. Pin Assignment

Pin Description

Pin No. Pin Name

Pin Description

LDO Feedback. This node is regulated to V_REF

1

2

FBLDO

R(T)

.

Oscillator Set Resistor. This pin provides oscillator switching frequency adjustment. By plac-

ing a resistor (RT) from this pin to GND, the nominal 50kHz switching frequency is increased.

3

4

ILIM

SS

Current Limit. A resistor from this pin to GND sets the current limit.

Soft-Start. A capacitor from this pin to GND programs the slew rate of the converter and the

LDO during initialization. It also sets the time by which the converter delays when restarting

after a fault occurs. SS has to reach 1.2V before fault shutdown feature is enabled. The LDO

is enabled when SS reaches 2.2V.

5

6

COMP

FB

COMP. The output of the error amplifier drives this pin.

Feedback. This pin is the inverting input of the internal error amplifier. Use this pin, in combi-

nation with the COMP pin, to compensate the feedback loop of the converter.

7

EN

Enable. Enables operation when pulled to logic high. Toggling EN resets the regulator after a

latched fault condition. This is a CMOS input whose state is indeterminate if left open and

needs to be properly biased at all times.

8

9

AGND

SW

Analog Ground. The signal ground for the IC. All internal control voltages are referred to this

pin. Tie this pin to the ground island/plane through the lowest impedance connection available.

Switching Node. Return for the high-side MOSFET driver and a current sense input. Connect

to source of high-side MOSFET and drain of low-side MOSFET.

10

HDRV

High-Side Gate Drive Output. Connect to the gate of the high-side power MOSFETs. This

pin is also monitored by the adaptive shoot-through protection circuitry to determine when the

high-side MOSFET is turned off.

11

12

13

BOOT

PGND

LDRV

Bootstrap Supply Input. Provides a boosted voltage to the high-side MOSFET driver.

Connect to bootstrap capacitor as shown in Figure 1.

Power Ground. The return for the low-side MOSFET driver. Connect to source of low-side

MOSFET.

Low-Side Gate Drive Output. Connect to the gate of the low-side power MOSFETs. This pin

is also monitored by the adaptive shoot-through protection circuitry to determine when the

lower MOSFET is turned off.

14

15

R(RAMP) Ramp Resistor. A resistor from this pin to VIN sets the ramp amplitude and provides voltage

feed-forward.

VCC

V_CC. Provides bias power to the IC and the drive voltage for LDRV. Bypass with a ceramic

capacitor as close to this pin as possible. This pin has a shunt regulator which draws current

when the input voltage is above 5.6V.

16

GLDO

Gate Drive for the LDO. Turned off (low) until SS is greater than 2.2V.

FAN5099 Rev. 1.1.3

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3

Absolute Maximum Ratings

The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The

device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables

are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table defines the

(1)

conditions for actual device operation.

Parameter

Min.

Max.

6.0

Unit

V

V_CCto PGND

BOOT to PGND

SW to PGND

33.0

V

Continuous

-0.5

-3.0

33.0

V

Transient (t < 50ns, f < 500kHz)

33.0

V

HDRV (V_BOOT– V_SW

)

6.0

V

LDRV

-0.5

-0.3

6.0

V

All Other Pins

V_CC+ 0.3

150

V

Maximum Shunt Current for V_CC

mA

kV

Electrostatic Discharge (ESD) Protection

Level⁽²⁾

HBM

CDM

3.5

1.8

Notes:

1. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This

is a stress rating only; functional operation of the device at these or any conditions above those indicated in the

operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended

periods may affect device reliability. Absolute maximum ratings apply individually only, not in combination. Unless

otherwise specified, all other voltages are referenced to AGND.

2. Using Mil Std. 883E, method 3015.7 (Human Body Model) and EIA/JESD22C101-A (Charge Device Model).

Thermal Information

Symbols

T_STG

Parameter

Min.

Typ.

Max.

150

300

215

220

715

Unit

°C

Storage Temperature

-65

T_L

Lead Soldering Temperature, 10 Seconds

Vapor Phase, 60 Seconds

°C

Infrared, 15 Seconds

°C

P_D

θ_JC

θ_JA

Power Dissipation, T_A= 25°C

mW

°C/W

Thermal Resistance – Junction-to-Case

Thermal Resistance – Junction-to-Ambient⁽³⁾

37

100

3. Junction-to-ambient thermal resistance, θ_JA, is a strong function of PCB material, board thickness, thickness and

number of copper planes, number of vias used, diameter of vias used, available copper surface, and attached heat

sink characteristics.

Recommended Operating Conditions

Symbols

Parameter

Supply Voltage

Conditions

V_CCto GND

Commercial

Industrial

Min.

4.5

Typ.

Max.

5.5

Unit

V

V_CC

5.0

-10

85

°C

T_A

T_J

Ambient Temperature

Junction Temperature

-40

85

°C

125

°C

FAN5099 Rev. 1.1.3

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4

Electrical Characteristics

Unless otherwise noted, V_CC= 5V, T_A= 25°C, using the circuit in Figure 1. The ‘•’ denotes that the specifications apply

to the full ambient operating temperature range.^(4,5)

Symbol

Parameter

Conditions

Min.

Typ.

Max. Unit

Supply Current

•

I_VCC

V_CCCurrent (Quiescent)

HDRV, LDRV Open

EN = 0V, V_CC= 5.5V

2.6

3.2

200

10

3.8

400

15

mA

μA

I_VCC(SD)V_CCCurrent (Shutdown)

EN = 5V, V_CC= 5.0V,

Q_FET= 20nC, F_SW= 200kHz

mA

I_VCC(OP)V_CCCurrent (Operating)

V_SHUNTV_CCVoltage⁽⁶⁾

Sinking 1mA to 100mA at V Pin

5.4

5.9

V

CC

Under-Voltage Lockout (UVLO)

UVLO(H) Rising V_CCUVLO Threshold

UVLO(L) Falling V_CCUVLO Threshold

•

4.00

3.60

4.25

3.75

0.5

4.50

4.00

V

V_CCUVLO Threshold

Hysteresis

Soft-Start

I_SS

Current

10

2.2

1.2

μA

V

V_LDOSTARTLDO Start Threshold

V_SSOK

PWM Protection Enable

Threshold

V

Oscillator

R(T) = 25.5KΩ ± 1%

R(T) = 199KΩ ± 1%

R(T) = Open

240

60

300

80

360

100

kHz

V

F_OSC

Frequency

50

Operating Frequency Range

40

600

ΔV_RAMPRamp Amplitude

R(RAMP) = 330KΩ

0.4

(Peak-to-Peak)

Minimum On Time

Reference

f = 200kHz

200

ns

•

Reference Voltage

(Measured at FB Pin)

T_A= 0°C to 70°C

790

788

800

160

810

812

mV

V_REF

T_A= -40°C to 85°C

Current Amplifier Reference

(at SW node)

Error Amplifier

DC Gain

80

25

8

dB

MHz

V/μS

V

GBWP

S/R

Gain-BW Product

Slew Rate

10pF across COMP to GND

No Load

•

Output Voltage Swing

FB Pin Source Current

0.5

4.0

I_FB

Gate Drive

R_HUP

μA

•

HDRV Pull-up Resistor

HDRV Pull-down Resistor

LDRV Pull-up Resistor

LDRV Pull-down Resistor

Sourcing

Sinking

1.8

1.2

3.0

2.0

Ω

R_HDN

R_LUP

Sourcing

Sinking

R_LDN

FAN5099 Rev. 1.1.3

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5

Electrical Characteristics (Continued)

Unless otherwise noted, V_CC= 5V, T_A= 25°C, using the circuit in Figure 1. The ‘•’ denotes that the specifications apply

to the full ambient operating temperature range.^{(4, 5)}

Symbol

Parameter

Conditions

Min.

Typ.

Max.

Unit

Protection/Disable

I_LIM

ILIMIT Source Current

9

10

11

μA

mA

%

I_SWPDSW Pull-down Current

SW = 1V, EN = 0V

As % of set point;

2μS noise filter

65

75

80

•

V_UV

V_OV

Under-Voltage Threshold

Over-Voltage Threshold

As % of set point;

2μS noise filter

110

115

120

%

Supply Current

TSD

Thermal Shutdown

160

°C

V

•

Enable Condition

Disable Condition

V_CC= 5V

2.0

V_EN

Enable Threshold Voltage

Enable Source Current

0.8

V

50

10

μA

V_CC= 5V and fault conditions

(overload, short-circuit,

Enable Sink Current

over-voltage, under-voltage)

Low Drop-Out (LDO)⁽⁷⁾

•

V_LDOREFReference Voltage

T_A= 0°C to 70°C

T_A= -40°C to 85°C

0A ≤ I_LOAD≤ 5A

775

770

1.17

800

1.20

825

830

1.23

0.3

mV

V

(measured at FBLDO pin)

Regulation

V_{LDO_DO}Drop-out Voltage

I_LOAD≤ 5A and R_DS-ON< 50mΩ

V_CC= 4.75V

V

•

4.5

V

External Gate Drive

V_CC= 5.6V

5.3

V

Gate Drive Source Current

Gate Drive Sink Current

1.2

mA

μA

400

Notes:

4. All limits at operating temperature extremes are guaranteed by design, characterization, and statistical quality control.

5. AC specifications guaranteed by design/characterization (not production tested).

6. For a case when V_CCis higher than the typical 5V V_CC,voltage observed at V_CCpin when the internal shunt regulator

is sinking current to keep voltage on V_CCpin constant.

7. Test Conditions: V_{LDO_IN}= 1.5V and V_{LDO_OUT}= 1.2V.

FAN5099 Rev. 1.1.3

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6

Typical Performance Characteristics

V_IN=12V, V_dd=5V, V_OUT=1.5V, V_ldo=1.2V, I_load=5A, I_ldo=2A, F_osc= 300kHz, unless otherwise noted.

Ch1: HDRV; Ch2: LDRV. Dead times: 62ns, 32ns

Ch1: V

; Ch3: I , 5A/div

L

OUT

Figure 3. Dead Time Waveform

Figure 6. PWM Load Transient (0 to 15A)

Ch1: V

; Ch3: I

, 1A/div

OUT_LDO

LDO

Ch1: V

; Ch3: I , 2.5A/div

L

OUT

Figure 4. PWM Load Transient (0 to 5A)

Figure 7. LDO Load Transient (0 to 2A)

Ch1: V

; Ch3: I

, 2.5A/div

OUT_LDO

LDO

Ch1: V

; Ch3: I , 5A/div

L

OUT

Figure 5. PWM Load Transient (0 to 10A)

Figure 8. LDO Load Transient (0 to 5A)

FAN5099 Rev. 1.1.3

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7

Typical Performance Characteristics (Continued)

V_IN=12V, V_dd=5V, V_OUT=1.5V, V_ldo=1.2V, I_load=5A, I_ldo=2A, F_osc= 300kHz, unless otherwise noted.

Ch1: V

; Ch2: SS; Ch3: EN

Ch1: V

; Ch2:V

; Ch3: SS

OUT_LDO

OUT

Figure 9. PWM/LDO Power Up

Figure 12. Enable On (I_PWM= 5A)

Ch1: V

; Ch2: V

; Ch3: SS

OUT_LDO

Ch1: V

; Ch2: SS; Ch3: EN

OUT

Figure 10. PWM/LDO Power Down

Figure 13. Enable Off (I_PWM= 5A)

Ch1: EN; Ch2: SS; Ch3: V

; Ch4: I , 25A/div

L

OUT

Figure 11. Auto Restart

Figure 14. PWM Line Regulation

FAN5099 Rev. 1.1.3

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8

Typical Performance Characteristics (Continued)

V_IN=12V, V_dd=5V, V_OUT=1.5V, V_ldo=1.2V, I_load=5A, I_ldo=2A, F_osc= 300kHz, unless otherwise noted.

Figure 18. R_Tvs. Frequency

Figure 15. LDO Load Regulation

Figure 19. 1.5V PWM Efficiency

Figure 16. PWM Load Regulation

Figure 20. Efficiency Comparison at V_IN=12V

Figure 17. LDO Load Regulation

FAN5099 Rev. 1.1.3

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9

Block Diagram

C_BOOT

InternalVcc 5.6V Max.

BOOT

Vcc

Internal

Boot Diode

Shunt Reg

10μA

R_ILIM

ILIM

Current Limit

Comparator

V_IN

PWM

COMP

FB

Error

Amplifier

PWM

Comparator

R Q

HDRV

S

Adaptive

GateDrive

Circuit

Vref

Vcc

L_O

Vout

C_O

10μA

OSC

SW

SS

Current

Sense

Amplifier

LDRV

V_IN

Summing

Amplifier

R_RAMP

Ramp

Generator

R(RAMP)

EN

PGND

Enable

Figure 21. Block Diagram

Selection (IC)

R

Detailed Operation Description

VCC

The selection of R_VCCis dependent on:

FAN5099 combines a high-efficiency, fixed-frequency

PWM controller designed for single-phase synchronous

buck Point-Of-Load converters with an integrated LDO

controller to support GTL-type loads. This controller is

ideally suited to deliver low-voltage, high-current power

supplies needed in desktop computers, notebooks,

workstations, and servers. The controller comes with an

integrated boot diode which helps reduce component

cost and increase space savings. With this controller, the

input to the power supply can be varied from 3V to 24V

and the output voltage can be set to regulate at 0.8V to

15V on the switcher output. The LDO output can be con-

figured to regulate between 0.8V to 3V and the input to

the LDO can be from 1.5V to 5V, respectively. An internal

shunt regulator at the V_CCpin facilitates the controller

operation from either a 5V or 12V power source.

■ Variation of the 12V supply

■ Sum of gate charges of top and bottom FETs (Q_FET

■ Switching frequency (F_SW

)

■ Shunt regulator minimum current (1mA)

■ Quiescent Current of the IC (I_Q)

Calculate R_VCCbased on the minimum input voltage for

the V_CC

:

VIN_MIN– 5.6

R_VCC= -----------------------------------------------------------------------------------------

(I_Q+ 1 • 10^–3+ Q_FET• F_SW• 1.2)

For a typical example, where:

V_IN= 11.5V, I_Q= 3mA, Q_FET= 30nC, F_SW= 300kHz,

R_VCCis calculated to be 398.65Ω.

MIN

V

Bias Supply

CC

FAN5099 can be configured to operate from 5V or 12V

for V . When 5V supply is used for V , no resistor is

PWM Section

CC

required to be connected between the supply and the

The FAN5099’s PWM controller combines the conven-

tional voltage mode control and current sensing through

lower MOSFET R_{DS_ON}to generate the PWM signals.

This method of current sensing is loss-less and cost

effective. For more accurate current sense requirements,

an optional external resistor can be connected with the

bottom MOSFET in series.

V

. When the 12V supply is used, a resistor R

is

CC

VCC

connected between the 12V supply and the V

as

CC,

shown in Figure 1. The internal shunt regulator at the V

CC

pin is capable of sinking 150mA of current to ensure the

controller’s internal V is maintained at 5.6V maximum.

CC

Choose a resistor such that:

■ It is rated to handle the power dissipation.

■ Current sunk within the controller is minimized to

prevent IC temperature rise.

FAN5099 Rev. 1.1.3

www.fairchildsemi.com

10

tively changes the slope of the internal ramp, minimizing

the variation of the PWM modulator gain when input volt-

age varies. The R_RAMPeffect on the current limit is

explained in later sections. The R_RAMPvalue can be

approximated using the following equation:

PWM Operation

Refer to Figure 21 for the PWM control mechanism. The

FAN5099 uses the summing mode method of control to

generate the PWM pulses. The amplified output of the

current-sense amplifier is summed with an internally

generated ramp and the combined signal is amplified

and compared with the output of the error amplifier to get

the pulse width to drive the high-side MOSFET. The

sensed current from the previous cycle is used to modu-

late the output of the summing block. The output of the

summing block is also compared against the voltage

threshold set by the R_LIMresistor to limit the inductor cur-

rent on a cycle-by-cycle basis. The controller facilitates

external compensation for enhanced flexibility.

V

_{(IN, nom)}– 1.8

R_RAMP= -------------------------------------------KΩ

6.3×10^–8× F_OSC

(EQ. 3)

where F_OSCis in Hz. For example, for F_OSC= 80kHz and

V_IN= 12V, R_RAMP= 2MΩ.

Gate Drive Section

The adaptive gate control logic translates the internal

PWM control signal into the MOSFET gate drive signals

and provides necessary amplification, level shifting, and

shoot-through protection. It also has functions that help

optimize the IC performance over a wide range of oper-

ating conditions. Since the MOSFET switching time can

vary dramatically from device to device and with the

input voltage, the gate control logic provides adaptive

dead time by monitoring the gate-to-source voltages of

both upper and lower MOSFETs. The lower MOSFET

drive is not turned on until the gate-to-source voltage of

the upper MOSFET has decreased to less than approxi-

mately 1V. Similarly, the upper MOSFET is not turned on

until the gate-to-source voltage of the lower MOSFET

has decreased to less than approximately 1V. This

allows a wide variety of upper and lower MOSFETs to be

used without a concern for simultaneous conduction, or

shoot-through.

Initialization

When the PWM is disabled, the SW node is connected

to GND through an internal 500Ω MOSFET to slowly dis-

charge the output. As long as the PWM controller is

enabled, this internal MOSFET remains OFF.

Soft-Start (PWM and LDO)

When V_CCexceeds the UVLO threshold and EN is high,

the circuit releases SS and enables the PWM regulator.

The capacitor connected to the SS pin and GND is

charged by a 10µA internal current source, causing the

voltage on the capacitor to rise. When this voltage

exceeds 1.2V, all protection circuits are enabled. When

this voltage exceeds 2.2V, the LDO output is enabled.

The input to the error amplifier at the non-inverting pin is

clamped by the voltage on the SS pin until it crosses the

reference voltage.

A low impedance path between the driver pin and the

MOSFET gate is recommended for the adaptive dead-

time circuit to work properly. Any delay along this path

reduces the delay generated by the adaptive dead-time

circuit, thereby increasing the chances for shoot-through.

The time it takes the PWM output to reach regulation

(T_Rise) is calculated using the following equation:

T_RISE= 8 × 10^–2× C_SS(C_SSis in μf)

(EQ. 1)

Protection

Oscillator Clock Frequency (PWM)

In the FAN5099, the converter is protected against over-

load, short-circuit, over-voltage, and under-voltage con-

ditions. All of these extreme conditions generate an

internal “fault latch” which shuts down the converter. For

all fault conditions, both the high-side and the low-side

drives are off, except in the case of OVP, where the low-

side MOSFET is turned on until the voltage on the FB pin

goes below 0.4V. The fault latch can be reset either by

toggling the EN pin or recycling V_CCto the chip.

The clock frequency on the oscillator is set using an

external resistor, connected between R(T) pin and

ground. The frequency follows the graph, as shown in

Figure 18. The minimum clock frequency is 50kHz,

which is when R(T) pin is left open. Select the value of

R(T) as shown in the equation below. This equation is

valid for all F_OSC> 50kHz:

4 × 10⁷

R(t) = -----------------------------------------------------------------kΩ

6.25 × F_OSC– 2.99 × 10⁵

(EQ. 2)

Over-Current Limit (PWM)

where, F_OSCis in Hz.

The PWM converter is protected against overloading

through a cycle-by-cycle current limit set by selecting

R_ILIMresistor. An internal 10µA current source sets the

threshold voltage for the output of the summing amplifier.

When the summing amplifier output exceeds this thresh-

old level, the current limit comparator trips and the PWM

starts skipping pulses. If the current limit tripping occurs

for 16 continuous clock cycles, a fault latch is set and the

For example, for F_OSC= 80kHz, R(t) = 199kΩ.

R

Selection and Feedforward Operation

RAMP

The FAN5099 provides for input voltage feedforward

compensation through R_RAMP. The value of R_RAMPeffec-

FAN5099 Rev. 1.1.3

www.fairchildsemi.com

11

controller shuts down the converter. This shutdown fea-

ture is disabled during the start-up until the voltage on

the SS capacitor crosses 1.2V.

EN Pin

Pull to GND

V_CC

PWM/Restart

OFF

No restart after fault

To achieve current limit, the FAN5099 monitors the

inductor current during the OFF time by monitoring and

holding the voltage across the lower MOSFET. The volt-

age across the lower MOSFET is sensed between the

PGND and the SW pins.

Cap to GND

Restart after

t_DELAY(Sec.) = 0.85 x C

where C is in μF

The fault latch can also be reset by recycling the V_CCto

the controller.

The output of the summing amplifier is a function of the

inductor current, R_{DS_ON}of the bottom FET and the gain

of the current sense amplifier. With the R_{DS_ON}method

of current sensing, the current limit can vary widely from

unit to unit. R_{DS_ON}not only varies from unit to unit, but

also has a typical junction temperature coefficient of

about 0.4%/°C (consult the MOSFET datasheet for

actual values). The set point of the actual current limit

decreases in proportion to increase in MOSFET die tem-

perature. A factor of 1.6 in the current limit set point typi-

cally compensates for all MOSFET R_{DS_ON}variations,

assuming the MOSFET's heat sinking keeps its operat-

ing die temperature below 125°C.

Under Voltage Protection (PWM)

The PWM converter output is monitored constantly for

under voltage at the FB pin. If the voltage on the FB pin

stays lower than 75% of internal V_REFfor 16 clock

cycles, the fault latch is set and the converter shuts

down. This shutdown feature is disabled during startup

until the voltage on the SS capacitor reaches 1.2V.

Over-Voltage Protection (PWM)

The PWM converter output voltage is monitored con-

stantly at the FB pin for over voltage. If the voltage on the

FB pin stays higher than 115% of internal V_REFfor two-

clock cycles, the controller turns OFF the upper MOS-

FET and turns ON the lower MOSFET. This crowbar

action stops when the voltage on the FB pin comes down

to 0.4V to prevent the output voltage from becoming neg-

ative. This over-voltage protection (OVP) feature is

active when the voltage on the EN pin becomes HIGH.

For more accurate current limit setting, use resistor

sensing. In a resistor sensing scheme, an appropriate

current sense resistor is connected between the source

terminal of the bottom MOSFET and PGND.

Set the current limit by choosing R_ILIMas follows:

K1 • I_MAX• R_DSON• 10³

128 + -----------------------------------------------------------------

1.43

1.8

1 -------- • ---------------------------------------------------

Vout • 33.32 • 10¹¹

Turning ON the low-side MOSFETs on an OVP condition

pulls down the output, resulting in a reverse current,

which starts to build up in the inductor. If the output over-

voltage is due to failure of the high-side MOSFET, this

crowbar action pulls down the input supply or blows its

fuse, protecting the system, which is very critical.

R_ILIM

=

( - )

+

(

)

Vin

F_SW• R_RAMP

(EQ. 4)

where:

R_ILIMis in KΩ.

I_MAXis the maximum load current.

During soft-start, if the output overshoots beyond 115%

of V_REF, the output voltage is brought down by the low-

side MOSFET until the voltage on the FB pin goes below

0.4V. The fault latch is NOT set until the voltage on the

SS pin reaches 1.2V. Once the fault latch is set, the con-

verter shuts down.

K1 is a constant to accommodate for the variation of

MOSFET R_DS(ON)(typically 1.6).

With K₁= 1.6, I_MAX= 20A, R_DS(ON)= 7mΩ, V_IN= 24V,

V_OUT= 1.5V, F_SW= 300 kHz, R_RAMP= 400 KΩ, R_ILIM

calculates to be 323.17KΩ.

ILIM

115% Vref

UV

Fault

Latch

S

R

OV

Q

V_SS>1.2V

Auto Restart (PWM)

Delay

2 Clks

EN

FB

The FAN5099 supports two modes of response when the

internal fault latch is set. The user can configure it to

keep the power supply latched in the OFF state OR in

S

Q

LS Drive

R

0.4V

the auto restart mode. When the EN pin is tied to V_CC

,

Figure 22. Over-Voltage Protection

Thermal Fault Protection

the power supply is latched OFF. When the EN pin is ter-

minated with a 100nF to GND, the power supply is in

auto restart mode. The table below describes the rela-

tionship between PWM restart and setting on EN pin. Do

not leave the EN pin open without any capacitor.

The FAN5099 features thermal protection where the IC

temperature is monitored. When the IC junction temper-

ature exceeds +160°C, the controller shuts down and

when the junction temperature gets down to +125°C, the

converter restarts.

FAN5099 Rev. 1.1.3

www.fairchildsemi.com

12

LDO Section

The LDO controller is designed to provide ultra low volt-

ages, as low as 0.8V for GTL-type loads. The regulating

loop employs a very fast response feedback loop and

small capacitors can be used to keep track of the chang-

ing output voltage during transients. For stable opera-

tion, the minimum capacitance on the output needs to be

100µF and the typical ESR needs to be around 100mΩ.

operate at the boundary of continuous and discontinuous

conduction modes.

Setting the Output Voltage (PWM)

The internal reference for the PWM controller is at 0.8V.

The output voltage of the PWM regulator can be set in

the range of 0.8V to 90% of its power input by an exter-

nal resistor divider. The output is divided down by an

external voltage divider to the FB pin (for example, R1

and R_BIASas in Figure 25). The output voltage is given

by the following equation:

The maximum voltage at the gate drive for the MOSFET

can reach close to 0.5V below the V_CCof the controller.

For example, for a 1.2V output, the minimum enhance-

ment voltage required with 4.75V on V_CCis 3.05V

(4.75V-0.5V-1.2V = 3.05V). The dropout voltage for the

LDO is dependent on the load current and the MOSFET

chosen. It is recommended to use low enhancement

voltage MOSFETs for the LDO. In an application where

LDO is not needed, pull up the FBLDO pin (Pin 1) higher

than 1V to disable the LDO.

R1

R_BIAS

⎛

⎞

⎠

V_OUT= 0.8V × 1 + ---------------

⎝

(EQ. 5)

To minimize noise pickup on this node, keep the resistor

to GND (R_BIAS) below 10KΩ.

Inductor Selection (PWM)

The soft-start on the LDO output (ramp) is controlled by

the capacitor on the SS pin to GND. The LDO output is

enabled only when the voltage on the SS pin reaches

2.2V. Refer to Figure 9 for startup waveform.

When the ripple current, switching frequency of the con-

verter, and the input-output voltages are established,

select the inductor using the following equation:

2

V_OUT

⎛

⎝

⎞

⎠

V

_OUT– --------------

V_IN

Design Section

L_MIN= -------------------------------------------

I_Ripple× F_SW

(EQ. 6)

General Design Guidelines

where I_Rippleis the ripple current.

Establishing the input voltage range and the maximum

current loading on the converter before choosing the

switching frequency and the inductor ripple current is

highly recommended. There are design tradeoffs choos-

ing optimum switching frequency and ripple current.

This number typically varies between 20% to 50% of the

maximum steady-state load on the converter.

When selecting an inductor from the vendors, select the

inductance value which is close to the value calculated at

the rated current (including half the ripple current).

The input voltage range should accommodate the worst-

case input voltage with which the converter may ever

operate. This voltage needs to account for the cable drop

encountered from the source to the converter. Typically,

the converter efficiency tends to be higher at lower input

voltage conditions.

Input Capacitor Selection (PWM)

The input capacitors must have an adequate RMS cur-

rent rating to withstand the temperature rise caused by

the internal power dissipation. The combined RMS cur-

rent rating for the input capacitor should be greater than

the value calculated using the following equation:

When selecting maximum loading conditions, consider

the transient and steady-state (continuous) loading sep-

arately. The transient loading affects the selection of the

inductor and the output capacitors. Steady-state loading

affects the selection of MOSFETs, input capacitors, and

other critical heat-generating components.

2

V_OUTV_OUT

⎛

⎜

⎝

⎞

⎟

⎠

⎛

⎞

⎠

I_INPUT(RMS)= I_LOAD(MAX)

×

-------------- – --------------

⎝

V_IN

(EQ. 7)

Common capacitor types used for such application

include aluminum, ceramic, POS CAP, and OSCON.

The selection of switching frequency is challenging.

While higher switching frequency results in smaller com-

ponents, it also results in lower efficiency. Ideal selection

of switching frequency takes into account the maximum

operating voltage. The MOSFET switching losses are

directly proportional to F_SWand the square function of

the input voltage.

Output Capacitor Selection (PWM)

The output capacitors chosen must have low enough

ESR to meet the output ripple and load transient require-

ments. The ESR of the output capacitor should be lower

than both of the values calculated below to satisfy both

the transient loading and steady-state ripple conditions

as given by the following equation:

When selecting the inductor, consider the minimum and

maximum load conditions. Lower inductor values pro-

duce better transient response, but result in higher ripple

and lower efficiency due to high RMS currents. Optimum

minimum inductance value enables the converter to

V_STEP

ESR ≤ ---------------------------------- and ESR ≤ ------------------

ΔI_LOAD(MAX)I_Ripple

V_Ripple

(EQ. 8)

FAN5099 Rev. 1.1.3

www.fairchildsemi.com

13

In the case of aluminum and polymer-based capacitors,

the output capacitance is typically higher than normally

required to meet these requirements. While selecting the

ceramic capacitors for the output; although lower ESR

can be achieved easily, higher capacitance values are

required to meet the V_OUT(MIN)restrictions during a load

transient. From the stability point of view, the zero

caused by the ESR of the output capacitor plays an

important role in the stability of the converter.

Output Capacitor Selection (LDO)

Figure 24. Drive Equivalent Circuit

For stable operation, the minimum capacitance of 100µF

with ESR around 100mΩ is recommended. For other val-

ues, contact the factory.

The upper graph in Figure 23 represents Drain-to-

Source Voltage (V_DS) and Drain Current (I_D) waveforms.

The lower graph details Gate-to-Source Voltage (V_GS

versus time with a constant current charging the gate.

The x-axis is representative of Gate Charge (Q_G). C_ISS

)

Power MOSFET Selection (PWM)

=

The FAN5099 is capable of driving N-Channel MOSFETs

as circuit switch elements. For better performance, MOS-

C_GD+ C_GSand controls t1, t2, and t4 timing. C_GD

receives current from the gate driver during t3 (as VDS is

falling). Obtain the gate charge (Q_G) parameters shown

on the lower graph from the MOSFET datasheets.

FET selection should address these key parameters

:

■

The maximum Drain-to-Source Voltage (V_DS) should be

at least 25% higher than the worst-case input voltage.

Assuming switching losses are about the same for both

the rising edge and falling edge, Q1's switching losses

occur during the shaded time when the MOSFET has

voltage across it and current through it.

■

The MOSFETs should have low Q_G, Q_GDand Q_GS

,

.

The R_{DS_ON}of the MOSFETs should be as low as possible.

In typical applications for a buck converter, the duty

cycles are lower than 20%. To optimize the selection of

MOSFETs for both the high-side and low-side, follow dif-

ferent selection criteria. Select the high-side MOSFET to

minimize the switching losses and the low-side MOSFET

to minimize the conduction losses due to the channel

and the body diode losses. Note that the gate drive

losses also affect the temperature rise on the controller.

Losses are given by Equations 9-11:

P_UPPER= P_SW+ P_COND

(EQ. 9)

V_DS× I_L

(EQ. 10)

⎛

⎞

P_SW

=

--------------------- × 2 × t_sF_SW

⎝

⎠

2

V_OUT

(EQ. 11)

⎛

⎝

⎞

P_COND

=

-------------- × I_O²_UT× R_DS(ON)

⎠

V_IN

For loss calculation, refer to Fairchild's Application Note

AN-6005 and the associated spreadsheet.

where P_UPPERis the upper MOSFET's total losses and

P_SWand P_CONDare the switching and conduction losses

for a given MOSFET R_DS(ON)is at the maximum junction

temperature (T_J) and t_Sis the switching period (rise or

fall time) and equals t2+t3, as shown in Figure 23.

High-Side Losses

To understand losses in the MOSFET, follow the MOS-

FET switching interval shown in Figure 23. The MOSFET

gate drive equivalent circuit is shown in Figure 24

.

The driver's impedance and C_ISSdetermine t2 while t3's

period is controlled by the driver's impedance and Q_GD

.

Since most of t_Soccurs when V_GS= V_SP,assume a con-

stant current for the driver to simplify the calculation of t_S

with the following equation:

Q_G(SW)

I_Driver

Q

t_s= ------------------- ≈ ------------------^G----⁽--^S----^W-----⁾-------------

(EQ. 12)

V_CC– V_SP

----------------------------------------

_Driver+ R_Gate

⎛

⎝

⎞

⎠

R

Most MOSFET vendors specify Q_GDand Q_GS. Q_G(SW)

can be determined as:

Q_G(SW)= Q_GD+ Q_GS– Q_THwhere Q_THis the gate

charge required to reach the MOSFET threshold (V_TH).

Note that for the high-side MOSFET, V_DSequals V_IN,

which can be as high as 20V in a typical portable appli-

cation. Include the power delivered to the MOSFET's

(P_GATE) in calculating the power dissipation required for

the FAN5099.

Figure 23. Switching Losses and Q_g

FAN5099 Rev. 1.1.3

www.fairchildsemi.com

14

P_GATEis determined by the following equation:

P_Gate= Q_G× V_CC× F_SW

R-C components for the snubber are selected as follows:

(EQ. 13)

a) Measure the SW node ringing frequency (F_ring) with a

low capacitance scope probe.

where Q_Gis the total gate charge to reach V_CC

Low-Side Losses

.

b) Connect a capacitor (C_SNUB) from SW node to GND

so that it reduces this ringing by half.

Q2 switches on or off with its parallel Schottky diode

simultaneously conducting, so the V_DS≈ 0.5V. Since

P_SWis proportional to V_DS, Q2's switching losses are

negligible and Q2 is selected based on R_DS(ON)alone.

c) Place a resistor (R_SNUB) in series with this capacitor.

R_SNUBis calculated using the following equation:

2

R_SNUB= ----------------------------------------------

π × F_ring× C_SNUB

(EQ. 16)

Conduction losses for Q2 are given by the equation:

d) Calculate the power dissipated in the snubber resisto-

ras shown in the following equation:

P_COND= (1 – D) × I_O²_UT× R_DS(ON)

(EQ. 14)

P_R(SNUB)= C_SNUB× V²_IN(MAX)× F_SW

(EQ. 17)

where R_DS(ON)is the R_DS(ON)of the MOSFET at the

highest operating junction temperature and D=V_OUT/V_IN

is the minimum duty cycle for the converter.

where, V_IN(MAX)is the maximum input voltage and FSW

is the converter switching frequency.

Since D_MIN< 20% for portable computers, (1-D) ≈ 1 pro-

duces a conservative result, simplifying the calculation.

The snubber resistor chosen should be de-rated to han-

dle the worst-case power dissipation. Do not use wire-

The maximum power dissipation (P_D(MAX)) is a function

of the maximum allowable die temperature of the low-

side MOSFET, the θ_JA,and the maximum allowable

ambient temperature rise. P_D(MAX)is calculated using

the following equation:

wound resistors for R_SNUB

.

Loop Compensation

Typically, the closed-loop crossover frequency (F_cross),

where the overall gain is unity, should be selected to

achieve optimal transient and steady-state response to

disturbances in line and load conditions. It is recom-

mended to keep F_crossbelow one-fifth of the switching

frequency of the converter. Higher phase margin tends to

have a more stable system with more sluggish response

to load transients. Optimum phase margin is about 60°, a

good compromise between steady-state and transient

responses. A typical design should address variations

over a wide range of load conditions and over a large

sample of devices.

T

_J(MAX)– T_A(MAX)

P_D(MAX)= ------------------------------------------------

θ_JA

(EQ. 15)

θ_JAdepends primarily on the amount of PCB area

devoted to heat sinking.

Selection of MOSFET Snubber Circuit

The switch node (SW) ringing is caused by fast switching

transitions due to energy stored in parasitic elements.

This ringing on the SW node couples to other circuits

around the converter if they are not handled properly. To

dampen ringing, an R-C snubber is connected across

the SW node and the source of the low-side MOSFET.

V_IN

Current

Sense

Amplifier

Q1

V_IN

R_RAMP

Ramp

Generator

L

R_DC

V_OUT

PWM

&

Summing

Amplifier

C

DRIVER

R_L

Q2

R_ES

C2

C1

R2

C3

R3

R_BIAS

R1

Reference

Figure 25. Closed-Loop System with Type-3 Network

FAN5099 Rev. 1.1.3

www.fairchildsemi.com

15

FAN5099 has a high gain error amplifier around which

the loop is closed. Figure 25 shows a type-3 compensa-

tion network. For type-2 compensation, R3 and C3 are

not used. Since the FAN5099 architecture employs sum-

ming current mode, type-2 compensation can be used

for most applications. For for further information about

type-2 compensation networks, refer to the following:

Note: For critical applications requiring wide loop band-

width using very low ESR output capacitors, use type-3

compensation.

■ Venable, H. Dean, "The K factor: A new mathematical

tool for stability analysis and synthesis," Proceedings

of Powercon, March 1983.

Type-3 Feedback Component Calculations

Use these steps to calculate feedback components:

Notation:

C₀= Net Output Filter Capacitance

G_p(s) = Net Gain of Plant = control-to-output transfer function

L = Inductor Value

R_DSON= On-State Drain-to Source Resistance of Low-side MOSFET

R_es= Net ESR of the output filter capacitors

R_L= Load Resistance

T_s= Switching Period

V_i= Input Voltage

F_SW= Switching Frequency

Equations:

Effective current sense resistance = R_i= 7 × R_DSON

(EQ. 18)

(EQ. 19)

R_L

Current modulator DC gain = M_i= ------

R_i

(V_i– 1.8) × T_s

V_m= 3.33 × 10¹⁰× ------------------------------------

Effective ramp amplitude =

R_ramp

(EQ. 20)

(EQ. 21)

V_i

Voltage modulator DC gain = M_v= -------

V_m

M_v× M_i

||

Plant DC gain = M_o= M_vM_i= -------------------

(EQ. 22)

(EQ. 23)

(EQ. 24)

(EQ. 25)

M_v+ M_i

π

Sampling gain natural frequency = ω_n= -----

T_s

M_O

M_v× R_i

⎛

⎞

⎠

Effective inductance = L_e= -------- × L + -------------------

⎝

M_v

ω_n× Q_z

M_v× R_i× R_L

||

R_p= -------------------------------- = (M_v× R_i) R_L

M_v× R_i+ R_L

FAN5099 Rev. 1.1.3

www.fairchildsemi.com

16

Poles and Zeros of Plant Transfer Function:

1

Plant zero frequency = f_z= -----------------------------------------

2 × π × C_o× R_es

(EQ. 26)

(EQ. 27)

1

Plant 1^stpole frequency = f_p1= ----------------------------------------------------------

L_e

⎛

⎞

2 × π × C_o× R_p+ ------

⎝

⎠

R_L

R_p

1

2 × π

1

Plant 2^ndpole frequency = f_p2= ------------ × -------------------- + ------

(EQ. 28)

(EQ. 29)

⎛

⎞

⎠

⎝

C_o× R_LL_e

ω²_n× L_e

Plant 3^rdpole frequency = f_p3= -------------------------

2 × π × R_p

Plant gain (magnitude) response:

2

f

⎛ ⎞

1 + ---

⎝ ⎠

f_z

G_p(f) = 20 × logM₀+ 10 × log ---------------------------------------------------------------------------------------------------------

2

f

⎛

⎞

⎠

⎛

⎞

⎠

⎞

⎠

1 + ------

× 1 + ------

⎝

f_p3

f_p1

f_p2

(EQ. 30)

(EQ. 31)

Plant phase response:

^–1⎛ ^f⎞

⎛

⎞

⎛

⎞

⎠

–1

f

–1

f

–1

f

⎛

∠G_P(f) = tan --- – tan ------ – tan ------ – –tan ------

⎝ ⎠

f_z

⎝

⎠

⎝

⎠

⎝

f_p3

f_p1

f_p2

Choose R1, R_BIASto set the output voltage using EQ.5. Choose the zero crossover frequency F_crossof the overall

loop. Typically F_crossshould be less than 1/5th of F_sw. Choose the desired phase margin. Typically this number should

be between 60° to 90°.

Calculate plant gain at F_crossusing EQ.30 by substituting F_crossin place of f. The gain that the amplifier needs to pro-

vide to get the required crossover is given by:

1

G_AMP= -------------------------------

(EQ. 32)

(EQ. 33)

G_p(F_cross

)

The phase boost required is calculated as given in (EQ. 33).

Phase Boost = M – ∠G_P(F_cross) – 90°

where M is the desired phase margin in degrees.

The feedback component values are now calculated as given in equations below:

2

⎧

⎫

⎬

⎭

Boost

⎛

⎞

K = Tan ---------------- + 45

(EQ. 34)

⎨

⎝

⎠

4

⎩

1

C2 = -----------------------------------------------------------------------

2 × π × F_cross× G_AMP× R1

(EQ. 35)

(EQ. 36)

(EQ. 37)

C1 = C2 × (K – 1)

1

C3 = ---------------------------------------------------------------

2 × π × F_cross

× K × R3

K

R2 = -------------------------------------------------

2 × π × F_cross× C1

(EQ. 38)

(EQ. 39)

R1

R3 = -----------------

(K – 1)

FAN5099 Rev. 1.1.3

www.fairchildsemi.com

17

Design Tools

Layout Considerations

Fairchild application note AN-6020 provides a PSPICE

model and spreadsheet calculator for the PWM regula-

tor, simplifying external component selections and verify-

ing loop stability. The topics covered in the datasheet

provide an understanding behind the calculations in the

spreadsheet.

The switching power converter layout needs careful

attention and is critical to achieving low losses and clean

and stable operation. Below are specific recommenda-

tions for a good board layout:

■ Keep the high current traces and load connections as

short as possible.

The spreadsheet calculator, which is part of AN-6020

can be used to calculate all external component values

for designing around FAN5099. The spreadsheet pro-

vides optimized compensation components and gener-

ates a Bode plot to ensure loop stability.

■ Use thick copper boards whenever possible to

achieve higher efficiency.

■ Keep the loop area between the SW node, low-side

MOSFET, inductor, and the output capacitor as small

as possible.

■ Route high dV/dt signals, such as SW node, away

from the error amplifier input/output pins. Keep com-

ponents connected to these pins close to the pins.

Based on the input values entered, AN-6020’s PSPICE

model can be used to simulate Bode plots (for loop sta-

bility) as well as transient analysis that help customize

the design for a wide range of applications.

■ Place ceramic de-coupling capacitors very close to

V_CCpin.

Use Fairchild application note AN-6005 for prediction of

the losses and die temperatures for the power semicon-

ductors used in the circuit.

■ All input signals are referenced with respect to AGND

pin. Dedicate one layer of the PCB for a GND plane.

Use at least four layers for the PCB.

Both AN-6020 and AN-6005 can be downloaded from

www.fairchildsemi.com/apnotes/.

■ Minimize GND loops in the layout to avoid EMI-related

issues.

■ Use wide traces for the lower gate drive to keep the

drive impedances low.

■ Connect PGND directly to the lower MOSFET source

pin.

■ Use wide land areas with appropriate thermal vias to

effectively remove heat from the MOSFETs.

■ Use snubber circuits to minimize high-frequency

ringing at the SW nodes.

■ Place the output capacitor for the LDO close to the

source of the LDO MOSFET.

FAN5099 Rev. 1.1.3

www.fairchildsemi.com

18

Application Board Schematic

V_IN= 3 to 24V; V_OUT=1.5V at 20A; F_OSC= 300kHz.

Figure 26. Application Board Schematic

Bill of Materials

Vendor Part

Number

Part Description

Quantity Designator

Vendor

Capacitor, 1500pF, 10%, 50V, 0603, X7R

Capacitor, 220pF, 5%, 50V, 0603, NPO

Capacitor, 3300pF, 10%, 50V, 0603, X7R

Capacitor, 0.1µF, 10%, 25V, 0603, X7R

Capacitor, 0.22µF, 20%, 25V, 0603, X7R

Capacitor, 0.01µF, 10%, 50V, 0603, X7R

Capacitor, 820µF, 20%, 10X20, 25V, 20mΩ, 1.96A

Capacitor, 820µF, 20%, 8X8, 2.5V, 7mΩ, 6.1A

Capacitor, 560µF, 20%, 8X11.5, 4V, 7mΩ, 5.58A

Capacitor, 3300pF, 10%, 50V, 0805, X7R

Connector Header 0.100 Vertical, Tin – 2 Pin

Terminal Quickfit Male .052"Dia.187" Tab

Inductor, 1.8µH, 20%, 26Amps Max, 3.24mΩ

MOSFET N-CH, 32mΩ, 20V, 21A, D-PAK, FSID: FDD6530A

MOSFET N-CH, 8.8mΩ, 30V, 50A, D-PAK, FSID: FDD6296

MOSFET N-CH, 6mΩ, 30V, 75A, D-PAK, FSID: FDD6606

Resistor, 5.11k, 1%, 1/16W

1

C1

C2

C3

Panasonic

ECJ1VB1H152K

ECJ1VC1H221J

ECJ1VB1H332K

ECJ1VB1E104K

C1608JB1E224K

ECJ1VB1H103K

KZH25VB820MHJ20

PSC2.5VB820MH08

PSA4VB560MH11

ECJ2VB1H332K

22-28-4360

1

4

2

1

2

1

3

1

6

1

2

1

3

1

Panasonic

C4, C5, C6, C15 Panasonic

C7, C8

TDK

C9

Panasonic

C10, C11

Nippon-Chemicon

Panasonic

C17

C12, C13, C14

C16

J1

Molex

J2–J7

Keystone

1212

L1

Inter-Technical

Fairchild Semiconductor

Panasonic

SC5018-1R8M

FDD6530A

Q1

Q2

FDD6296

Q3, Q4

FDD6606

R1

ERJ3EKF5111V

ERJ3EKF1272V

ERJ3EKF8250V

ERJ3EKF2552V

ERJ3EKF2103V

ERJ3EKF453V

ERJ3EKF1002V

ERJ3EKF4991V

ERJ8ENF2000V

ERJ3EKF5901V

ERJ8RQF2R2V

22-28-4360

Resistor, 12.7k, 1%, 1/16W

R2

Panasonic

Resistor, 825, 1%, 1/16W

R3

Panasonic

Resistor, 25.5k, 1%, 1/16W

R4

Panasonic

Resistor, 210k, 1%, 1/16W

R5

Panasonic

Resistor, 453k, 1%, 1/16W

R6

Panasonic

Resistor, 10k, 1%, 1/16W

R7

Panasonic

Resistor, 4.99k, 1%, 1/16W

R8

Panasonic

Resistor, 200, 1%, 1/4W

R9

Panasonic

Resistor, 5.90k, 1%, 1/16W

R10

Panasonic

Resistor, 2.2, 1%, 1/4W

R11

Panasonic

Connector Header 0.100 Vertical, Tin – 1 Pin

IC, System Regulator, TSSOP16, FSID: FAN5099

TP1, TP2, Vcc

U1

Molex

Fairchild Semiconductor

FAN5099

FAN5099 Rev. 1.1.3

www.fairchildsemi.com

19

Application Board Schematic

V_IN= 3 to 24V; V_OUT=1.5V at 20A; F_OSC= 80kHz.

Figure 27. Application Board Schematic

Bill of Materials

Vendor Part

Number

Part Description

Quantity Designator

Vendor

Capacitor, 3900pF, 10%, 50V, 0603, X7R

Capacitor, 680pF, 5%, 50V, 0603, NPO

Capacitor, 6800pF, 10%, 50V, 0603, X7R

Capacitor, 0.1µF, 10%, 25V, 0603, X7R

Capacitor, 0.22µF, 20%, 25V, 0603, X7R

Capacitor, 0.01µF, 10%, 50V, 0603, X7R

Capacitor, 820µF, 20%, 10X20, 25V, 20mΩ, 1.96A

Capacitor, 820µF, 20%, 8X8, 2.5V, 7mΩ, 6.1A

Capacitor, 560µF, 20%, 8X11.5, 4V, 7mΩ, 5.58A

Capacitor, 3300pF, 10%, 50V, 0805, X7R

Connector Header 0.100 Vertical, Tin – 2 Pin

Terminal Quickfit Male .052"Dia.187" Tab

1

C1

Panasonic

ECJ1VB1H392K

ECJ1VC1H681J

ECJ1VB1H682K

ECJ1VB1E104K

C1608JB1E224K

ECJ1VB1H103K

KZH25VB820MHJ20

PSC2.5VB820MH08

PSA4VB560MH11

ECJ2VB1H332K

22-28-4360

1

4

2

1

2

1

3

1

6

1

C2

Panasonic

C3

Panasonic

C4, C5, C6, C15

Panasonic

C7, C8

C9

TDK

Panasonic

C10, C11

C17

Nippon-Chemicon

Panasonic

C12, C13, C14

C16

J1

Molex

J2–J7

L1

Keystone

1212

Inductor, 4.0µH@25A, 9.0µH@0A, 25A max, 4.4mΩ, wound

on T80-52B core (Micrometals), 12 turns, 14 AWG wire

Custom made

MOSFET N-CH, 32mΩ, 20V, 21A, D-PAK, FSID: FDD6530A

MOSFET N-CH, 8.8mΩ, 30V, 50A, D-PAK, FSID: FDD6296

MOSFET N-CH, 6mΩ, 30V, 75A, D-PAK, FSID: FDD6606

Resistor, 5.11k, 1%, 1/16W

1

2

1

3

1

Q1

Fairchild Semiconductor

Panasonic

FDD6530A

Q2

FDD6296

Q3, Q4

FDD6606

R1

ERJ3EKF5111V

ERJ3EKF1052V

ERJ3EKF8450V

ERJ3EKF2003V

ERJ3EKF2873V

ERJ3EKF453V

ERJ3EKF1002V

ERJ3EKF4991V

ERJ8ENF2000V

ERJ3EKF5901V

ERJ8RQF2R2V

22-28-4360

Resistor, 10.5k, 1%, 1/16W

R2

Panasonic

Resistor, 845, 1%, 1/16W

R3

Panasonic

Resistor, 200k, 1%, 1/16W

R4

Panasonic

Resistor, 287k, 1%, 1/16W

R5

Panasonic

Resistor, 453k, 1%, 1/16W

R6

Panasonic

Resistor, 10k, 1%, 1/16W

R7

Panasonic

Resistor, 4.99k, 1%, 1/16W

R8

Panasonic

Resistor, 200, 1%, 1/4W

R9

Panasonic

Resistor, 5.90k, 1%, 1/16W

R10

Panasonic

Resistor, 2.2, 1%, 1/4W

R11

Panasonic

Connector Header 0.100 Vertical, Tin – 1 Pin

IC, System Regulator, TSSOP16, FSID: FAN5099

TP1, TP2, Vcc

U1

Molex

Fairchild Semiconductor

FAN5099

FAN5099 Rev. 1.1.3

www.fairchildsemi.com

20

Typical Application Board Layout

Figure 31. Mid Layer 2

Figure 28. Assembly Diagram

Figure 29. Top Layer

Figure 32. Bottom Layer

Figure 30. Mid Layer 1

FAN5099 Rev. 1.1.3

www.fairchildsemi.com

21

Mechanical Dimensions

16-Lead TSSOP

All dimensions are in millimeters unless otherwise specified.

Figure 33. 16-Lead Thin Shrink Small Outline Package

FAN5099 Rev. 1.1.3

www.fairchildsemi.com

22

Mechanical Dimensions (continued)

16-Lead SOIC

All dimensions are in millimeters unless otherwise specified.

Figure 34. 16-Lead Molded Small Outline Package

FAN5099 Rev. 1.1.3

www.fairchildsemi.com

23

FAN5099 Rev. 1.1.3

www.fairchildsemi.com

24


型号：	FAN5099
厂家：	FAIRCHILD SEMICONDUCTOR
描述：	Wide Frequency Synchronous Buck PWM AND LDO Controller 宽广的频率同步降压PWM和LDO控制器控制器
文件：	总24页 (文件大小：1018K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

FAN5099 [FAIRCHILD]

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