FAN53418M [FAIRCHILD]
Synchronous DC-DC MOSFET Driver; 同步DC-DC MOSFET驱动器
| 型号： | FAN53418M |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Synchronous DC-DC MOSFET Driver |
| 文件： | 总11页 (文件大小：258K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
www.fairchildsemi.com
FAN53418
Synchronous DC-DC MOSFET Driver
Features
General Description
• Drives N-channel High-Side and Low-Side MOSFETs in
a synchronous buck configuration
• Internal Adaptive “Shoot-Through” Protection
• High Switching Frequency (> 500kHz)
– 30ns Output Rise/Fall Times w/3000pF load
– 20ns Propagation Delay
The FAN53418 is a high frequency, dual MOSFET driver
specifically designed to drive two power N-Channel
MOSFETs in a synchronous rectified buck converter.
These drivers combined with a FAN53168 Multi-Phase Buck
PWM controller and power MOSFETs form a complete core
voltage regulator solution for advanced microprocessors.
• 12V High-Side and 12V Low-Side Drive
• OD input for Output Disable – allows for synchronization
with PWM controller
The FAN53418 drives both the upper and lower gates in a
synchronous rectifier to +12V. The upper gate drive imple-
ments bootstrapping with only an external capacitor and
diode required. This reduces implementation complexity
and allows the use of higher performance, cost effective,
N-Channel MOSFETs.
• SOIC-8 Package
Applications
• Multi-phase VRM/VRD regulators for Microprocessor
Power
• High Current/High Frequency DC/DC Converters
• High Power Modular Power Supplies
The output drivers in the FAN53418 have the capacity to
efficiently switch power MOSFETs at frequencies over
500kHz. Each driver is capable of driving a 3000pF load
with a ~20ns propagation delay and ~30ns transition time.
Adaptive shoot-through protection is integrated to prevent
both MOSFETs from conducting simultaneously. Addition-
ally an Output Disable function is included to synchronize
the driver with the PWM controller. The FAN53418 is
rated for operation from 0°C to +85°C and is available in a
low-cost SOIC-8 package.
Basic Application
+12V
C
BST
C
Q1
VIN
D1
1
2
3
4
8
7
6
5
BST
IN
DRVH
SW
L1
FAN54318
OD
PGND
Q2
VCC
DRVL
C
VCC
Figure 1. Basic Application Circuit
REV. 1.0.0 6/11/03
FAN53418
Pin Configuration
BST
1
2
3
4
8
7
6
5
DRVH
SW
IN
OD
FAN53418
SOIC-8
PGND
DRVL
VCC
Pin Description
Pin Number
Pin Name
Pin Function Description
1
BST
Bootstrap Supply Input. Provides voltage supply to high-side MOSFET driver.
Connect to bootstrap capacitor (typically 100nF to 1µF). See Applications
Section for detailed information.
2
3
IN
PWM Signal Input. This pin accepts a digital logic-level PWM switching signal
from the controller.
OD
Output Disable. When low, this pin disables PWM switching and pulls DRVH
and DRVL low.
4
5
VCC
Power Input. +12V chip bias power. Bypass with a 1µF ceramic capacitor.
DRVL
Low Side Gate Drive Output. Connect to the gate of low-side power
MOSFET(s).
6
7
PGND
SW
Power Ground. Power ground connect close to low-side MOSFET to minimize
ground loops.
Switch Node Input. Connect to switching node between HS and LS MOSFETs.
It is necessary for adaptive shoot-thru protection. Also it provides return for
high-side bootstrapped driver.
8
DRVH
High Side Gate Drive Output. Connect to the gate of high-side power
MOSFET(s).
Internal Block Diagram
VCC
4
IN
2
1
8
BST
DRVH
Delay
+1V
7
SW
5
6
DRVL
PGND
+1V
1kΩ
3
OD
2
REV. 1.0.0 6/11/03
FAN53418
Absolute Maximum Ratings
Absolute maximum ratings are the values beyond which the device may be damaged or have its useful life
impaired. Functional operation under these conditions is not implied.
Parameter
Min.
-0.3
Max.
+15
Units
Supply Voltage: VCC to PGND
SW to PGND
V
V
V
V
V
V
V
-5
+15
BST to SW Voltage: VBST – VSW
BST Voltage: VBST – PGND
DRVH
-0.3
+15
-0.3
VCC + 15
VBST + 0.3
VCC + 0.3
VCC + 0.3
VSW – 0.3
-2
DRVL (<200ns duration)
Voltage on any other pin
-0.3
Thermal Information
Parameter
Min.
0
Typ.
Max.
Units
Operating Junction Temperature (TJ)
Storage Temperature
+150
+150
+300
+215
+220
1052
°C
°C
–65
Lead Soldering Temperature, 10 seconds
Vapor Phase, 60 seconds
Infrared, 15 seconds
°C
°C
°C
Power Dissipation (PD) @ TA = 25°C
Thermal Resistance (ΘJA)*
mW
°C/W
95
Recommended Operating Conditions See Figure 1
Parameter
Conditions
Min.
10.8
0
Typ.
Max.
13.2
+85
Units
V
Supply Voltage VCC
VCC to GND
12
Ambient Operating Temperature
Operating Junction Temperature (TJ)
°C
0
+150
°C
Note:
1.
2
Θ
is defined as 2 oz., 4 layer copper PCB with 1 in thermal pad.
JA
REV. 1.0.0 6/11/03
3
FAN53418
Electrical Specifications
(Vcc = 12V, and TA = 0°C to +85°C, VBST = 4V to 26V, unless otherwise noted.)
The • denotes specifications which apply over the full operating temperature range.
Parameter
Symbol
Conditions
Min.
Typ.
Max. Units
Input Supply
Supply Voltage Range
Supply Current
OD Input
VCC
•
•
4.15
13.2
6
V
ISYS
BST = 12V, IN = 0V
3
mA
Input High Voltage
Input Low Voltage
Input Current
VIH(OD)
VIL(OD)
IIL(OD)
•
•
•
2.8
-1
V
V
0.8
+1
µA
Propagation Delay Time2 tpdl(OD)
tpdh(OD)
See Figure 2
See Figure 2
•
•
15
20
30
40
ns
ns
PWM Input
Input High Voltage
Input Low Voltage
Input Current
VIH(PWM)
VIL(PWM)
IIL(PWM)
•
•
•
3.5
-1
V
V
0.8
+1
µA
High-Side Driver
Output Resistance,
Sourcing Current
VBST – VSW = 12V
VBST – VSW = 12V
•
•
•
•
1.8
1.0
35
3.0
2.5
45
Ω
Ω
Output Resistance,
Sinking Current
Transition Times2
trDRVH
tfDRVH
See Figure 3, VBST – VSW = 12V,
CLOAD=3nF
ns
ns
See Figure 3, VBST – VSW = 12V,
CLOAD=3nF
20
30
Propagation Delay2,3
tpdhDRVH
tpdlDRVH
See Figure 3, VBST – VSW = 12V
See Figure 3, VBST – VSW = 12V
•
•
40
20
65
35
ns
ns
Low-Side Driver
Output Resistance,
Sourcing Current
•
•
1.8
1.0
3.0
2.5
Ω
Ω
Output Resistance,
Sinking Current
Transition Times2
trDRVL
tfDRVL
See Figure 3, CLOAD = 3nF
See Figure 3, CLOAD = 3nF
•
•
25
21
35
30
ns
ns
Propagation Delay2,3
tpdhDRVL
tpdlDRVL
See Figure 3
See Figure 3
•
30
10
60
20
ns
ns
Notes:
1. All limits at operating temperature extremes are guaranteed by design, characterization and statistical quality control.
2. AC Specifications guaranteed by design/characterization – NOT tested in production.
3. For propagation delays “t ” refers to low-to-high signal transition and “t ” refers to high-to-low signal transition.
pdh
pdl
4
REV. 1.0.0 6/11/03
FAN53418
Timing Characteristics
V
IH(OD)
OD
V
IL(OD)
t
t
pdh(OD)
pdl(OD)
90%
HDRV/LDRV
10%
Figure 2. Output Disable Timing
t
IN
f(DRVL)
t
pdl(DRVL)
t
pdl(DRVH)
t
DRVL
f(DRVH)
t
t
r(DRVH)
r(DRVL)
t
pdh(DRVH)
DRVH-SW
V
V
TH
TH
SW
1V
pdh(DRVH)
t
Figure 3. Non-overlap Timing Diagram (Timing is referenced to the 90% and 10% points unless otherwise noted)
REV. 1.0.0 6/11/03
5
FAN53418
Typical Characteristics
DRVH Rise and DRVL Fall Times
DRVH and DRVL Fall Times vs. Temperature
DRVH and DRVL Rise Times vs. Load Capacitance
DRVH Fall and DRVL Rise Times
DRVH and DRVL Rise Times vs. Temperature
DRVH and DRVL Fall Times vs. Load Capacitance
6
REV. 1.0.0 6/11/03
FAN53418
Typical Characteristics (Continued)
Supply Curreny vs. Frequency
DRVL Output Voltage vs. Supply Voltage
Supply Current vs. Temperature
REV. 1.0.0 6/11/03
7
FAN53418
waiting for the voltage on the SW pin to reach 1V, the over-
lap protection circuit ensures that Q1 is off before Q2 turns
on, regardless of variations in temperature, supply voltage,
gate charge, and drive current.
Theory of Operation
The FAN53418 is a dual MOSFET driver optimized for
driving two N-channel MOSFETs in a synchronous buck
converter topology. A single PWM input signal is all that is
required to properly drive the high-side and the low-side
MOSFETs. Each driver is capable of driving a 3nF load at
frequencies over 500kHz.
To prevent the overlap of the gate drives during Q2’s turn off
and Q1’s turn on, the overlap circuit provides a internal delay
that is set to 50ns. When the PWM input signal goes high,
Q2 will begin to turn off (after a propagation delay), but
before Q1 can turn on the overlap protection circuit waits for
the voltage at DRVL to drop to around 10% of VCC. Once
the voltage at DRVL has reached the 10% point, the overlap
protection circuit will wait for a 20 ns typical propagation
delay. Once the delay period has expired, Q1 will begin
turn on.
A more detailed description of the FAN53418 and its
features follows. Refer to the Internal Block Diagram.
Low-Side Driver
The low-side driver is designed to drive a ground-referenced
low RDS(on) N-channel MOSFETs. The bias to the low-side
driver is internally connected to the VCC supply and PGND.
When the driver is enabled, the driver’s output is 180 degrees
out of phase with the PWM input. When the FAN53418 is
disabled, the low-side gate is held low.
Application Information
Supply Capacitor Selection
For the supply input (VCC) of the FAN53418, a local bypass
capacitor is recommended to reduce the noise and to supply
some of the peak currents drawn. Use a 4.7µF, low ESR
capacitor. Multilayer ceramic chip (MLCC) capacitors pro-
vide the best combination of low ESR and small size. Keep
the ceramic capacitor as close as possible to the FAN53418.
High-Side Driver
The high-side driver is designed to drive a floating low
RDS(on) N-channel MOSFET. The bias voltage for the
high-side driver is developed by an external bootstrap supply
circuit, which is connected between the BST and SW pins.
The bootstrap circuit comprises a diode, D1, and bootstrap
capacitor, CBST. When the FAN53418 is starting up, the SW
pin is at ground, so the bootstrap capacitor will charge up to
VCC through D1. When the PWM input goes high,
Bootstrap Circuit
The bootstrap circuit uses a charge storage capacitor (CBST
and a diode, as shown in Figure 1. Selection of these
components can be done after the high-side MOSFET has
been chosen.
)
the high-side driver will begin to turn the high-side
MOSFET, Q1, on by pulling charge out of CBST. As Q1
turns on, the SW pin will rise up to VIN, forcing the BST pin
to VIN +VC(BST), which is enough gate to source voltage to
hold Q1 on. To complete the cycle, Q1 is switched off by
pulling the gate down to the voltage at the SW pin. When the
low-side MOSFET, Q2, turns on, the SW pin is pulled to
ground. This allows the bootstrap capacitor to charge up to
The bootstrap capacitor must have a voltage rating that is
able to handle twice the maximum supply voltage. A mini-
mum 50V rating is recommended. The capacitance is
determined using the following equation:
QGATE
(1)
VCC again.
CBST = ------------------
∆VBST
The high-side driver’s output is in phase with the PWM
input. When the driver is disabled, the high-side gate is
held low.
where QGATE is the total gate charge of the high-side
MOSFET, and ∆VBST is the voltage droop allowed on the
high-side MOSFET drive. For example, an FDD6696 has a
total gate charge of about 17nC. For an allowed droop of
200mV, the minimum required bootstrap capacitance is
85nF. A good quality 100nF X7R ceramic capacitor should
be used.
Overlap Protection Circuit
The overlap protection circuit prevents both of the main
power switches, Q1 and Q2, from being on at the same time.
This is done to prevent shoot-through currents from flowing
through both power switches and the associated losses that
can occur during their on-off transitions. The overlap pro-
tection circuit accomplishes this by adaptively controlling
the delay from Q1’s turn off to Q2’s turn on, and by inter-
nally setting the delay from Q2’s turn off to Q1’s turn on.
A small–signal diode can be used for the bootstrap diode
due to the ample gate drive voltage supplied by VCC. The
bootstrap diode must have a minimum 15V rating to with-
stand the maximum supply voltage. The average forward
current can be estimated by:
To prevent the overlap of the gate drives during Q1’s turn off
and Q2’s turn on, the overlap circuit monitors the voltage at
the SW pin. When the PWM input signal goes low, Q1 will
begin to turn off (after a propagation delay), but before Q2
can turn on the overlap protection circuit waits for the volt-
age at the SW pin to fall from VIN to 1V. Once the voltage on
the SW pin has fallen to 1V, Q2 will begin turn on. By
(2)
IF(AVG) = QGATE × fMAX
where fMAX is the maximum switching frequency of the
controller. The peak surge current rating should be checked
in-circuit, since this is dependent on the source impedance of
the 12V supply and the ESR of CBST
.
8
REV. 1.0.0 6/11/03
FAN53418
PC Board Layout Considerations
Use the following general guidelines when designing printed
circuit boards:
C
BST
D1
1. Trace out the high-current paths and use short, wide
(>20 mil) traces to make these connections.
2. Connect the PGND pin of the FAN53418 as close as
possible to the source of the lower MOSFET.
3. The VCC bypass capacitor should be located as close as
possible to VCC and PGND pins.
4. Use vias to other layers when possible to maximize
thermal conduction away from the IC.
Figure 4 gives an example of typical land patterns based on
the guidelines given above. For a complete CPU voltage
regulator subsystem, please refer to the FAN53168 data
sheet.
C
VCC
Figure 4. External Component Placement
Examples for the FAN53418
REV. 1.0.0 6/11/03
9
FAN53418
Mechanical Dimensions
8-Lead Small Outline IC (SOIC) 0.150" Body Width
Inches
Millimeters
Symbol
Notes
Min.
Max.
Min.
Max.
A
.053
.004
.013
.069
.010
.020
.010
.197
.158
1.35
0.10
0.33
0.20
4.80
3.81
1.75
0.25
0.51
0.25
5.00
4.01
A1
B
C
D
E
.0075
.189
.150
5
2
2
e
.050 BSC
1.27 BSC
H
h
.228
.010
.016
.244
.020
.050
5.79
0.25
0.40
6.20
0.50
1.27
L
3
6
N
α
8
8
0°
8°
0°
8°
ccc
—
.004
—
0.10
Notes:
1. Dimensioning and tolerancing per ANSI Y14.5M-1982.
2. "D" and "E" do not include mold flash. Mold flash or
protrusions shall not exceed .010 inch (0.25mm).
3. "L" is the length of terminal for soldering to a substrate.
4. Terminal numbers are shown for reference only.
5. "C" dimension does not include solder finish thickness.
6. Symbol "N" is the maximum number of terminals.
8
1
5
4
E
H
D
A1
h x 45°
A
C
SEATING
PLANE
– C –
α
e
LEAD COPLANARITY
L
B
ccc C
10
REV. 1.0.0 6/11/03
FAN53418
Ordering Information
Part Number
Temperature Range
0°C to +85°C
Package
FAN53418M
SOIC-8
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO
ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME
ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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6/11/03 0.0m 003
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© 2003 Fairchild Semiconductor Corporation
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