FAN54010UCX(1)_技术文档

July 2012

FAN54010 / FAN54011 / FAN54012 / FAN54013 / FAN54014

USB-Compliant Single-Cell Li-Ion Switching Charger with

USB-OTG Boost Regulator

Features

Description

The FAN54010 family (FAN5401X) combines

a highly

.

Fully Integrated, High-Efficiency Charger for Single-Cell

Li-Ion and Li-Polymer Battery Packs

integrated switch-mode charger, to minimize single-cell Lithium-

ion (Li-ion) charging time from a USB power source, and a

boost regulator to power a USB peripheral from the battery.

.

Faster Charging than Linear

Charge Voltage Accuracy:

0.5% at 25°C

1% from 0 to 125°C

The charging parameters and operating modes are

programmable through an I²C Interface that operates up to

3.4 Mbps. The charger and boost regulator circuits switch at

3MHz to minimize the size of external passive components.

.

5% Input Current Regulation Accuracy

5% Charge Current Regulation Accuracy

20 V Absolute Maximum Input Voltage

6 V Maximum Input Operating Voltage

1.45 A Maximum Charge Rate

The FAN5401X provides battery charging in three phases:

conditioning, constant current, and constant voltage.

To ensure USB compliance and minimize charging time, the

input current is limited to the value set through the I²C host.

Charge termination is determined by a programmable

minimum current level. A safety timer with reset control

provides a safety backup for the I²C host.

Programmable through High-Speed I²C Interface

(3.4 Mb/s) with Fast Mode Plus Compatibility

–

Input Current

The integrated circuit (IC) automatically restarts the charge

cycle when the battery falls below an internal threshold. If the

input source is removed, the IC enters a high-impedance

mode with leakage from the battery to the input prevented.

Charge status is reported back to the host through the I²C

port. Charge current is reduced when the die temperature

reaches 120°C.

Fast-Charge / Termination Current

Charger Voltage

Termination Enable

.

3 MHz Synchronous Buck PWM Controller with Wide

Duty Cycle Range

.

Small Footprint 1H External Inductor

The FAN5401X can operate as a boost regulator on

command from the system. The boost regulator includes a

soft-start that limits inrush current from the battery.

Safety Timer with Reset Control

1.8 V Regulated Output from VBUS for Auxiliary Circuits

The FAN5401X is available in a 1.96 x 1.87 mm, 20-bump,

0.4 mm pitch, WLCSP package.

Weak Input Sources Accommodated by Reducing

Charging Current to Maintain Minimum VBUS Voltage

.

Low Reverse Leakage to Prevent Battery Drain to VBUS

5 V, 500 mA Boost Mode for USB OTG for 3.0 V to

4.5 V Battery Input

Applications

.

Cell Phones, Smart Phones, PDAs

Tablet, Portable Media Players

Gaming Device, Digital Cameras

Figure 1. Typical Application

All trademarks are the property of their respective owners.

FAN5401X Family • Rev. 1.0.4

www.fairchildsemi.com

Ordering Information

Part Number

FAN54010UCX⁽¹⁾

FAN54011UCX⁽¹⁾

FAN54012UCX⁽¹⁾

FAN54013UCX

FAN54014UCX⁽¹⁾

Temperature Range

Package

PN Bits: IC_INFO[4:2] Packing Method

-40 to 85°C

011

001

011

101

111

Tape and Reel

20-Bump, Wafer-Level

Chip-Scale Package

(WLCSP),

0.4 mm Pitch,

Estimated Size:

1.96 x 1.87 mm

Note:

1. Preliminary release only; please contact a Fairchild representative for information about part availability.

Table 1. Feature Comparison Summary

Battery

Slave

Automatic

Charge

Special

Safety

VREG

(E3 Pin)

PN Bits:

Part Number

Absent

E2 Pin

REG3[4:2]

Address

Charger⁽²⁾Limits

Behavior

FAN54010UCX

FAN54011UCX

FAN54012UCX

FAN54013UCX

FAN54014UCX

Note:

011

001

011

101

111

1101011

Yes

No

OFF

ON

AUXPWR

(Connect

to VBAT)

PMID

1.8V

Yes

No

Yes

OFF

DISABLE

2. A “special charger” is a current-limited charger that is not a USB compliant source.

Table 2. Recommended External Components

Component

Description

Vendor

Parameter

Typ.

Unit

1 µH ±20%, 1.6 A

DCR=55 mΩ, 2520

Murata: LQM2HPN1R0

L1

L

1.0

H

1 µH ±30%, 1.4A

DCR=85 mΩ, 2016

Murata: LQM2MPN1R0

Murata: GRM188R60J106M

TDK: C1608X5R0J106M

C_BAT

C_MID

10 µF, 20%, 6.3 V, X5R, 0603

4.7 µF, 10%, 6.3 V, X5R, 0603

1.0 µF, 10%, 25 V, X5R, 0603

C

C⁽³⁾

C

10

4.7

1.0

F

Murata: GRM188R60J475K

TDK: C1608X5R0J475K

Murata GRM188R61E105K

TDK:C1608X5R1E105M

C_BUS

Note:

3. A 6.3 V rating is sufficient for C_MIDsince PMID is protected from over-voltage surges on VBUS by Q3 (Figure 3).

FAN5401X Family • Rev. 1.0.4

www.fairchildsemi.com

2

Block Diagram

Figure 2. IC and System Block Diagram

VBUS

C_IN1

PMID

Q3

C_IN2

CHARGE

PUMP

Q1

Q1A

Q1B

CSIN

SW

L1

PMID

Greater than V_BAT

Less than V_BAT

Q1A Q1B

ON OFF

OFF ON

Q2

1H

R_SENSE

68m

C_OUT

PGND

VBAT

Battery

+

C_BAT

SYSTEM

LOAD

Figure 3. Power Stage

FAN5401X Family • Rev. 1.0.4

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3

Pin Configuration

A1

B1

C1

D1

E1

A2

B2

C2

D2

E2

A3

B3

C3

D3

E3

A4

B4

C4

D4

E4

A4

B4

C4

D4

E4

A3

B3

C3

D3

E3

A2

B2

C2

D2

E2

A1

B1

C1

D1

E1

Top View

Bottom View

Figure 4. WLCSP-20 Pin Assignments

Pin Definitions

Pin #

A1, A2

A3

Name

VBUS

NC

Part # Description

ALL Charger Input Voltage and USB-OTG output voltage. Bypass with a 1 µF capacitor to PGND.

ALL No Connect. No external connection is made between this pin and the IC’s internal circuitry.

ALL I²C Interface Serial Clock. This pin should not be left floating.

A4

SCL

Power Input Voltage. Power input to the charger regulator, bypass point for the input current

ALL sense, and high-voltage input switch. Bypass with a minimum of 4.7 µF, 6.3 V capacitor to

PGND.

B1-B3

PMID

B4

C1-C3

C4

SDA

SW

ALL I²C Interface Serial Data. This pin should not be left floating.

ALL Switching Node. Connect to output inductor.

STAT

ALL Status. Open-drain output indicating charge status. The IC pulls this pin LOW when charging.

Power Ground. Power return for gate drive and power transistors. The connection from this pin

to the bottom of C_MIDshould be as short as possible.

D1-D3

D4

PGND

OTG

ALL

On-The-Go. Enables boost regulator in conjunction with OTG_EN and OTG_PL bits (see Table

16). On VBUS Power-On Reset (POR), this pin sets the input current limit for t_15MINcharging.

ALL

Current-Sense Input. Connect to the sense resistor in series with the battery. The IC uses this

node to sense current into the battery. Bypass this pin with a 0.1F capacitor to PGND.

E1

CSIN

ALL

10, 11, Auxiliary Power. Connect to the battery pack to provide IC power during High-Impedance

E2

AUXPWR

12

Mode. Bypass with a 1 µF capacitor to PGND.

Charge Disable. If this pin is HIGH, charging is disabled. When LOW, charging is controlled by

the I²C registers. When this pin is HIGH, the 15-minute timer is reset. This pin does not affect

the 32-second timer.

13, 14,

E2

DISABLE

Regulator Output. Connect to a 1 µF capacitor to PGND. This pin can supply up to 2 mA of DC

E3

E4

VREG

VBAT

ALL load current. For FAN54010-FAN54012, the output voltage is PMID, which is limited to 6.5 V.

For FAN54013-FAN54014, the output voltage is regulated to 1.8 V.

Battery Voltage. Connect to the positive (+) terminal of the battery pack. Bypass with a 0.1 μF

ALL

capacitor to PGND if the battery is connected through long leads.

FAN5401X Family • Rev. 1.0.4

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4

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above

the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended

exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum

ratings are stress ratings only.

Symbol

V_BUS

V_STAT

V_I

Parameter

Min.

–1.4

–2.0

–0.3

Max.

Unit

Continuous

VBUS Voltage

20.0

V

Pulsed, 100 ms Maximum Non-Repetitive

STAT Voltage

PMID Voltage

16.0

7.0

V

SW, CSIN, VBAT, AUXPWR, DISABLE Voltage

Voltage on Other Pins

–0.3

7.0

6.5⁽⁴⁾

V_O

V

dV_BUS

dt

Maximum V_BUSSlope above 5.5 V when Boost or Charger are Active

4

V/s

Human Body Model per JESD22-A114

Charged Device Model per JESD22-C101

2000

500

Electrostatic Discharge

Protection Level

ESD

V

T_J

T_STG

T_L

Junction Temperature

Storage Temperature

–40

–65

+150

+260

°C

Lead Soldering Temperature, 10 Seconds

Note:

4. Lesser of 6.5 V or V_I+ 0.3 V.

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating

conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend

exceeding them or designing to absolute maximum ratings.

Symbol

Parameter

Min.

Max.

6

Unit

V

V_BUS

Supply Voltage

4

V_BAT(MAX)Maximum Battery Voltage when Boost enabled

4.5

4

V

T_A< 60°C

T_A> 60°C

dV_BUS

dt

Negative VBUS Slew Rate during VBUS Short Circuit,

_MID< 4.7 µF (see VBUS Short While Charging)



V/s

C

2

T_A

T_J

Ambient Temperature

Junction Temperature (see Thermal Regulation and Protection section)

–30

+85

+120

°C

Thermal Properties

Junction-to-ambient thermal resistance is a function of application and board layout. This data is measured with four-layer

2s2p boards in accordance to JEDEC standard JESD51. Special attention must be paid not to exceed junction temperature

T

_J(max)at a given ambient temperature T_A. For measured data, see Table 11.

Symbol Parameter

Typical

60

Unit

°C/W

Junction-to-Ambient Thermal Resistance

Junction-to-PCB Thermal Resistance

_JA

_JB

20

FAN5401X Family • Rev. 1.0.4

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5

Electrical Specifications

Unless otherwise specified: according to the circuit of Figure 1; recommended operating temperature range for T_Jand T_A;

V_BUS=5.0 V; HZ_MODE; OPA_MODE=0; (Charge Mode); SCL, SDA, OTG=0 or 1.8 V; and typical values are for T_J=25°C.

Symbol

Parameter

Conditions

Min. Typ. Max. Unit

Power Supplies

V_BUS> V_BUS(min), PWM Switching

10

mA

V_BUS> V_BUS(min); PWM Enabled,

Not Switching (Battery OVP

Condition); I_IN Setting=100mA

2.5

I_VBUS

VBUS Current

0°C < T_J< 85°C, HZ_MODE=1

63

90

5.0

20

10

A

V

_BAT< V_LOWV, 32S Mode

0°C < T_J< 85°C, HZ_MODE=1,

_BAT=4.2 V, V_BUS=0 V

0°C < T_J< 85°C, HZ_MODE=1,

_BAT=4.2 V

I_LKG

VBAT to VBUS Leakage Current

0.2

V

Battery Discharge Current in High-

Impedance Mode

I_BAT

A

FAN54013-14, DISABLE=1,

0°C < T_J< 85°C, V_BAT=4.2 V

Charger Voltage Regulation

Charge Voltage Range

3.5

–0.5%

–1%

4.4

V_OREG

T_A=25°C

+0.5%

+1%

V

Charge Voltage Accuracy

Charging Current Regulation

Output Charge Current Range

T_J=0 to 125°C

V_LOWV< V_BAT< V_OREG

550

1450

mA

%

R_SENSE=68m

FAN54010-12

FAN54013-14

FAN54010-12

FAN54013-14

95

92

97

94

100

97

105

102

103

100

20 mV < V_IREG

40 mV

<

I_OCHRG

Charge Current Accuracy Across

R_SENSE

100

97

V_IREG> 40 mV

Rising Voltage

Weak Battery Detection

Weak Battery Threshold Range

3.4

–5

3.7

+5

V

%

V_LOWV

Weak Battery Threshold Accuracy

Weak Battery Deglitch Time

30

ms

Logic Levels: DISABLE, SDA, SCL, OTG

V_IH

V_IL

I_IN

High-Level Input Voltage

Low-Level Input Voltage

Input Bias Current

1.05

V

0.4

Input Tied to GND or V_IN

0.01

1.00

A

Charge Termination Detection

Termination Current Range

50

–25

–5

400

+25

+5

mA

%

V_BAT> V_OREG– V_RCH, R_SENSE=68 m

[V_CSIN– V_BAT] from 3 mV to 20 mV

[V_CSIN– V_BAT] from 20 mV to 40 mV

2 mV Overdrive

I_(TERM)

Termination Current Accuracy

Termination Current Deglitch Time

30

ms

1.8V Linear Regulator

V_REG

1.8 V Regulator Output

I_REGfrom 0 to 2 mA, FAN54013-14

1.7

1.8

1.9

V

Continued on the following page…

FAN5401X Family • Rev. 1.0.4

www.fairchildsemi.com

6

Electrical Specifications

Unless otherwise specified: according to the circuit of Figure 1; recommended operating temperature range for T_Jand T_A;

V_BUS=5.0 V; HZ_MODE; OPA_MODE=0; (Charge Mode); SCL, SDA, OTG=0 or 1.8 V; and typical values are for T_J=25°C.

Symbol

Parameter

Conditions

Min. Typ. Max. Unit

Input Power Source Detection

V_IN(MIN)1VBUS Input Voltage Rising

V_IN(MIN)2Minimum VBUS During Charge

To Initiate and Pass VBUS Validation

During Charging

4.29

3.71

30

4.42

3.94

V

t_{VBUS_VALID}VBUS Validation Time

ms

Special Charger (V_BUS) (FAN54013, FAN54014)

–3

+3

%

V_SP

Special Charger Setpoint Accuracy

Input Current Limit

I_INSet to 100 mA

I_INSet to 500 mA

88

93

98

I_INLIM

Input Current Limit Threshold

mA

450

475

500

V_REFBias Generator

Bias Regulator Voltage

Short-Circuit Current Limit

V

_BUS> V_IN(MIN)or V_BAT> V_BAT(MIN)

6.5

V

V_REF

20

mA

Battery Recharge Threshold

Recharge Threshold

Below V_(OREG)

100

120

130

150

mV

V_RCH

Deglitch Time

V_BATFalling Below V_RCHThreshold

ms

STAT Output

V_STAT(OL)

I_STAT(OH)

STAT Output Low

I_STAT=10 mA

V_STAT=5 V

0.4

V

STAT High Leakage Current

1

A

Battery Detection

Battery Detection Current before

I_DETECT

t_DETECT

–0.80

262

mA

ms

Charge Done (Sink Current)⁽⁵⁾

Battery Detection Time

Begins after Termination Detected

and V_BAT< V_OREG–V_RCH

Sleep Comparator

Sleep-Mode Entry Threshold,

_BUS– V_BAT

V_SLP

2.3 V < V_BAT< V_OREG, V_BUSFalling

Rising Voltage

0

0.04

30

0.10

V

Deglitch Time for VBUS Rising

Above V_BATby V_SLP

t_{SLP_EXIT}

ms

Power Switches (see Figure 3)

Q3 On Resistance (VBUS to PMID) I_IN(LIMIT)=500 mA

180

130

150

250

225

R_DS(ON)

Q1 On Resistance (PMID to SW)

Q2 On Resistance (SW to GND)

mΩ

Charger PWM Modulator

f_SW

Oscillator Frequency

2.7

3.0

3.3

MHz

%

D_MAX

D_MIN

Maximum Duty Cycle

Minimum Duty Cycle

100

0

%

Synchronous to Non-Synchronous

Current Cut-Off Threshold⁽⁶⁾

Low-Side MOSFET (Q2) Cycle-by-

Cycle Current Limit

I_SYNC

140

mA

Continued on the following page…

FAN5401X Family • Rev. 1.0.4

www.fairchildsemi.com

7

Electrical Specifications

Unless otherwise specified: according to the circuit of Figure 1; recommended operating temperature range for T_Jand T_A;

V_BUS=5.0 V; HZ_MODE; OPA_MODE=0; (Charge Mode); SCL, SDA, OTG=0 or 1.8 V; and typical values are for T_J=25°C.

Symbol

Parameter

Conditions

Min. Typ. Max. Unit

Boost Mode Operation (OPA_MODE=1, HZ_MODE=0)

2.5 V < V_BAT< 4.5 V, I_LOADfrom 0 to

200 mA

4.80

4.77

5.07

5.17

V_BOOST

Boost Output Voltage at VBUS

V

3.0 V < V_BAT< 4.5 V, I_LOADfrom 0 to

500 mA

I_BAT(BOOST)Boost Mode Quiescent Current

PFM Mode, V_BAT=3.6 V, I_OUT=0

140

1590

2.42

2.58

300

A

I_LIMPK(BST)

Q2 Peak Current Limit

1272

1908

mA

While Boost Active

Minimum Battery Voltage for Boost

Operation

UVLO_BST

V

To Start Boost Regulator

2.70

6.49

VBUS Load Resistance

Normal Operation

Charger Validation

1500

100

K

R_VBUS

VBUS to PGND Resistance



Protection and Timers

VBUS Over-Voltage Shutdown

V

_BUSRising

6.09

6.29

100

V

VBUS_OVP

I_LIMPK(CHG)

V_SHORT

I_SHORT

Hysteresis

V_BUSFalling

mV

Q1 Cycle-by-Cycle Peak Current

Limit

Charge Mode

2.3

A

Battery Short-Circuit Threshold

Hysteresis

V_BATRising

1.95

20

2.00

100

30

2.05

40

V

V_BATFalling

mV

mA

Linear Charging Current

Thermal Shutdown Threshold⁽⁷⁾

Hysteresis⁽⁷⁾

V_BAT< V_SHORT

T_JRising

145

10

T_SHUTDWN

°C

T_JFalling

T_CF

t_INT

Thermal Regulation Threshold⁽⁷⁾

Charge Current Reduction Begins

120

2.1

°C

s

Detection Interval

Charger Enabled

20.5

18.0

12.0

–25

25.2

13.5

28.0

34.0

15.0

25

t_32S

32-Second Timer⁽⁸⁾

s

Charger Disabled

t_15MIN

15-Minute Timer

15-Minute Mode (FAN54013-14)

Charger Inactive

min

%

∆t_LF

Low-Frequency Timer Accuracy

Notes:

5. Negative current is current flowing from the battery to VBUS (discharging the battery).

6. Q2 always turns on for 60 ns, then turns off if current is below I_SYNC

.

7. Guaranteed by design; not tested in production.

8. This tolerance (%) applies to all timers on the IC, including soft-start and deglitching timers.

www.fairchildsemi.com

FAN5401X Family • Rev. 1.0.4

8

I²C Timing Specifications

Guaranteed by design.

Symbol

Parameter

Conditions

Min. Typ. Max. Unit

Standard Mode

Fast Mode

100

400

kHz

f_SCL

SCL Clock Frequency

High-Speed Mode, C_B< 100 pF

High-Speed Mode, C_B< 400 pF

Standard Mode

3400

1700

4.7

Bus-Free Time between STOP

and START Conditions

t_BUF

s

Fast Mode

1.3

Standard Mode

4

s

ns

s

ns

s

ns

s

ns

START or Repeated START

Hold Time

t_HD;STA

Fast Mode

600

160

4.7

1.3

160

320

4

High-Speed Mode

Standard Mode

Fast Mode

t_LOW

SCL LOW Period

SCL HIGH Period

High-Speed Mode, C_B< 100 pF

High-Speed Mode, C_B< 400 pF

Standard Mode

Fast Mode

600

60

t_HIGH

High-Speed Mode, C_B< 100 pF

High-Speed Mode, C_B< 400 pF

Standard Mode

120

4.7

600

160

250

100

10

t_SU;STA

Repeated START Setup Time

Data Setup Time

Fast Mode

High-Speed Mode

Standard Mode

t_SU;DAT

Fast Mode

ns

High-Speed Mode

Standard Mode

0

3.45

900

70

s

ns

Fast Mode

t_HD;DAT

Data Hold Time

SCL Rise Time

SCL Fall Time

High-Speed Mode, C_B< 100 pF

High-Speed Mode, C_B< 400 pF

Standard Mode

150

1000

300

80

20+0.1C_B

10

Fast Mode

t_RCL

ns

High-Speed Mode, C_B< 100 pF

High-Speed Mode, C_B< 400 pF

Standard Mode

20

160

300

40

20+0.1C_B

10

Fast Mode

t_FCL

High-Speed Mode, C_B< 100 pF

High-Speed Mode, C_B< 400 pF

Standard Mode

20

80

20+0.1C_B

10

1000

300

80

SDA Rise Time

Fast Mode

t_RDA

t_RCL1

Rise Time of SCL after a

Repeated START Condition

and after ACK Bit

High-Speed Mode, C_B< 100 pF

High-Speed Mode, C_B< 400 pF

20

160

Continued on the following page…

FAN5401X Family • Rev. 1.0.4

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9

I²C Timing Specifications

Guaranteed by design.

Symbol

Parameter

Conditions

Min. Typ. Max. Unit

Standard Mode

Fast Mode

20+0.1C_B

300

80

20+0.1C_B

t_FDA

SDA Fall Time

ns

High-Speed Mode, C_B< 100 pF

High-Speed Mode, C_B< 400 pF

Standard Mode

10

20

160

4

s

ns

pF

t_SU;STO

Stop Condition Setup Time

Fast Mode

600

160

High-Speed Mode

C_B

Capacitive Load for SDA, SCL

400

Timing Diagrams

t_F

t_SU;STA

t_BUF

SDA

t_R

T_SU;DAT

t_HD;STO

t_HIGH

t_HD;DAT

SCL

t_LOW

t_HD;STA

REPEATED

START

STOP

START

Figure 5. I²C Interface Timing for Fast and Slow Modes

REPEATED

START

STOP

t_FDA

t_RDA

t_SU;DAT

SDAH

t_SU;STA

t_RCL1

t_FCL

t_HIGH

t_HD;DAT

note A

t_RCL

t_SU;STO

SCLH

t_LOW

t_HD;STA

REPEATED

START

= MCS Current Source Pull-up

= R_PResistor Pull-up

Note A: First rising edge of SCLH after Repeated Start and after each ACK bit.

Figure 6. I²C Interface Timing for High-Speed Mode

FAN5401X Family • Rev. 1.0.4

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10

Charge Mode Typical Characteristics

Unless otherwise specified, circuit of Figure 1, V_OREG=4.2 V, V_BUS=5.0 V, and T_A=25°C.

180

160

140

120

100

80

900

800

700

600

500

400

300

200

100

-

60

40

5.5VBUS

5.0VBUS

4.5VBUS

5.5VBUS

5.0VBUS

4.5VBUS

20

-

2.5

3

3.5

4

4.5

2.5

3

3.5

4

4.5

Battery Voltage, VBAT (V)

Figure 7. Battery Charge Current vs. V_BUSwith

I_INLIM=100 mA

Figure 8. Battery Charge Current vs. V_BUSwith

I_INLIM=500 mA

97%

94%

92%

90%

88%

4.20VBAT, 4.5VBUS

4.20VBAT, 5.0VBUS

3.54VBAT, 5.0VBUS

3.54VBAT, 4.5VBUS

94%

91%

88%

85%

82%

4.5VBUS

86%

5.0VBUS

5.5VBUS

84%

2.5

2.7

2.9

3.1

3.3

3.5

3.7

3.9

4.1

4.3

100

300

500

700

900

1100

1300

1500

Battery Voltage, VBAT (V)

Battery Charge Current (mA)

Figure 9. Charger Efficiency, No I_INLIM, I_OCHARGE=1,450 mA

Figure 10. Charger Efficiency vs. V_BUS, I_INLIM=500 mA

Figure 11. Auto-Charge Startup at V_BUSPlug-in,

I_INLIM=100 mA, OTG=1, V_BAT=3.4 V

Figure 12. Auto-Charge Startup at V_BUSPlug-in,

I_INLIM=500 mA, OTG=1, V_BAT=3.4 V

FAN5401X Family • Rev. 1.0.4

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11

Charge Mode Typical Characteristics

Unless otherwise specified, circuit of Figure 1, V_OREG=4.2 V, V_BUS=5.0 V, and T_A=25°C.

Figure 13. AutoCharge Startup with 300 mA Limited

Charger / Adaptor, I_INLIM=500 mA, OTG=1, V_BAT=3.4 V

Figure 14. Charger Startup with HZ_MODE Bit Reset,

I_INLIM=500 mA, I_OCHARGE=1,050 mA, OREG=4.2 V, V_BAT=3.6 V

Figure 15. Battery Removal / Insertion During Charging, Figure 16. Battery Removal / Insertion During Charging,

V_BAT=3.9 V, I_OCHARGE=1,050 mA, No I_INLIM,TE=0

V_BAT=3.9 V, I_OCHARGE=1,050 mA, No I_INLIM,TE=1

FAN5401X Family • Rev. 1.0.4

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12

Charge Mode Typical Characteristics

Unless otherwise specified, circuit of Figure 1, V_OREG=4.2 V, V_BUS=5.0 V, and T_A=25°C.

Figure 17. No Battery at V_BUSPower-up; FAN54010,

Figure 18. No Battery at V_BUSPower-up; FAN54012

FAN54013

1.82

1.81

1.80

1.79

1.78

1.77

200

150

100

50

-30C

+25C

+85C

-10C, 5.0VBUS

+25C, 5.0VBUS

+85C, 5.0VBUS

0

4.0

4.5

5.0

5.5

6.0

0

1

2

3

4

5

1.8V Regulator Load Current (mA)

Input Voltage, VBUS (V)

Figure 19. VBUS Current in High-Impedance Mode

with Battery Open

Figure 20. V_REG1.8 V Output Regulation

FAN5401X Family • Rev. 1.0.4

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13

Boost Mode Typical Characteristics

Unless otherwise specified, using circuit of Figure 1, V_BAT=3.6 V, T_A=25°C.

100

95

90

85

80

75

100

95

90

85

80

75

3.0 VBAT

3.6 VBAT

4.2 VBAT

-10C, 3.6VBAT

+25C, 3.6VBAT

+85C, 3.6VBAT

0

100

200

300

400

500

0

100

200

300

400

500

V

BUS Load Current (mA)

V

BUS Load Current (mA)

Figure 21. Efficiency vs. V_BAT

Figure 22. Efficiency Over Temperature

5.10

5.05

5.00

4.95

4.90

4.85

4.80

5.10

5.05

5.00

4.95

4.90

4.85

4.80

3.0 VBAT

3.6 VBAT

4.2 VBAT

-10C, 3.6VBAT

+25C, 3.6VBAT

+85C, 3.6VBAT

0

100

200

300

400

500

0

100

200

300

400

500

V

BUS Load Current (mA)

V

BUS Load Current (mA)

Figure 23. Output Regulation vs. V_BAT

Figure 24. Output Regulation Over Temperature

250

200

150

100

50

20

-30C

+25C

+85C

15

10

-30C

5

+25C

+85C

0

2

2.5

3

3.5

4

4.5

5

2

2.5

3

3.5

4

4.5

5

Battery Voltage, VBAT (V)

Figure 25. Quiescent Current

Figure 26. High-Impedance Mode Battery Current

FAN5401X Family • Rev. 1.0.4

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14

Boost Mode Typical Characteristics

Unless otherwise specified, using circuit of Figure 1, V_BAT=3.6 V, T_A=25°C.

Figure 27. Boost PWM Waveform

Figure 28. Boost PFM Waveform

30

25

20

15

10

5

30

25

20

15

10

5

2.7 VBAT

3.6 VBAT

4.2 VBAT

4.5 VBAT

-30C, 3.6VBAT

+25C, 3.6VBAT

+85C, 3.6VBAT

0

100

200

300

400

500

0

100

200

300

400

500

V

BUS Load Current (mA)

V

BUS Load Current (mA)

Figure 29. Output Ripple vs. V_BAT

Figure 30. Output Ripple vs. Temperature

FAN5401X Family • Rev. 1.0.4

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15

Boost Mode Typical Characteristics

Unless otherwise specified, using circuit of Figure 1, V_BAT=3.6 V, T_A=25°C.

Figure 32. V_BUSFault Response, 3.6 V_BAT

Figure 31. Startup, 3.6 V_BAT, 44  Load, Additional 10 µF,

X5R Across V_BUS

Figure 33. Load Transient, 5-155-5 mA, t_R=t_F=100 ns

Figure 34. Load Transient, 5-255-5 mA, t_R=t_F=100 ns

FAN5401X Family • Rev. 1.0.4

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16

Circuit Description / Overview

When charging batteries with a current-limited input source,

such as USB, a switching charger’s high efficiency over a

wide range of output voltages minimizes charging time.

The FAN5401X is designed to work with a current-limited

input source at VBUS. During the current regulation phase of

charging, I_INLIMor the programmed charging current limits the

amount of current available to charge the battery and power

the system. The effect of I_INLIMon I_CHARGEcan be seen in

Figure 36.

FAN5401X combines a highly integrated synchronous buck

regulator for charging with a synchronous boost regulator,

which can supply 5 V to USB On-The-Go (OTG) peripherals.

The regulator employs synchronous rectification for both the

charger and boost regulators to maintain high efficiency over

a wide range of battery voltages and charge states.

V_OREG

I_CHARGE

I_OCHARGE

The FAN5401X has three operating modes:

1. Charge Mode:

Charges a single-cell Li-ion or Li-polymer battery.

I_TERM

V_SHORT

2. Boost Mode:

Provides 5 V power to USB-OTG with an integrated

synchronous rectification boost regulator using the

battery as input.

I_SHORT

3. High-Impedance Mode:

PRE-

CHARGE

CURRENT REGULATION

VOLTAGE

REGULATION

Both the boost and charging circuits are OFF in this

mode. Current flow from VBUS to the battery or from the

battery to VBUS is blocked in this mode. This mode

consumes very little current from VBUS or the battery.

Figure 35. Charge Curve, I_CHARGENot Limited by I_INLIM

V

Note: Default settings are denoted by bold typeface.

OREG

Charge Mode

In Charge Mode, FAN5401X employs four regulation loops:

1. Input Current: Limits the amount of current drawn from

VBUS. This current is sensed internally and can be

programmed through the I²C interface.

I_TERM

V

SHORT

2. Charging Current: Limits the maximum charging current.

This current is sensed using an external R_SENSEresistor.

I_SHORT

3. Charge Voltage: The regulator is restricted from

exceeding this voltage. As the internal battery voltage

rises, the battery’s internal impedance and R_SENSEwork

in conjunction with the charge voltage regulation to

decrease the amount of current flowing to the battery.

Battery charging is completed when the voltage across

R_SENSEdrops below the I_TERMthreshold.

PRE-

CHARGE

CURRENT REGULATION

VOLTAGE

REGULATION

Figure 36. Charge Curve, I_INLIMLimits I_CHARGE

Assuming that V_OREGis programmed to the cell’s fully

charged “float” voltage, the current that the battery accepts

with the PWM regulator limiting its output (sensed at VBAT)

to V_OREGdeclines, and the charger enters the voltage

regulation phase of charging. When the current declines to

the programmed I_TERMvalue, the charge cycle is complete.

Charge current termination can be disabled by resetting the

TE bit (REG1[3]).

4. Temperature: If the IC’s junction temperature reaches

120°C, charge current is reduced until the IC’s

temperature stabilizes at 120°C.

5. An additional loop limits the amount of drop on VBUS to

a programmable voltage (V_SP) to accommodate “special

chargers” that limit current to a lower current than might

be available from a “normal” USB wall charger.

The charger output or “float” voltage can be programmed by

the OREG bits from 3.5 V to 4.44 V in 20 mV increments, as

shown in Table 3.

Battery Charging Curve

If the battery voltage is below V_SHORT, a linear current source

pre-charges the battery until V_BATreaches V_SHORT. The PWM

charging circuit is then started and the battery is charged

with a constant current if sufficient input power is available.

The current slew rate is limited to prevent overshoot.

FAN5401X Family • Rev. 1.0.4

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17

A new charge cycle begins when one of the following occurs:

Table 3. OREG Bits (OREG[7:2]) vs. Charger V_OUT

(V_OREG) Float Voltage

.

The battery voltage falls below V_OREG- V_RCH

Decimal Hex VOREG

VBUS Power on Reset (POR) clears and the battery

voltage is below the weak battery threshold (V_LOWV).

This occurs for all versions except the FAN54011.

0

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

10

11

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

3.50

3.52

3.54

3.56

3.58

3.60

3.62

3.64

3.66

3.68

3.70

3.72

3.74

3.76

3.78

3.80

3.82

3.84

3.86

3.88

3.90

3.92

3.94

3.96

3.98

4.00

4.02

4.04

4.06

4.08

4.10

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

20

21

22

23

24

25

26

27

28

29

2A

2B

2C

2D

2E

2F

30

31

32

33

34

35

36

37

38

39

3A

3B

3C

3D

3E

4.14

4.16

4.18

4.20

4.22

4.24

4.26

4.28

4.30

4.32

4.34

4.36

4.38

4.40

4.42

4.44

1

.

CE or HZ_MODE is reset through I²C write to

CONTROL1 (R1) register.

2

3

4

Charge Current Limit (I_OCHARGE

)

5

Table 5. I_OCHARGE(REG4 [6:4]) Current as Function

of I_OCHARGEBits and R_SENSEResistor Values

6

7

I

_OCHARGE(mA)

V_RSENSE

(mV)

DEC

BIN

HEX

8

68m 100m

9

0

1

2

3

4

5

6

7

000

001

010

011

100

101

110

111

00

01

02

03

04

05

06

07

37.4

44.2

51.0

57.8

71.4

78.2

91.8

98.6

550

650

374

442

510

578

714

782

918

986

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

750

850

1050

1150

1350

1450

Termination Current Limit

Current charge termination is enabled when TE (REG1[3])=1.

Typical termination current values are given in Table 6.

Table 6. I_TERMCurrent as Function of I_TERMBits

(REG4[2:0]) and R_SENSEResistor Values

FAN54010-FAN54012 FAN54013-FAN54014

I_TERM(mA)

V_RSENSE

(mV)

V_RSENSE

(mV)

I_TERM

68 m 100 m

0

1

2

3

4

5

6

7

3.4

50

34

3.3

6.6

49

33

66

6.8

100

150

200

250

300

350

400

68

97

10.2

13.6

17.0

20.4

23.8

27.2

102

136

170

204

238

272

9.9

146

194

243

291

340

388

99

13.2

16.5

19.8

23.1

26.4

132

165

198

231

264

The following charging parameters can be programmed by

the host through I²C:

Table 4. Programmable Charging Parameters

Parameter

Output Voltage Regulation

Battery Charging Current Limit

Input Current Limit

Name

V_OREG

I_OCHRG

I_INLIM

Register

REG2[7:2]

REG4[6:4]

REG1[7:6]

REG4[2:0]

REG1[5:4]

When the charge current falls below I_TERM, PWM charging

stops and the STAT bits change to READY (00) for about

500 ms while the IC determines whether the battery and

charging source are still connected. STAT then changes to

CHARGE DONE (10), provided the battery and charger are

still connected.

Charge Termination Limit

Weak Battery Voltage

I_TERM

V_LOWV

FAN5401X Family • Rev. 1.0.4

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18

PWM Controller in Charge Mode

USB-Friendly Boot Sequence

The IC uses a current-mode PWM controller to regulate the

output voltage and battery charge currents. The synchronous

rectifier (Q2) has a negative current limit that turns off Q2 at

140 mA to prevent current flow from the battery.

For FAN54010/12/13, NOT FAN54011/14

At VBUS POR, when the battery voltage is above the weak

battery threshold (V_LOWV), the IC operates in accordance with

its I²C register settings. If V_BAT< V_LOWV, the IC sets all

registers to their default values and enables the charger

using an input current limit controlled by the OTG pin

(100 mA if OTG is LOW and 500 mA if OTG is HIGH). This

feature can revive a battery whose voltage is too low to

ensure reliable host operation. Charging continues in the

absence of host communication even after the battery has

reached V_OREG, whose default value is 3.54 V, and the

charger remains active until t_15MINtimes out. Once the host

processor begins writing to the IC, charging parameters are

set by the host, which must continually reset the t_32Stimer to

continue charging using the programmed charging

parameters. If t_32S.times out, the register defaults are loaded,

the FAULT bits are set to 110, STAT is pulsed HIGH, and

charging continues with default charge parameters.

Safety Timer

Section references Figure 41 and Figure 42.

At the beginning of charging, the IC starts a 15-minute timer

(t_15MIN). When this timer times out, charging is terminated.

Writing to any register through I²C stops and resets the t_15MIN

timer, which in turn starts a 32-second timer (t_32S). Setting

the TMR_RST bit (REG0[7]) resets the t_32Stimer. If the t_32S

timer times out, charging is terminated, the registers are set

to their default values, and charging resumes using the

default values with the t_15MINtimer running.

Normal charging is controlled by the host with the t_32Stimer

running to ensure that the host is alive. Charging with the

t_15MINtimer running is used for charging that is unattended by

the host. If the t_15MINtimer expires, the IC turns off the

The FAN54011 and FAN54014 do not automatically initiate

charging at VBUS POR. Instead, they wait for the host to

initiate charging through I²C commands.

charger, sets the

bit, and indicates a timer fault (110) on

CE

the FAULT bits (REG0[2:0]). This sequence prevents

overcharge if the host fails to reset the t_32Stimer.

Input Current Limiting

V_BUSPOR / Non-Compliant Charger Rejection

To minimize charging time without overloading VBUS current

limitations, the IC’s input current limit can be programmed by

the I_INLIMbits (REG1[7:6]).

When the IC detects that V_BUShas risen above V_IN(MIN)1

(4.4 V), the IC applies a 100 load from VBUS to GND. To

clear the VBUS POR (Power-On-Reset) and begin charging,

VBUS must remain above V_IN(MIN)1and below VBUS_OVPfor

t_{VBUS_VALID}(30 ms) before the IC initiates charging. The

VBUS validation sequence always occurs before charging is

initiated or re-initiated (for example, after a VBUS OVP fault

or a V_RCHrecharge initiation).

Table 7. Input Current Limit

I

_INLIMREG1[7:6]

Input Current Limit

100 mA

00

01

10

11

500 mA

800 mA

t_{VBUS_VALID}ensures that unfiltered 50/60 Hz chargers and

other non-compliant chargers are rejected.

No limit

For all versions except the FAN54011/14, the OTG pin

establishes the input current limit when t_15MINis running. For

the FAN54011 and FAN54014, no charging occurs

automatically at VBUS POR; the input current limit is

established by the I_INLIMbits.

FAN5401X Family • Rev. 1.0.4

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19

Flow Charts

Figure 37. Charger VBUS POR

FAN5401X Family • Rev. 1.0.4

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20

Flow Charts (Continued)

Figure 38. Charge Mode

FAN5401X Family • Rev. 1.0.4

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21

Flow Charts (Continued)

Charge

Configuration

State

T32Sec

ARMED AND

CCEE# = 0?

YES

Charge State

NO

Has T15Min

and CCEE# = 0

START T15Min

NO

YES

VBAT < VOREG

for 262ms?

NO

YES

Figure 39. Charge Configuration

Figure 40. HZ-State

FAN5401X Family • Rev. 1.0.4

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22

Flow Charts (Continued)

Charge Start

Start T_15MIN

Reset Registers

YES

T_32SEC

NO

Expired?

Start T_32SEC

Stop T_15MIN

YES

NO

T_15MIN

Active?

I²C Write

received?

T_15MIN

Continue

Charging

YES

NO

Expired?

Timer Fault :

Set CE

YES

CE

Figure 41. Timer Flow Chart for FAN54010, FAN54012, FAN54013

Charge Start

from Host control

Timer Fault

Stop Charging and

Reset Registers

T_32SEC

Reset T_32SEC

Charge

NO

YES

Expired?

NO

TMR_RST

bit Set?

YES

Figure 42. Timer Flow Chart for FAN54011 and FAN54014

FAN5401X Family • Rev. 1.0.4

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23

Table 9. I_SAFE(I_OCHARGELimit) as Function of ISAFE

Bits (REG6[6:4])

Special Charger

FAN54013, FAN54014 Only

The FAN54013 and FAN54014 have additional functionality

to limit input current in case a current-limited “special

charger” is supplying VBUS. These slowly increase the

charging current until either:

ISAFE (REG6[6:4])

I_SAFE(mA)

DEC BIN HEX V_RSENSE(mV)

68 m 100 m

.

I_INLIMor I_OCHARGEis reached

0

1

2

3

4

5

6

7

000

001

010

011

100

101

110

111

00

01

02

03

04

05

06

07

37.4

44.2

51.0

57.8

71.4

78.2

91.8

98.6

550

650

374

442

510

578

714

782

918

986

or

.

V_BUS=V_SP.

750

If V_BUScollapses to V_SPwhen the current is ramping up, the

FAN54013 and FAN54014 charge with an input current that

keeps V_BUS=V_SP. When the V_SPcontrol loop is limiting the

charge current, the SP bit (REG5[4]) is set.

850

1050

1150

1350

1450

Table 8. V_SPas Function of SP Bits (REG5[2:0])

SP (REG5[2:0])

DEC

BIN

000

001

010

011

100

101

110

111

HEX

00

V_SP

Table 10. V_SAFE(V_OREGLimit) as Function of VSAFE

Bits (REG6[3:0])

0

1

2

3

4

5

6

7

4.213

4.293

4.373

4.453

4.533

4.613

4.693

4.773

01

VSAFE (REG6[3:0])

02

Max. OREG

(REG2[7:2])

VOREG

Max.

DEC

BIN

HEX

03

04

0

1

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

100011

100100

100101

100110

100111

101000

101001

101010

101011

101100

101101

101110

101111

110000

110001

110010

4.20

4.22

4.24

4.26

4.28

4.30

4.32

4.34

4.36

4.38

4.40

4.42

4.44

05

06

2

07

3

4

Safety Settings

FAN54013 and FAN54014 Only

5

6

The FAN54013 and FAN54014 contain a SAFETY register

(REG6) that prevents the values in OREG (REG2[7:2]) and

IOCHARGE (REG4[6:4]) from exceeding the values of the

VSAFE and ISAFE values.

7

8

9

After V_BATexceeds V_SHORT, the SAFETY register is loaded

with its default value and may be written only before any

other register is written. After writing to any other register,

10

11

12

13

14

15

the SAFETY register is locked until V_BATfalls below V_SHORT

.

The ISAFE (REG6[6:4]) and VSAFE (REG6[3:0]) registers

establish values that limit the maximum values of I_OCHARGE

and V_OREGused by the control logic. If the host attempts to

write a value higher than VSAFE or ISAFE to OREG or

IOCHARGE, respectively; the VSAFE, ISAFE value appears

as the OREG, IOCHARGE register value, respectively.

Thermal Regulation and Protection

When the IC’s junction temperature reaches T_CF(about

120°C), the charger reduces its output current to 550 mA to

prevent overheating. If the temperature increases beyond

T_SHUTDOWN; charging is suspended, the FAULT bits are set

to 101, and STAT is pulsed HIGH. In Suspend Mode, all

timers stop and the state of the IC’s logic is preserved.

Charging resumes at programmed current after the die

cools to about 120°C.

FAN5401X Family • Rev. 1.0.4

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24

Battery Detection During Charging

Additional _JAdata points, measured using the FAN5401X

evaluation board, are given in Table 11 (measured with

T_A=25°C). Note that as power dissipation increases, the

effective _JAdecreases due to the larger difference between

the die temperature and its ambient.

The IC can detect the presence, absence, or removal of a

battery if the termination bit (TE) is set. During normal

charging, once V_BATis close to V_OREGand the termination

charge current is detected, the IC terminates charging and

sets the STAT bits to 10. It then turns on a discharge current,

I_DETECT, for t_DETECT. If V_BATis still above V_OREG– V_RCH, the

battery is present and the IC sets the FAULT bits to 000. If

V_BATis below V_OREG– V_RCH, the battery is absent and the IC:

Table 11. FAN5401X Evaluation Board Measured _JA

Power (W)

0.504



_JA

54°C/W

50°C/W

46°C/W

1. Sets the registers to their default values.

2. Sets the FAULT bits to 111.

0.844

1.506

3. Resumes charging with default values after t_INT

.

Battery Short-Circuit Protection

If the battery voltage is below the short-circuit threshold

(V_SHORT); a linear current source, I_SHORT, supplies V_BATuntil

Charge Mode Input Supply Protection

Sleep Mode

When V_BUSfalls below V_BAT+ V_SLP, and V_BUSis above

V_IN(MIN),the IC enters Sleep Mode to prevent the battery from

draining into VBUS. During Sleep Mode, reverse current is

disabled by body switching Q1.

V_BAT> V_SHORT.

Battery Detection During Power-up

For FAN54010 and FAN54013

Input Supply Low-Voltage Detection

The IC continuously monitors VBUS during charging. If V_BUS

falls below V_IN(MIN), the IC:

At VBUS POR, a 5 k load is applied to VBAT for 500 ms to

discharge any residual system capacitance in case the

battery is absent. If V_BAT

< V_SHORT, linear charging

commences. When V_BATrises above V_SHORT, PWM charging

proceeds with the float voltage (OREG) temporarily set to

4 V. If the battery voltage exceeds 3.7 V within 32 ms of the

beginning of PWM charging, the battery is absent. If battery

absent is detected:

1. Terminates charging

2. Pulses the STAT pin, sets the STAT bits to 11, and sets

the FAULT bits to 011.

If V_BUSrecovers above the V_IN(MIN)rising threshold after time

t_INT(about two seconds), the charging process is repeated.

This function prevents the USB power bus from collapsing or

oscillating when the IC is connected to a suspended USB

port or a low-current-capable OTG device.

1. High-Impedance Mode is entered.

2. FAULT bits are set to 111.

3. The t_15MINtimer is disabled until VBUS is removed.

If V_BATremains below 3.7 V during the initial 32 ms period,

the float voltage returns to the OREG register setting and

PWM charging continues.

Input Over-Voltage Detection

When the V_BUSexceeds VBUS_OVP, the IC:

1. Turns off Q3

System Operation with No Battery

2. Suspends charging

3. Sets the FAULT bits to 001, sets the STAT bits to 11,

and pulses the STAT pin.

The FAN54012 continues charging after VBUS POR with the

default parameters, regulating the V_BATline to 3.54 V until

the host processor issues commands or the 15-minute timer

expires. In this way, the FAN54012 can start the system

without a battery.

When V_BUSfalls about 150mV below VBUS_OVP, the fault is

cleared and charging resumes after V_BUSis revalidated (see

VBUS POR / Non-Compliant Charger Rejection).

The FAN5401X soft-start function can interfere with the

system supply with battery absent. The soft-start activates

whenever V_OREG, I_INLIM, or I_OCHARGEare set from a lower to

higher value. During soft-start, the I_INlimit drops to 100 mA

for about 1 ms unless I_INLIMis set to 11 (no limit). This could

cause the system processor to fail to start. To avoid this

behavior, use the following sequence.

VBUS Short While Charging

If VBUS is shorted with a very low impedance while the IC is

charging with I_INLIMIT=100 mA, the IC may not meet

datasheet specifications until power is removed. To trigger

this condition, V_BUSmust be driven from 5 V to GND with a

high slew rate. Achieving this slew rate requires a 0  short

to the USB cable less than 10cm from the connector.

1. Set the OTG pin HIGH. When VBUS is plugged in, I_INLIM

is set to 500mA until the system processor powers up

and can set parameters through I²C.

Charge Mode Battery Detection & Protection

VBAT Over-Voltage Protection

2. Program the Safety Register.

The OREG voltage regulation loop prevents V_BATfrom

overshooting the OREG voltage by more than 50 mV when

the battery is removed. When the PWM charger runs with no

battery, the TE bit is not set and a battery is inserted that is

charged to a voltage higher than V_OREG; PWM pulses stop. If

no further pulses occur for 30 ms, the IC sets the FAULT bits

to 100, sets the STAT bits to 11, and pulses the STAT pin.

3. Set I_INLIMto 11 (no limit).

4. Set OREG to the desired value (typically 4.18).

5. Reset the IOLEVEL bit, then set IOCHARGE.

6. Set I_INLIMto 500mA if a USB source is connected.

FAN5401X Family • Rev. 1.0.4

www.fairchildsemi.com

25

During the initial system startup, while the charger IC is

being programmed, the system current is limited to 325 mA

for 1ms during steps 4 and 5. This is the value of the soft-

start ICHARGE current used when I_INLIMis set to No Limit.

Charge Mode Control Bits

Setting either HZ_MODE or CE through I²C disables the

charger and puts the IC into High-Impedance Mode and

resets t_32S. If V_BAT< V_LOWVwhile in High-Impedance Mode,

t_32Sbegins running and, when it overflows, all registers

(except SAFETY) reset, which enables t_15MINcharging on

versions with the 15-minute timer.

If the system is powered up without a battery present, the

CV bit should be set. When a battery is inserted, the CV bit

is cleared.

When t_15MINoverflows, the IC sets the CE bit and the IC

Charger Status / Fault Status

enters High-Impedance Mode. If CE was set by t_15MIN

overflow, a new charge cycle can only be initiated through

I²C or VBUS POR.

The STAT pin indicates the operating condition of the IC and

provides a fault indicator for interrupt driven systems.

Table 12. STAT Pin Function

Setting the RESET bit clears all registers. If HZ_MODE or

EN_STAT

Charge State

X

STAT Pin

OPEN

CE bits were set when the RESET bit is set, these bits are

also cleared, but the t_32Stimer is not started, and the IC

remains in High-Impedance Mode.

0

X

1

Normal Conditions

Charging

OPEN

LOW

Table 14. FAN54013-14 DISABLE Pin and CE Bit

Functionality

Fault

(Charging or Boost)

128 µs Pulse,

then OPEN

X

Charging

DISABLE Pin

HZ_MODE

CE

The FAULT bits (R0[2:0]) indicate the type of fault in Charge

Mode (see Table 13).

ENABLE

DISABLE

0

X

1

0

1

0

X

1

Table 13. Fault Status Bits During Charge Mode

Fault Bit

X

Fault Description

B2 B1 B0

X

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Normal (No Fault)

VBUS OVP

Raising the DISABLE pin stops t_32Sfrom advancing, but

does not reset it. If the DISABLE pin is raised during t_15MIN

charging, the t_15MINtimer is reset.

Sleep Mode

Operational Mode Control

Poor Input Source

Battery OVP

OPA_MODE (REG1[0]) and the HZ_MODE (REG1[1]) bits in

conjunction with the FAULT state define the operational

mode of the charger.

Thermal Shutdown

Timer Fault

Table 15. Operation Mode Control

HZ_MODE OPA_MODE FAULT Operation Mode

No Battery

0

1

0

X

1

0

1

0

X

Charge

Charge Configure

Boost

X

High Impedance

The IC resets the OPA_MODE bit whenever the boost is

deactivated, whether due to a fault or being disabled by

setting the HZ_MODE bit.

FAN5401X Family • Rev. 1.0.4

www.fairchildsemi.com

26

V_BUSas a function of I_LOADcan be computed when the

regulator is in PWM Mode (continuous conduction) as:

Boost Mode

Boost Mode can be enabled if the IC is in 32-Second Mode

with the OTG pin and OPA_MODE bits as indicated in Table

16. The OTG pin ACTIVE state is 1 if OTG_PL=1 and 0

when OTG_PL=0.

EQ. 1

V

 5.07 R

I

OUT LOAD

OUT

At V_BAT=3.3 V, and I_LOAD=200 mA, V_BUSwould drop to:

EQ. 1A

V

 5.07  0.26 0.2  5.018V

If boost is active using the OTG pin, Boost Mode is initiated

even if the HZ_MODE=1. The HZ_MODE bit overrides the

OPA_MODE bit.

OUT

At V_BAT=2.7 V, and I_LOAD=200 mA, V_BUSwould drop to:

EQ. 1B

Table 16. Enabling Boost

V

 5.07  0.327  0.2  5.005V

OUT

OTG

HZ_

MODE MODE

OPA_

OTG_EN

BOOST

PFM Mode

If V_BUS> VREF_BOOST(nominally 5.07 V) when the minimum

off-time has ended, the regulator enters PFM Mode. Boost

pulses are inhibited until V_BUS< VREF_BOOST. The minimum

on-time is increased to enable the output to pump up

sufficiently with each PFM boost pulse. Therefore the

regulator behaves like a constant on-time regulator, with the

bottom of its output voltage ripple at 5.07 V in PFM Mode.

1

X

0

X

0

X

1

X

1

0

X

1

Enabled

Disabled

ACTIVE

X

ACTIVE

X

1

ACTIVE

Table 17. Boost PWM Operating States

0

Disabled

Mode

LIN

Description

Linear Startup

Boost Soft-Start

Invoked When

V_BAT> V_BUS

To remain in Boost Mode, the TMR_RST must be set by the

host before the t_32Stimer times out. If t_32Stimes out in Boost

Mode; the IC resets all registers, pulses the STAT pin, sets

the FAULT bits to 110, and resets the BOOST bit. VBUS

POR or reading R0 clears the fault condition.

SS

V_BUS< V_BST

V_BAT> UVLO_BSTand

SS Completed

BST

Boost Operating Mode

Boost PWM Control

Startup

The IC uses a minimum on-time and computed minimum off-

time to regulate VBUS. The regulator achieves excellent

transient response by employing current-mode modulation.

This technique causes the regulator to exhibit a load line.

During PWM Mode, the output voltage drops slightly as the

input current rises. With a constant V_BAT, this appears as a

constant output resistance.

When the boost regulator is shut down, current flow is

prevented from V_BATto V_BUS, as well as reverse flow from

V_BUSto V_BAT.

LIN State

When EN rises, if V_BAT> UVLO_BST, the regulator first

attempts to bring PMID within 400mV of V_BATusing an

internal 450 mA current source from VBAT (LIN State). If

PMID has not achieved V_BAT– 400mV after 560 µs, a FAULT

state is initiated.

The “droop” caused by the output resistance when a load is

applied allows the regulator to respond smoothly to load

transients with no undershoot from the load line. This can be

seen in Figure 33 and Figure 43.

SS State

350

325

300

275

250

225

200

When PMID > V_BAT– 400 mV, the boost regulator begins

switching with a reduced peak current limit of about 50% of

its normal current limit. The output slews up until V_BUSis

within 5% of its setpoint; at which time, the regulation loop is

closed and the current limit is set to 100%.

If the output fails to achieve 95% of its setpoint (V_BST) within

128 µs, the current limit is increased to 100%. If the output

fails to achieve 95% of its setpoint after this second 384s

period, a fault state is initiated.

2.0

2.5

3.0

3.5

4.0

4.5

5.0

Battery Voltage, VBAT (V)

Figure 43. Output Resistance (R_OUT

)

FAN5401X Family • Rev. 1.0.4

www.fairchildsemi.com

27

BST State

VREG Pin

This is the normal operating mode of the regulator. The

regulator uses a minimum t_OFF-minimum t_ONmodulation

The VREG pin on FAN54010, FAN54011, and FAN54012

provides a voltage protected from over-voltage surges on

VBUS, which can be used to run auxiliary circuits. This

voltage is essentially a current-limited replica of PMID. The

maximum voltage on this node is 5.9 V.

V

IN

scheme. The minimum t_OFFis proportional to

, which

V

OUT

keeps the regulator’s switching frequency reasonably

constant in CCM. t_ON(MIN)is proportional to V_BATand is a

higher value if the inductor current reached 0 before t_OFF(MIN)

in the prior cycle.

FAN54013 and FAN54014 provide a 1.8 V regulated output

on this pin, which can be disabled through I²C by setting the

DIS_VREG bit (REG5[6]). VREG can supply up to 2 mA.

This circuit, which is powered from PMID, is enabled only

when PMID > V_BATand does not drain current from the

battery. During boost, V_REGis off. It is also off when the

HZ_MODE bit (REG1[1])=1.

To ensure the VBUS does not pump significantly above the

regulation point, the boost switch remains off as long as

FB > V_REF

.

Boost Faults

If a BOOST fault occurs:

Monitor Register (Reg10H)

Additional status monitoring bits enable the host processor

to have more visibility into the status of the IC. The monitor

bits are real-time status indicators and are not internally

debounced or otherwise time qualified.

1. The STAT pin pulses.

2. OPA_MODE bit is reset.

3. The power stage is in High-Impedance Mode.

4. The FAULT bits (REG0[2:0]) are set per Table 18.

The state of the MONITOR register bits listed in High-

Impedance Mode are only valid when V_BUSis valid.

Restart After Boost Faults

If boost was enabled with the OPA_MODE bit and

OTG_EN=0, Boost Mode can only be enabled through

subsequent I²C commands since OPA_MODE is reset on

boost faults. If OTG_EN=1 and the OTG pin is still ACTIVE

(see Table 16), the boost restarts after a 5.2 ms delay, as

shown in Figure 44. If the fault condition persists, restart is

attempted every 5 ms until the fault clears or an I²C

command disables the boost.

Table 18. Fault Bits During Boost Mode

Fault Bit

Fault Description

B2 B1 B0

0

1

Normal (no fault)

V_BUS> VBUS_OVP

V_BUSfails to achieve the voltage required to

advance to the next state during soft-start or

sustained (>50 µs) current limit during the

BST state.

0

1

0

1

0

1

0

1

0

1

V_BAT< UVLO_BST

N/A: This code does not appear.

Thermal shutdown

Timer fault; all registers reset.

N/A: This code does not appear.

0

VBUS

560

5200

450mA

BATTERY

CURRENT

0

64

BOOST

ENABLED

Figure 44. Boost Response Attempting to Start into V_BUS

Short Circuit (Times in µs)

FAN5401X Family • Rev. 1.0.4

www.fairchildsemi.com

28

Table 19. MONITOR Register Bit Definitions

STATE

BIT#

NAME

Active When

0

1

MONITOR

Address 10H

_CSIN– V_BAT< V_ITERM

V_CSIN– V_BAT< 1 mV

_BAT< V_SHORT

V

V_CSIN– V_BAT> V_ITERM

V_CSIN– V_BAT> 1 mV

V_BAT> V_SHORT

Charging with TE=1

Charging with TE=0

Charging

7

ITERM_CMP

VBAT_CMP

V

6

V_BAT< V_LOWV

V_BAT> V_LOWV

High-Impedance Mode

Boosting

V_BAT< UVLO_BST

V_BAT> UVLO_BST

Linear Charging Enabled

T_J> 120°C

5

4

LINCHG

T_120

Linear Charging Not Enabled

T_J< 120°C

Charging

Charging Current Controlled by

Charging Current Not Controlled by

I_CHARGEControl Loop

3

ICHG

Charging

I

_CHARGEControl Loop

2

1

0

IBUS

I_BUSLimiting Charging Current

V_BUSNot Valid

Charge Current Not Limited by I_BUSCharging

VBUS_VALID

CV

V_BUSis Valid

V_BUS> V_BAT

Charging

Constant Current Charging

Constant Voltage Charging

FAN5401X Family • Rev. 1.0.4

www.fairchildsemi.com

29

I²C Interface

The FAN5401X’s serial interface is compatible with

Standard, Fast, Fast Plus, and High-Speed Mode I²C-Bus®

specifications. The SCL line is an input and the SDA line is a

bi-directional open-drain output; it can only pull down the bus

when active. The SDA line only pulls LOW during data reads

and signaling ACK. All data is shifted in MSB (bit 7) first.

A transaction ends with a STOP condition, which is defined

as SDA transitioning from 0 to 1 with SCL HIGH, as shown

in Figure 47.

Slave Releases

Master Drives

t_HD;STO

ACK(0) or

NACK(1)

SDA

SCL

Slave Address

Table 20. I²C Slave Address Byte

Part Types

7 6

5

4

3

2

1

0

FAN54010–FAN54014

1

0

1

0

1

Figure 47. Stop Bit

R/W

During a read from the FAN5401X (Figure 50), the master

issues a Repeated Start after sending the register address

and before resending the slave address. The Repeated Start

is a 1-to-0 transition on SDA while SCL is HIGH, as shown in

Figure 48.

In hex notation, the slave address assumes a 0 LSB. The

hex slave address is D6H the family of parts.

Bus Timing

As shown in Figure 45, data is normally transferred when

SCL is LOW. Data is clocked in on the rising edge of SCL.

Typically, data transitions shortly at or after the falling edge

of SCL to allow ample time for the data to set up before the

next SCL rising edge.

High-Speed (HS) Mode

The protocols for High-Speed (HS), Low-Speed (LS), and

Fast-Speed (FS) Modes are identical except the bus speed

for HS Mode is 3.4 MHz. HS Mode is entered when the bus

master sends the HS master code 00001XXX after a start

condition. The master code is sent in Fast or Fast Plus Mode

(less than 1MHz clock); slaves do not ACK this transmission.

Data change allowed

SDA

T_H

The master then generates a repeated start condition

(Figure 48) that causes all slaves on the bus to switch to HS

Mode. The master then sends I²C packets, as described

above, using the HS Mode clock rate and timing.

T_SU

SCL

Figure 45. Data Transfer Timing

The bus remains in HS Mode until a stop bit (Figure 47) is

sent by the master. While in HS Mode, packets are

separated by repeated start conditions (Figure 48).

Each bus transaction begins and ends with SDA and SCL

HIGH. A transaction begins with a START condition, which is

defined as SDA transitioning from 1 to 0 with SCL HIGH, as

shown in Figure 46.

Slave Releases

t_SU;STA

t_HD;STA

ACK(0) or

NACK(1)

SLADDR

MS Bit

SDA

SCL

T_HD;STA

Slave Address

MS Bit

SDA

SCL

Figure 48. Repeated Start Timing

Figure 46. Start Bit

FAN5401X Family • Rev. 1.0.4

www.fairchildsemi.com

30

Read and Write Transactions

Table 21. Bit Definitions for Figure 49, Figure 50

The figures below outline the sequences for data read and

write. Bus control is signified by the shading of the packet,

Symbol

Definition

Master Drives Bus

Slave Drives Bus

defined as

and

.

S

START, see Figure 46.

All addresses and data are MSB first.

ACK. The slave drives SDA to 0 to acknowledge

the preceding packet.

A

NACK. The slave sends a 1 to NACK the

preceding packet.

R

P

Repeated START, see Figure 48

STOP, see Figure 47

0

7 bits

8 bits

Data

S

Slave Address

0

A

Reg Addr

A

P

Figure 49. Write Transaction

0

1

7 bits

Slave Address

8 bits

7 bits

8 bits

Data

S

0

A

Reg Addr

A

R

Slave Address

1

A

P

Figure 50. Read Transaction

FAN5401X Family • Rev. 1.0.4

www.fairchildsemi.com

31

Register Descriptions

FAN54010-FAN54012 have seven user-accessible registers; FAN54013 and FAN54014 have an additional two registers,

defined in Table 22.

Table 22. I²C Register Address

Register

Address Bits

IC

Name

REG#

7

0

6

0

5

0

4

0

3

0

2

0

1

0

1

0

1

0

CONTROL0

CONTROL1

OREG

0

1

2

ALL

03

or

IC_INFO

0

1

3BH

IBAT

4

5

0

1

0

1

0

1

0

SP_CHARGER

SAFETY

FAN54013 and FAN54014

ALL

6

MONITOR

10H

Table 23. Register Bit Definitions

This table defines the operation of each register bit for all IC versions. Default values are in bold text.

Bit

Name

Value Type

Description

CONTROL0

Register Address: 00

Default Value=X1XX 0XXX

W

Writing a 1 resets the t_32Stimer; writing a 0 has no effect

Returns the OTG pin level (1=HIGH)

TMR_RST

7

1

OTG

R

Prevents STAT pin from going LOW during charging; STAT pin still pulses to

enunciate faults

0

R/W

6

EN_STAT

1

00

01

10

11

0

Enables STAT pin LOW when IC is charging

R

Ready

Charge in progress

5:4

STAT

Charge done

Fault

R

IC is not in Boost Mode

3

BOOST

FAULT

1

IC is in Boost Mode

2:0

R

Fault status bits: for Charge Mode, see Table 13; for Boost Mode, see Table 18

CONTROL1

Register Address: 01

Default Value=0011 0000 (30H)

7:6

I_INLIM

R/W Input current limit, see Table 7

00

01

10

11

0

R/W 3.4 V

3.5 V

5:4

V_LOWV

Weak battery voltage threshold

3.6 V

3.7 V

R/W Disable charge current termination

Enable charge current termination

R/W Charger enabled

Charger disabled

3

2

TE

CE

1

0

1

FAN5401X Family • Rev. 1.0.4

www.fairchildsemi.com

32

Table 23. Register Bit Definitions

This table defines the operation of each register bit for all IC versions. Default values are in bold text.

Bit

Name

Value Type

Description

0

1

0

1

R/W Not High-Impedance Mode

High-Impedance Mode

R/W Charge Mode

1

HZ_MODE

See Table 16

0

OPA_MODE

Boost Mode

OREG

Register Address: 02

Default Value=0000 1010 (0AH)

Charger output “float” voltage; programmable from 3.5 V to 4.44 V in 20 mV

increments; defaults to 000010 (3.54 V), see Table 3

7:2

OREG

R/W

0

1

0

1

R/W OTG pin active LOW

OTG pin active HIGH

R/W Disables OTG pin

Enables OTG pin

1

0

OTG_PL

OTG_EN

IC_INFO

Register Address: 03 or 3B

Default Value=100X X100

7:5

4:2

Vendor Code

100

00

R

Identifies Fairchild Semiconductor as the IC supplier

PN

Part number bits, see the Ordering Info on page 1

1:0

REV

IC Revision, revision 1.X, where X is the decimal of these three bits

IBAT

Register Address: 04

Default Value=1000 1001 (89H)

Writing a 1 resets charge parameters, except the Safety register (Reg6), to their

defaults: writing a 0 has no effect; read returns 1

7

RESET

1

W

6:4

3

IOCHARGE

Reserved

ITERM

Table 5

1

R/W Programs the maximum charge current, see Table 5

Unused

R/W Sets the current used for charging termination, see Table 6

R

2:0

Table 6

SP_CHARGER (FAN54013-14)

Register Address: 05

Default Value=001X X100

7

Reserved

0

1

0

R

Unused

R/W 1.8 V regulator is ON

6

DIS_VREG

1.8 V regulator is OFF

R/W Output current is controlled by IOCHARGE bits

Voltage across R_SENSEfor output current control is set to 22.1 mV (325 mAfor

5

4

IO_LEVEL

SP

1

R_SENSE=68 m, 221 mA for 100 m)

0

R

Special charger is not active (V_BUSis able to stay above V_SP)

1

Special charger has been detected and V_BUSis being regulated to V_SP

DISABLE pin is LOW

0

1

3

EN_LEVEL

VSP

DISABLE pin is HIGH

2:0

Table 8

R/W Special charger input regulation voltage, see Table 8

SAFETY (FAN54013-14)

Register Address: 06

Default Value=0100 0000 (40H)

7

Reserved

ISAFE

0

R

Bit disabled and always returns 0 when read back

6:4

3:0

Table 9

R/W Sets the maximum I_OCHARGEvalue used by the control circuit, see Table 9

VSAFE

Table 10 R/W Sets the maximum V_OREGused by the control circuit, see Table 10

Register Address: 10H (16)

See Table 19

MONITOR

7

6

5

ITERM_CMP

R

ITERM comparator output, 1 when VRSENSE > ITERM reference

Output of VBAT comparator

VBAT_CMP Table 19

LINCHG

30 mA linear charger ON

FAN5401X Family • Rev. 1.0.4

www.fairchildsemi.com

33

Table 23. Register Bit Definitions

This table defines the operation of each register bit for all IC versions. Default values are in bold text.

Bit

Name

Value Type

Description

Thermal regulation comparator; when=1 and T_145=0, the charge current is limited

to 22.1 mV across R_SENSE

4

T_120

R

3

2

1

ICHG

IBUS

R

0 indicates the ICHARGE loop is controlling the battery charge current

0 indicates the IBUS (input current) loop is controlling the battery charge current

1 indicates VBUS has passed validation and is capable of charging

VBUS_VALID

1 indicates the constant-voltage loop (OREG) is controlling the charger and all

current limiting loops have released

0

CV

R

PCB Layout Recommendations

Bypass capacitors should be placed as close to the IC as

possible. In particular, the total loop length for CMID should

be minimized to reduce overshoot and ringing on the SW,

PMID, and VBUS pins. All power and ground pins must be

routed to their bypass capacitors, using top copper whenever

possible. Copper area connecting to the IC should be

maximized to improve thermal performance if possible.

Figure 51. PCB Layout Recommendations

FAN5401X Family • Rev. 1.0.4

www.fairchildsemi.com

34

Physical Dimensions

F

BALL A1

E

A

INDEX AREA

1.20

B

Ø0.20

Cu Pad

0.03 C

2X

A1

1.60

D

0.40

Ø0.30 Solder

Mask Opening

0.40

0.03 C

2X

TOP VIEW

RECOMMENDED LAND PATTERN

(NSMD TYPE)

0.06 C

0.625

0.547

0.378±0.018

0.208±0.021

E

0.05 C

C

D

SEATING PLANE

SIDE VIEWS

NOTES:

A. NO JEDEC REGISTRATION APPLIES.

B. DIMENSIONS ARE IN MILLIMETERS.

0.005

C A B

1.20

Ø0.260±0.02

20X

0.40

C. DIMENSIONS AND TOLERANCE

PER ASMEY14.5M, 1994.

E

D

C

B

1.60

D. DATUM C IS DEFINED BY THE SPHERICAL

CROWNS OF THE BALLS.

(Y) ±0.018

F

0.40

A

E. PACKAGE NOMINAL HEIGHT IS 586 MICRONS

±39 MICRONS (547-625 MICRONS).

2

3

4

1

(X) ±0.018

F. FOR DIMENSIONS D, E, X, AND Y SEE

PRODUCT DATASHEET.

BOTTOM VIEW

G. DRAWING FILNAME: MKT-UC020AArev2.

Figure 52. 20-Ball WLCSP, 4X5 Array, 0.4 mm Pitch, 250 µm Ball

Product-Specific Dimensions

Product

D

E

X

Y

FAN5401XUCX

1.960 +0.030

1.870 +0.030

0.335

0.180

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without

notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most

recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty

therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

FAN5401X Family • Rev. 1.0.4

www.fairchildsemi.com

35

FAN5401X Family • Rev. 1.0.4

www.fairchildsemi.com

36


型号：	FAN54010UCX(1)
厂家：	FAIRCHILD SEMICONDUCTOR
描述：	FAN54010 / FAN54011 / FAN54012 / FAN54013 / FAN54014 FAN54010 / FAN54011 / FAN54012 / FAN54013 / FAN54014
文件：	总36页 (文件大小：1235K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

FAN54010UCX(1) [FAIRCHILD]

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