FAN6791 [FAIRCHILD]
Highly Integrated, Dual-PWM Combination Controller; 高度集成的双PWM组合控制器![FAN6791](http://pdffile.icpdf.com/pdf1/p00157/img/icpdf/FAN67_869523_icpdf.jpg)
型号: | FAN6791 |
厂家: | ![]() |
描述: | Highly Integrated, Dual-PWM Combination Controller |
文件: | 总19页 (文件大小:718K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
April 2009
FAN6791 / FAN6793
Highly Integrated, Dual-PWM Combination Controller
Features
Description
The highly integrated FAN6791/3 dual PWM
combination controller provides several features to
enhance the performance of converters.
High-Voltage Startup
Low Operating Current
Interleaved Stand-by PWM / Forward PWM Switching
Green Mode Stand-by PWM / Forward PWM
To minimize standby power consumption, a proprietary
green-mode function provides off-time modulation to
linearly decrease the switching frequency at light-load
conditions. To avoid acoustic-noise problems, the
minimum PWM frequency is set above 20KHz. This
green-mode function enables the power supply to meet
international power conservation requirements. With the
internal high-voltage startup circuitry, the power loss
due to bleeding resistors is also eliminated. To further
Linearly Decreasing Stand-by PWM Frequency to
20kHz
Remote On / Off
AC Brownout Protection
Forward PWM with Soft-Start
Frequency Hopping to Reduce EMI Emissions
reduce
power
consumption,
FAN6791/3
is
manufactured using the CMOS process, which allows
an operating current of only 6mA.
Cycle-by-Cycle Current Limiting for Stand-by PWM /
Forward PWM
FAN6791/3 integrates
a frequency-jittering function
internally to reduce EMI emissions of a power supply
with minimum line filters. The built-in synchronized slope
compensation achieves stable peak-current-mode
control. The proprietary internal line compensation
ensures constant output power limit.
Leading-Edge Blanking for Stand-by PWM / Forward
PWM
Synchronized Slope Compensation for Stand-by
PWM / Forward PWM
GATE Output Maximum Voltage Clamp
VDD Over-Voltage Protection (OVP)
VDD Under-Voltage Lockout (UVLO)
FAN6791/3 provides many protection functions,
including brownout protection, cycle-by-cycle current
limiting, and an internal open-loop protection circuit to
ensure safety should an open-loop or output short-
circuit failure occur. PWM output is disabled until VDD
drops below the UVLO lower limit when the controller
restarts. As long as VDD exceeds ~24.5V, the internal
OVP circuit is triggered.
Internal Open-Loop Protection for Stand-by PWM /
Forward PWM
Constant Power Limit for Stand-by PWM / Forward
PWM
Applications
General-purpose switch-mode power supplies and
flyback power converters, including:
PC-ATX Power Supplies
© 2008 Fairchild Semiconductor Corporation
FAN6791 / FAN6793 • Rev. 1.0.2
www.fairchildsemi.com
Ordering Information
Part
Number
OPWM
Operating
Packing
Method
Package
Eco Status
Green
Maximum Duty Temperature Range
16-pin Dual In-Line
Package (DIP)
FAN6791NY
FAN6793NY
FAN6791MY
FAN6793MY
48%
65%
48%
65%
-40°C to +105°C
-40°C to +105°C
-40°C to +105°C
-40°C to +105°C
Tube
16-pin Dual In-Line
Package (DIP))
Green
Tube
16-pin Small Out-Line
Package (SOP)
Green
Tape & Reel
Tape & Reel
16-pin Small Out-Line
Package (SOP)
Green
For Fairchild’s definition of “green” Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.
Application Diagram
Figure 1. Typical Application
© 2008 Fairchild Semiconductor Corporation
FAN6791 / FAN6793 • Rev. 1.0.2
www.fairchildsemi.com
2
Block Diagram
Pattern
Generator
Figure 2. Function Block Diagram
© 2008 Fairchild Semiconductor Corporation
FAN6791 / FAN6793 • Rev. 1.0.2
www.fairchildsemi.com
3
Marking Information
F – Fairchild Logo
Z – Plant Code
X – 1-Digit Year Code
Y – 1-Digit Week Code
TT – 2-Digit Die Run Code
T – Package Type (N:DIP, M:SOP)
P – Y: Green Package
M – Manufacture Flow Code
Figure 3. Top Mark
Pin Configuration
Figure 4. Pin Configuration (Top View)
© 2008 Fairchild Semiconductor Corporation
FAN6791 / FAN6793 • Rev. 1.0.2
www.fairchildsemi.com
4
Pin Definitions
Pin # Name Description
For startup, this pin is pulled HIGH to the line input or bulk capacitor via resistors.
1
2
3
HV
NC
No connection.
Ground.
GND
Oscillator Setting. One resistor connected between RI and ground pins determines the switching
frequency (resistance between 12 ~ 47kΩ is recommended). The switching frequency is equal to
[1560 / RI]kHz, where RI is in kΩ. For example, if RI is equal to 24kΩ, then the switching frequency
is 65kHz.
4
RI
Voltage Feedback for Flyback PWM Stage. It is internally pulled HIGH through a 6.5kΩ resistor.
An external opto-coupler from secondary feedback circuit is usually connected to this pin.
5
6
7
FBFYB
IFYB
PWM Current Sense for Flyback PWM Stage. The sensed voltage is used for peak-current-
mode control and cycle-by-cycle current limiting.
Voltage Feedback for Forward PWM Stage. It is internally pulled HIGH through a 6.5kΩ resistor.
An external opto-coupler from secondary feedback circuit is usually connected to this pin.
FBPWM
PWM Current Sense for Forward PWM Stage. Via a current sense resistor, this pin provides the
control input for peak-current-mode control and cycle-by-cycle current limiting.
8
9
IPWM
VREF
Reference voltage. This pin can provide a reference voltage 5V.
PWM Soft-Start. During startup, the SS pin charges an external capacitor with a 20µA constant
current source. The voltage on FBPWM is clamped by SS during startup. In the event of a
protection condition occurring and/or forward PWM being disabled, the SS pin quickly discharges.
10
SS
PWM Remote ON/OFF. Active HIGH. The forward PWM is disabled whenever the voltage at this
pin is lower than 0.8V or the pin is open.
11
12
13
ON/OFF
PGND
Ground. The power ground.
Forward PWM Gate Drive. The totem-pole output drive for the forward PWM MOSFET. This pin is
internally clamped under 16V to protect the MOSFET.
OPWM
Power Supply. The internal protection circuit disables PWM output as long as VDD exceeds the
OVP trigger point.
14
15
16
VDD
OFYB
VRMS
Flyback PWM Gate Drive. The totem-pole output drive for the forward PWM MOSFET. This pin is
internally clamped under 16V to protect the MOSFET.
Line-Voltage Detection. The pin is used for line compensation, for forward, and brownout
protection.
© 2008 Fairchild Semiconductor Corporation
FAN6791 / FAN6793 • Rev. 1.0.2
www.fairchildsemi.com
5
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only. All voltage values, except differential voltage, are given with
respect to GND pin. Stresses beyond those listed under “absolute maximum ratings “may cause permanent damage
to the device.
Symbol
Parameter
Min.
Max.
Unit
VDD
VHV
VHIGH
VLOW
PD
DC Supply Voltage
27
500
27.0
7.0
V
V
Input Voltage to HV Pin
OPWM, OFYB, ON/OFF
Others
-0.3
-0.3
V
V
Power Dissipation (TA < 50°C)
Operating Junction Temperature
Storage Temperature Range
°C/W
°C
°C
800
+125
TJ
-40
-55
TSTG
RΘ j-a
+150
82.5
Thermal Resistance (Junction-to-Case)
°C/W
°C
TL
Lead Temperature (Wave Soldering, 10 Seconds)
+260
3.5
Human Body Model , JEDEC:JESD22-A114
(All Pins Except HV Pin)
ESD
kV
Charged Device Model , JEDEC:JESD22-C101
(All Pins Except HV Pin)
1.5
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
Operating Ambient Temperature
Min.
Max.
Unit
TA
-40
+105
°C
© 2008 Fairchild Semiconductor Corporation
FAN6791 / FAN6793 • Rev. 1.0.2
www.fairchildsemi.com
6
Electrical Characteristics
VDD=18V; RI=24kΩ;TA =25°C, unless noted.
Symbol
VDD Section
VDD-OP
Parameter
Conditions
Min.
Typ.
Max.
Units
Continuously Operating Voltage
Startup Current
22
50
10
V
IDD ST
VDD – 0.16V
10
6
μA
mA
mA
IDD-OP1
Operating Current 1
VDD=15V, GATE Open
VDD=15V, GATE Open,
REF=10mA
IDD-OP2
Operating Current 2
16
20
I
VTH-ON
VTH-OFF
VTH-OLP
ITH-OLP
Start Threshold Voltage
Minimum Operating Voltage
IDD-OLP Off Voltage
15
9
16
10
7.5
80
17
11
V
V
6.5
70
8.0
100
V
Internal Sink Current
VTH-OLP +0.1V
VDD-OVP=26V
μA
V
VDD Over-voltage Protection
(Turn Off PWM with Delay)
VDD-OVP
23.4
80
24.5
100
25.5
120
VDD Over-Voltage Protection
Debounce
μs
tOVP
HV
VAC=90V(VDC=120V),
VDD=10µF
ID
Maximum Input Current
Internal Current Source
1.5
2.5
10
3.5
50
mA
IHV-CS
HV=500V,VDD=15V
μA
Oscillator and Green-Mode Operation
VRI
RI Voltage
1.176
62
1.200
65
1.224
68
V
Center Frequency,
RI=24kΩ
fOSC
Normal PWM Frequency
kHz
Jitter Range
±3.7
18
±4.2
20
±4.7
22
Minimum Frequency in Green
Mode
fOSC-G-MIN
RI
RI=24kΩ
kHz
kΩ
RI Range
12
24
47
If RI > RIOPEN, PWM
Turned Off
RIOPEN
RI Pin Open Protection
1
MΩ
If RI > RISHORT, PWM
Turned Off
RISHORT
RI Pin Short Protection
6
kΩ
VRMS for AC Brownout Protection
Off Threshold Voltage for AC
Brownout Protection
VRMS-OFF
VRMS-ON
tRMS
0.75
0.80
0.85
V
V
Start Threshold Voltage for AC
Brownout Protection
VRMS-UVP-1 VRMS-UVP-1 VRMS-UVP-1
+0.17
+0.19
+0.21
AC Brownout Protection
Debounce Time
RI=24kΩ
150
195
240
ms
VREF
VREF
Reference Voltage
IREF=1mA, CREF=0.1µF
4.75
5.00
5.25
80
V
Load Regulation of Reference
Voltage
CREF=0.1µF,
△VREF1
mV
IREF=1mA to 10mA
Line Regulation of Reference
Voltage
CREF=0.1µF,
VDD=12V to 22V
△VREF2
25
mV
IREF_MAX
IOS
Maximum Current
10
15
15
25
mA
mA
Output Short Circuit
20
© 2008 Fairchild Semiconductor Corporation
FAN6791 / FAN6793 • Rev. 1.0.2
www.fairchildsemi.com
7
Electrical Characteristics
VDD=18V; RI=24kΩ;TA =25°C, unless noted.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
ON/OFF
RON/OFF
Impedance ON/OFF Pin
50
100
3.6
kΩ
High Threshold Level of
Synchronizing Signal
VON
2.4
3.0
1.0
V
Low Threshold Level of
Synchronizing Signal
VOFF
0.8
1.2
V
Over Temperature Protection (OTP)
Protection Junction
TOff
130
100
140
110
+150
+120
°C
°C
Temperature(1)
TRestart
Restart Junction Temperature(2)
Flyback PWM Stage
FBFYB Feedback Input
FB Input to Current Comparator
Attenuation
AV-FLY
1/3.75
1/3.20
1/2.75
7
V/V
ZFB
VHGH
VFB-OLP
tOLP
Input Impedance
4
5
kΩ
Output High Voltage
FB Pin Open
5.0
4.2
53
5.2
4.5
56
V
V
FB Open-Loop Trigger Level
FB Open-Loop Protection Delay
Green Mode Entry FB Voltage
Slope of Green-Mode Modulation
Green Mode Ending FB Voltage
4.8
59
ms
V
VN
2.4
60
2.5
75
2.6
90
SG
Hz/mV
V
VG
1.8
1.9
2.0
VFBPWM for Zero Duty Cycle
(Forward Turn On)
VOZ-OFYB
1.2
1.3
1.4
V
IFYB Current Sense
ZCS
Input Impedance
12
kΩ
Peak Current Limit Threshold
Voltage 1
VLIMIT1
VRMS=1V
0.75
60
0.80
0.85
120
V
Peak Current Limit Threshold
Voltage 2
VLIMIT2
tPD
VRMS=1.5V
VLIMIT1 -0.1
V
Propagation Delay to GATE
Output
VDD=15V, OFYB Drops
to 9V
ns
tBNK
Leading-Edge Blanking Time
Slope Compensation
200
270
350
ns
V
Duty=DCYMAX
0.34
0.37
0.41
ΔVSLOPE
Threshold Voltage for SENSE
Short-Circuit Protection
VS-SCP
tD-SSCP
0.1
0.15
180
0.2
V
Delay Time for SENSE Short-
Circuit Protection
VSENSE<0.15V,
RI=24KΩ
100
240
µs
OFYB-GATE Driver
Flyback PWM Gate Output
VOFYB-CLAMP
VDD=22V
16
18
V
Clamping Voltage
Output Voltage Low
Output Voltage High
VOL-OFYB
VOH-OFYB
VDD=15V; IO=20mA
VDD=12V; IO=20mA
1.5
V
V
8
VDD=15V; Gate=1nF;
Gate=2~9V
tR-OFYB
tF-OFYB
Rising Time
Falling Time
30
60
120
ns
VDD=15V; Gate=1nF;
Gate=9~2V
30
60
50
65
90
70
ns
%
DCYMAX-OFYB Maximum Duty Cycle
© 2008 Fairchild Semiconductor Corporation
FAN6791 / FAN6793 • Rev. 1.0.2
www.fairchildsemi.com
8
Electrical Characteristics
VDD=18V; RI=24kΩ;TA =25°C, unless noted.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
Forward PWM Stage
FBPWM-Feedback Input
FB to Current Comparator
Attenuation
AV
1/3.2
1/2.7
1/2.2
7
V/V
ZFB
Input Impedance
Output High Voltage
4
5
kΩ
VHGH
FB Pin Open
5.0
5.2
V
PWM Open-Loop Protection
Voltage
VOPEN-PWM
4.2
4.5
4.8
V
tOPEN-PWM- Interval of PWM Open-Loop
RI=24kΩ
RI=24kΩ
500
600
700
ms
Protection Reset
HICCUP
PWM Open-Loop Protection
Delay Time
tOPEN-PWM
80
95
120
1.4
ms
V
VOZ-OPWM
VFBPWM for Zero Duty Cycle
1.2
1.3
IPWM-Current Sense
Propagation Delay to Output –
VLIMIT Loop
VDD=15V, OPWM
Drops to 9V
tPD
60
120
ns
V
Peak Current Limit Threshold
Voltage 1
VLIMIT1
VRMS=1V
0.75
0.80
0.85
Peak Current Limit Threshold
Voltage 2
VLIMIT2
tBNK
VRMS=1.5V
VLIMIT1-0.1
350
V
Leading-Edge Blanking Time
270
450
ns
Slope Compensation
ΔVs=ΔVSLOPE x (ton/t)
ΔVs: Compensation Voltage
Added to Current Sense
0.40
0.45
16
0.55
V
ΔVSLOPE
OPWM-GATE Driver
Output Voltage Maximum
(Clamp)
VOPWM-CLAMP
VDD=22V
18
V
VOL
VOH
Output Voltage Low
Output Voltage High
VDD=15V; IO=100mA
VDD=13V; IO=100mA
1.5
V
V
8
VDD=15V; CL=5nF;
O/P=2V to 9V
tR
tF
Rising Time
Falling Time
30
60
50
120
110
ns
ns
VDD=15V; CL=5nF;
O/P=9V to 2V
30
FAN6791 Maximum Duty Cycle
FAN6793 Maximum Duty Cycle
47
60
48
65
49
70
DCYMAX-OPWM
%
RI=24kΩ
Soft Start
Constant Current Output for
Soft-Start
ISS
17
20
23
µA
RI=24kΩ
RD
Discharge Resistance
470
564
Ω
Notes:
1. When activated, the output is disabled and the latch is turned off.
2. This is the threshold temperature for enabling the output again and resetting the latch after over-temperature
protection has been activated.
© 2008 Fairchild Semiconductor Corporation
FAN6791 / FAN6793 • Rev. 1.0.2
www.fairchildsemi.com
9
Typical Characteristics
10.0
9.0
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0.0
10.0
9.0
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0.0
-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
Figure 5. Startup Current IDD-ST vs. Temperature
Figure 6. IDD-OP1 vs. Temperature
20.0
19.0
18.0
17.0
16.0
15.0
14.0
13.0
12.0
11.0
2.5
2.0
1.5
1.0
0.5
0.0
10.0
-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
Figure 7. IDD-OP2 vs. Temperature
Figure 8. ID-MAX vs. Temperature
16.2
16.1
16.0
15.9
15.8
15.7
15.6
10.2
10.1
10.0
9.9
9.8
9.7
9.6
9.5
9.4
9.3
9.2
15.5
-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
Figure 9. VDD-ON vs. Temperature
Figure 10. VDD-OFF vs. Temperature
47.50
47.45
47.40
47.35
47.30
47.25
47.20
47.15
64.4
64.3
64.2
64.1
64.0
63.9
63.8
63.7
63.6
63.5
63.4
63.3
47.10
-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
Figure 11. OPWM Maximum Duty Cycle
vs. Temperature
Figure 12. OFYB Maximum Duty Cycle
vs. Temperature
© 2008 Fairchild Semiconductor Corporation
FAN6791 / FAN6793 • Rev. 1.0.2
www.fairchildsemi.com
10
Typical Characteristics
32.10
32.05
32.00
31.95
31.90
31.85
31.80
31.75
57.5
57.0
56.5
56.0
55.5
55.0
54.5
54.0
53.5
31.70
-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
Figure 13. Rising Time tR-OPWM vs. Temperature
Figure 14. Falling Time tF-OPWM vs. Temperature
27.4
27.2
27.0
26.8
26.6
26.4
26.2
26.0
39
38
37
36
35
34
33
32
31
25.8
30
-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
Figure 15. Rising Time tR-OFYB vs. Temperature
Figure 16. Falling Time tF-OFYB vs. Temperature
0.802
0.800
0.798
0.796
0.794
0.792
0.790
0.667
0.666
0.665
0.664
0.663
0.662
0.661
0.660
0.788
0.659
-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
Figure 17. IPWM-VLIMIT (VRMS=1V) vs. Temperature
Figure 18. IPWM-VLIMIT (VRMS=1.5V) vs. Temperature
0.815
0.810
0.805
0.800
0.795
0.790
0.785
0.653
0.652
0.651
0.650
0.649
0.648
0.647
0.646
0.645
0.644
0.780
0.643
-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
Figure 19. IFYB-VLIMIT (VRMS=1V) vs. Temperature
Figure 20. IFYB-VLIMIT (VRMS=1.5V)vs. Temperature
© 2008 Fairchild Semiconductor Corporation
FAN6791 / FAN6793 • Rev. 1.0.2
www.fairchildsemi.com
11
Typical Characteristics
66.1
66.0
65.9
65.8
65.7
65.6
66.3
66.2
66.1
66.0
65.9
65.8
65.7
65.6
65.5
-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
Figure 21. OPWM Frequency vs. Temperature
Figure 22. OFYB Frequency vs. Temperature
© 2008 Fairchild Semiconductor Corporation
FAN6791 / FAN6793 • Rev. 1.0.2
www.fairchildsemi.com
12
Functional Description
The highly integrated FAN6791 / FAN6793 dual-PWM
combination controller provides several features to
enhance the performance of converters.
Proprietary interleave switching synchronizes the
flyback and forward PWM stages. This reduces
switching noise.
The proprietary frequency jittering function for the
flyback and forward PWM stages helps reduce
switching EMI emissions.
Figure 23. Oscillation Frequency in Green Mode
For the flyback and forward PWM, the synchronized
slope compensation ensures the stability of the current
loop under continuous-mode operation. In addition,
FAN6791/3 provides complete protection functions,
such as brownout protection and RI open/short.
Line Voltage Detection (VRMS
)
Figure 24 shows a resistive divider with low-pass
filtering for line-voltage detection on VRMS pin. The
VRMS voltage is used for the PFC multiplier and
brownout protection. For brownout protection, when the
VRMS voltage drops below 0.8V, OPFC turns off.
Startup Current
For startup, the HV pin is connected to the line input or
bulk capacitor through external resistor RHV,
recommended as 100KΩ. Typical startup current drawn
from pin HV is 2mA and it charges the hold-up capacitor
through the resistor RHV. When the VDD capacitor level
reaches VDD-ON, the startup current switches off. At this
moment, the VDD capacitor only supplies the FAN6791/3
to maintain the VDD before the auxiliary winding of the
main transformer provides the operating current.
Oscillator Operation
A resistor connected from the RI pin to the GND pin
generates a constant current source for the FAN6791/3
controller. This current is used to determine the center
PWM frequency. Increasing the resistance reduces
PWM frequency. Using a 24KΩ resistor results in a
corresponding 65kHz PWM frequency. The switching
frequency is programmed by the resistor RI connected
between RI pin and GND. The relationship is:
Figure 24. Line-Voltage Detection on VRMS Pin
Remote On/Off
Figure 25 shows the remote on / off function. When the
supervisor FPO pin pulls down and enables the system
by connecting an opto-coupler, VREF applies to the
ON/OFF pin to enable forward PWM stage.
1560
fPWM
=
(kHz)
(1)
RI(kΩ)
The range of the PWM oscillation frequency is designed
as 33KHz ~ 130KHz. FAN6791/3 integrates frequency
hopping function internally. The frequency variation
ranges from around 61KHz to 69KHz for a center
frequency 65KHz. The frequency hopping function helps
reduce EMI emission of a power supply with minimum
line filters.
For power saving, flyback PWM stage has a green
mode function. Frequency linearly decreases when VFB
is within VG and VN. Once VFB is lower than VG,
switching frequency disables, and it enters burst mode.
Figure 25. Remote On/Off
© 2008 Fairchild Semiconductor Corporation
FAN6791 / FAN6793 • Rev. 1.0.2
www.fairchildsemi.com
13
Interleave Switching
Constant Power Control
The FAN6791/3 uses interleaved switching to
synchronize the stand-by PWM / forward PWM stages.
This reduces switching noise and spreads the EMI
emissions. Figure 26 shows that an off-time tOFF is
inserted in between the turn-off of the stand-by gate
drives and the turn-on of the forward PWM.
To limit the output power of the converter constantly, a
power-limit function is included. Sensing the converter
input voltage through the VRMS pin, the power limit
function generates a relative peak-current-limit threshold
voltage for constant power control, as shown in Figure 28.
Figure 26. Interleaved Switching
Slope Compensation
The stand-by PWM and forward PWM stage are
designed for flyback and forward power converters.
Peak-current-mode control is used to optimize system
performance. Slope compensation is added to stabilize
Figure 28. Constant Power Control
Protections
the current loop. The FAN6791/3 inserts
a
synchronized, positively sloped ramp at each switching
cycle. The positively sloped ramp is represented by the
voltage signal Vs-comp in Figure 27.
The FAN6791/3 provides full protection functions to
prevent the power supply and the load from being
damaged. The protection features include:
VDD Over-Voltage Protection. The stand-by PWM and
forward PWM stages will be disabled whenever the
VDD voltage exceeds the over-voltage threshold.
AC Under-Voltage Protection. The VRMS pin is used to
detect the AC input voltage. When voltage is lower than
the brownout threshold, voltage disables both forward
and stand-by PWM.
RI Pin Open / Short Protection. The RI pin is used to set
the switching frequency and internal current reference.
The stand-by PWM and forward PWM stages are
disabled whenever the RI pin is short or open.
Open-Loop Protection. The stand-by PWM and forward
PWM stages of FAN6791/3 is disabled whenever the
FBFYB / FBPWM pin is open.
Figure 27. Slope Compensation
Gate Drivers
FAN6791/3 output stages are fast totem-pole gate
drivers. The output driver is clamped by an internal 18V
Zener diode to protect the power MOSFET.
© 2008 Fairchild Semiconductor Corporation
FAN6791 / FAN6793 • Rev. 1.0.2
www.fairchildsemi.com
14
Reference Circuit
Figure 29. Reference Circuit
© 2008 Fairchild Semiconductor Corporation
FAN6791 / FAN6793 • Rev. 1.0.2
www.fairchildsemi.com
15
BOM List
Reference
Component
C/0.47µF/X2
C/0.47µF/X2
C/471P/50V
C/471P/50V
C/102P/50V
C/102P/50V
C/102P/50V
C/472/400V
C/472/400V
C/102P/50V
C/10µF/50V
C/104P/50V
C/102P/1KV
C/470µF/200V
C/470µF/200V
C/103P/1KV
C/1000µF/10V
C/330µF/10V
C/103P/50V
R/680K 1/4W NC
R/680K 1/4W
R/51.1K 1/4W
R/51.1K 1/4W
R/2.4M 1/4W
R/2.4M 1/4W
R/24K 1/8W
R/1K 1/8W
Reference
R18
R20
R21
R22
R23
R24
R26
R29
R31
R35
R37
R38
Q1
Component
R/100 1/8W
R/1/1W
C1
C2
C3
R/1 1/8W
R/402 1/8W
R/47K 3W
R/10K 1/8W
R/2K 1/8W
R/470 1/8W
R/0.1/2W
R/N.A 1/4W
R/20K 1% 1/8W
R/20K 1% 1/8W
2N/60
C4
C5
C6
C7
C8
C9
C10
C11
C12
C20
C21
C22
C23
C24
C25
C28
R1
Q2
9N90
Z3
7D271
Z2
7D271
Z1
7D561
D1
D/1N4007
D/UF107
D/SB540
D/UF1007
D/6A/600V
SG6791/3
PC-817
D2
D3
R2
D4
R3
BD1
U1
R4
R5
U2
R6
U3
TL431
R7
U6
PC-817
R8
R9
R/19.1K 1/8W
R/1K 1/8W
R10
R13
R14
R15
R17
R/100K 1/2W
R/10 1/8W
R/10 1/8W
R/100 1/8W
© 2008 Fairchild Semiconductor Corporation
FAN6791 / FAN6793 • Rev. 1.0.2
www.fairchildsemi.com
16
Physical Dimension
A
19.68
18.66
9
16
6.60
6.09
1
8
(0.40)
TOP VIEW
0.38 MIN
5.33 MAX
8.13
7.62
3.42
3.17
3.81
2.92
15
0
0.35
0.20
2.54
0.58
0.35
A
1.78
1.14
8.69
17.78
SIDE VIEW
NOTES: UNLESS OTHERWISE SPECIFIED
A
THIS PACKAGE CONFORMS TO
JEDEC MS-001 VARIATION BB
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS ARE EXCLUSIVE OF BURRS,
MOLD FLASH, AND TIE BAR PROTRUSIONS
D) CONFORMS TO ASME Y14.5M-1994
E) DRAWING FILE NAME: N16EREV1
Figure 30. 16-pin Dual In-Line Package (DIP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
© 2008 Fairchild Semiconductor Corporation
FAN6791 / FAN6793 • Rev. 1.0.2
www.fairchildsemi.com
17
Physical Dimensions (Continued)
Figure 31. 16-Pin Small Outline Package (SOIC)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
© 2008 Fairchild Semiconductor Corporation
FAN6791 / FAN6793 • Rev. 1.0.2
www.fairchildsemi.com
18
© 2008 Fairchild Semiconductor Corporation
FAN6791 / FAN6793 • Rev. 1.0.2
www.fairchildsemi.com
19
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