FAN7318AMX_技术文档

August 2009

FAN7318A

LCD Backlight Inverter Drive IC

Features

Description

The FAN7318A is a LCD backlight inverter drive IC that

controls P-N half-bridge topology.

High-Efficiency, Single-Stage Power Conversion

Wide Input Voltage Range: 6V to 30V

Backlight Lamp Ballast and Soft Dimming

Minimal External Components Required

Precision Voltage Reference Trimmed to 2%

Half-Bridge Topology

The FAN7318A provides a low-cost solution and reduces

external components by integrating proprietary wave

rectifiers for open-lamp protection and regulation. The

operating voltage range is wide, so an external regulator

isn’t necessary to supply voltage to the IC.

Soft-Start

The FAN7318A provides various protections, such as

open-lamp regulation, over-voltage protection, open-

lamp protection, short-lamp protection, and CMP-HIGH

protection, to increase the system reliability. The

FAN7318A provides burst dimming and analog dimming.

PWM Control at Fixed Frequency

Analog Dimming Function

Burst Dimming Function

Programmable Striking Frequency

Open-Lamp Protection (OLP)

Open-Lamp Regulation (OLR)

Over-Voltage Protection (OVP)

Short-Lamp Protection (SLP)

CMP-High Protection (CHP)

Thermal Shutdown (TSD)

The FAN7318A is available in a 16-SOIC package.

16-Pin SOIC Package

Applications

LCD TV

LCD Monitor

Ordering Information

Part

Number

Operating

Temperature

Packing

Method

Eco

Status

Package

FAN7318AM

Rail

-25 to +85°C

16-Lead, Small Outline Integrated Circuit (SOIC)

RoHS

FAN7318AMX

Tape & Reel

For Fairchild’s definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.

Protected under U.S. patent no. 5,652,479.

FAN7318A • 1.0.0

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Block Diagram

Short-Lamp Protection

Min.

-

50µA @ OVP,SLP

2µA @ OLP.CMP high

3V/1V @ striking/normal

TIMER

0.3V

+

OLR1

Over-Voltage Protection

Protection

Min. &

Max.

Detector

/Full Wave

Recifier

Max.

+

TSD 150^oC

1.34V

2V

-

OLR2

+

-

OUTA

OUTB

0μA

Output Driver

+

3μA

1.34V

2.2V

-

Error. Amp. source

current change

Gm Amp.

-

+

Open-Lamp Regulation

Oscillator

max. 2V

Control

Logic

On @ striking

min. 0.5V

CT

-

GND

+

CMP

Error. Amp. source

current change

-

UVLO 5.5V

Error Amp.

Negative

Analog

Dimming

V_ref

+

ADIM

+

VIN

+

-

Hys. 0.45V

High_CMP

-

3.5V

-

1.35V

High CMP Protection

disable @ striking

+

52μA burst

sink current on

ENA

200k

OLP max.

Striking off

Voltage Reference

& Internal Bias

5V, max. 3mA

REF

17 Pulses Counter

And OLR<1.4V

OLP1

OLP2

Min. & Max.

Detector

/Full or Half

Wave

max. 2V

OLP

Rectifier

min. 0.5V

-

BCT

OLP min.

-

150μs

52μA burst

sink current on

disable @ striking

Delay

0.7V/0.5V

Striking/normal

+

BDIM

If ENA>2.5V, OLP & SLP disable.

If ENA<2.1V, OLP & SLP enable.

Figure 1. Internal Block Diagram

FAN7318A • 1.0.0

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2

Pin Configuration

16

15

14

13

12

11

10

9

F PXYTT

FAN7318A

1

2

3

4

5

6

7

8

Figure 2. Package Diagram

FAN7318A • 1.0.0

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3

Pin Definitions

Pin #

Name

Description

This pin is for protection delay time setting.

1

TIMER

Error amplifier output. Typically, a compensation capacitor is connected to this pin from the

ground.

2

3

4

CMP

ADIM

CT

This pin is the input for negative analog dimming.

This pin is for programming the switching frequency. Typically, a capacitor is connected to

this pin from ground and a resistor is connected to this pin from the REF pin.

This pin is 5V reference output. Typically, resistors are connected to this pin from the CT pin

and the BCT pin.

5

6

7

REF

BCT

This pin is for programming the frequency of the burst dimming. Typically, a capacitor is

connected to this pin from ground and a resistor is connected to this pin from the REF pin.

This pin is the input for negative burst dimming. The voltage range of 0.5 to 2V at this pin

controls burst mode duty cycle from 0% to 100%.

BDIM

8

ENA

GND

OUTB

OUTA

VIN

This pin is for turning on/off the IC.

9

This pin is the ground.

10

11

12

13

This pin is NMOS gate-drive output.

This pin is PMOS gate-drive output.

This pin is the supply voltage of the IC.

This pin is for open-lamp regulation. Its functions are the same as the OLR1 pin.

OLR2

This pin is for open-lamp protection and feedback control of lamp currents. Its functions are

the same as the OLP1 pin.

14

OLP2

This pin is for open-lamp regulation and short-lamp protection. It is connected to the full-

wave rectifier internally. When the maximum of rectified OLR inputs is between 1.34V and

2V, the error amplifier output current is limited to 3.0µA. When the maximum of rectified

OLR inputs reaches 2V, the error amplifier output current is 0A and its output voltage

maintains constant. The maximum of rectified OLR inputs is inputted to the negative of

another error amplifier for feedback control of lamp voltage. When the maximum of rectified

OLR inputs is more than 2.2V, another error amplifier for OLR is operating and lamp voltage

is regulated. In normal mode, if the maximum of rectified OLR inputs is higher than 1.34V or

if the minimum of rectified OLR inputs is lower than 0.3V for a predetermined time by the

TIMER pin capacitor and an internal current source 50µA, the IC shuts down to protect the

system in over-voltage condition or short-lamp condition, respectively.

15

OLR1

This pin is for open-lamp protection and feedback control of lamp currents. It is connected to

the half-wave rectifier and the full-wave rectifier internally. In striking mode, if the minimum

of rectified OLP inputs is less than 0.7V for a predetermined time by the TIMER pin

capacitor and an internal current source or; in normal mode, if the minimum of rectified OLP

inputs is less than 0.5V for another predetermined time by the TIMER pin capacitor and

another internal current source; the IC shuts down to protect the system in open-lamp

condition. The maximum of rectified OLP inputs is inputted to the negative of the error

amplifier for feedback control of lamp current.

16

OLP1

FAN7318A • 1.0.0

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4

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In

addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.

The absolute maximum ratings are stress ratings only.

Symbol

V_IN

Parameter

Min.

6

Max.

30

Unit

V

IC Supply Voltage

T_A

Operating Temperature Range

Operating Junction Temperature

Storage Temperature Range

Thermal Resistance Junction-Air^(1,2)

Power Dissipation

-25

+85

+150

90

°C

T_J

°C

T_STG

θ_JA

-65

°C

°C/W

W

P_D

1.4

Notes:

1. Thermal resistance test board; size: 76.2mm x 114.3mm x 1.6mm (1S0P); JEDEC standard: JESD51-2, JESD51-3.

2. Assume no ambient airflow.

Pin Breakdown Voltage

Pin #

1

Name

TIMER

CMP

ADIM

CT

Value

Unit

7

2

3

4

5

REF

6

BCT

7

BDIM

ENA

8

V

9

GND

OUTB

OUTA

VIN

10

11

12

13

14

15

16

30

±7

OLR2

OLP2

OLR1

OLP1

FAN7318A • 1.0.0

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5

Electrical Characteristics

For typical values, T_A=25°C, V_IN=15V, and -25°C ≤ T_A≤ 85°C, unless otherwise specified. Specifications to -25°C ~

85°C are guaranteed by design based on final characterization results.

Symbol

Parameter

Test Conditions

Min.

Typ. Max.

Unit

Under-Voltage Lockout Section (UVLO)

V_th

V_thhys

I_st

Start Threshold Voltage

Start Threshold Voltage Hysteresis

Startup Current

Increase V_IN

4.9

0.20

10

5.2

0.45

70

5.5

0.60

100

3.5

V

Decrease V_IN

V_IN=4.5V

µA

mA

I_op

Operating Supply Current

V_IN=15V, Not Switching

0.5

2.0

ON/OFF Section

V_on

V_off

On-State Input Voltage

1.4

5.0

0.7

V

Off-State Input Voltage

Standby Current

I_sb

ENA=0V

ENA=2V

50

120

200

190

280

µA

kΩ

R_ENA

Pull-Down Resistor

120

Reference Section (Recommend 1µF X7R Capacitor)

V₅

5V Regulation Voltage

5V Line Regulation

5V Load Regulation

4.9

5.0

4

5.1

50

V

V_5line

V_5load

mV

6 ≤ V_IN≤ 30V

4

10µA ≤ I₅≤ 3mA

Oscillator Section (Main)

T_A=25°C, CT=220pF,

RT=100kΩ

101.3

101.0

126.5

105.0

131.0

108.3

109.0

135.5

f_osc

Oscillation Frequency

kHz

CT=220pF, RT=100kΩ

T_A=25°C, CT=220pF,

RT=100kΩ

f_str

Oscillator Frequency in Striking Mode

CT Discharge Current

CT=20pF, RT=100kΩ

Striking

126.0

1.03

770

131.0

1.18

870

-12

136.0

1.33

970

-9

I_ctdcs

I_ctdc

I_ctcs

V_cth

V_ctl

mA

μA

V

Normal

CT Charge Current

CT High Voltage

CT Low Voltage

Striking

-15

2

0.45

V

Oscillator Section (Burst)

T_A=25°C, BCT=4.7nF,

BRT=1.4MΩ

321

330

342

f_oscb

Burst Oscillation Frequency

Hz

BCT=4.7nF,

BRT=1.4MΩ

317

20

343

32

I_bctdc

V_bcth

V_bctl

BCT Discharge current

BCT High Voltage

BCT Low Voltage

26

2

μA

V

0.5

V

Continued on the following page…

FAN7318A • 1.0.0

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6

Electrical Characteristics (Continued)

For typical values, T_A=25°C, V_IN=15V, and -25°C ≤ T_A≤ 85°C, unless otherwise specified. Specifications to -25°C ~

85°C are guaranteed by design based on final characterization results.

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

Analog Dimming Section

ADIM=0V, T_A=25°C

ADIM=0V

1.244

1.231

1.329

1.178

1.008

1.421

1.427

AV_rexx

Reference Voltage

V

ADIM=0.5V

ADIM=1.0V

Error Amplifier Section

l_sin

Output Sink Current

OLP=2.5V, ADIM=2.5V

OLP=0V, ADIM=0V

CMP=3V

63

-65

-1.4

41

76

-50

-1.0

52

94

-35

-0.6

63

µA

V

l_sur1

l_sur2

I_bsin

I_olpi

I_olpo

Output Source Current 1

Output Source Current 2

Burst CMP Sink Current

OLP Input Current

BDIM=5V, BCT=0V

OLP=2V

0

OLP Output Current

OLP=-2V

-30

-20

0.34

1.55

-10

OLP=0.3V

V_lpfx

Rectifiers Output of OLP

OLP=1.5V

V

V_olpr

OLP Input Voltage Range⁽³⁾

-4

4

V

Open-Lamp Regulation Section

I_olr1

I_olr2

Striking, OLR=1.6V

OLR Sweep

-3.4

-2.8

0

-2.3

µA

V

Error Amplifier Source Current for

Open-Lamp Regulation

V_olr1

V_olr2

V_olr3

G_mOLR

I_ors

Open-Lamp Regulation Voltage 1

Open-Lamp Regulation Voltage 2

Open-Lamp Regulation Voltage 3

OLR Error Amplifier Transconductance

OLR Error Amplifier Sink Current

OLR Input Current

OLR Sweep

1.24

1.88

2.1

1.34

1.98

2.2

310

60

1.44

2.08

2.3

Striking, OLR Sweep

V

180

40

440

80

µmho

µA

V

Normal, OLR=2.5V

OLR=2.5V

I_olri

0

I_olro

OLR Output Current

OLR Input Voltage Range⁽³⁾

OLR=-2.5V

-35

-4

-25

-15

4

V_olrr

Note:

3. These parameters, although guaranteed, are not 100% tested in production.

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FAN7318A • 1.0.0

7

Electrical Characteristics (Continued)

For typical values, T_A=25°C, V_IN=15V, and -25°C ≤ T_A≤ 85°C, unless otherwise specified. Specifications to -25°C ~

85°C are guaranteed by design based on final characterization results.

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

Protection Section

V_olp0

V_olp1

V_cmpr

V_slp

Open-Lamp Protection Voltage 0⁽⁴⁾

Open-Lamp Protection Voltage 1

CMP-High Protection Voltage

Short-Lamp Protection Voltage

Timer Threshold Voltage 1

Timer Threshold Voltage 2

Timer Current 1

Striking

0.65

0.42

3.40

0.22

2.87

1.00

1.7

0.70

0.49

3.50

0.30

3.02

1.10

2.1

0.75

0.56

3.60

0.38

3.17

1.20

2.5

V

Sweep OLP

Sweep CMP

Sweep TIMER

Striking, Sweep TIMER

Sweep TIMER

OLP=0V

V

V_tmr1

V_tmr2

I_tmr1

V

µA

°C

V

I_tmr2

Timer Current 2

Thermal Shutdown⁽⁴⁾

OLR=1.8V

40

50

60

TSD

V_ovp

150

1.34

Over-Voltage Protection Voltage

Sweep OLR

1.24

2.1

1.44

2.5

ENA2.3V OLP Disable/Enable Change

Voltage

dcr

2.3

V

Output Section

V_pdhv

V_pdlv

V_ndhv

V_ndlv

PMOS Gate High Voltage⁽⁴⁾

V_IN=15V

V_IN

V

PMOS Gate Low Voltage

NMOS Gate High Voltage

NMOS Gate Low Voltage⁽⁴⁾

V_IN-9.0 V_IN-7.5 V_IN-6.5

7.5

8.5

0

10.0

PMOS Gate Voltage with UVLO

Activated

NMOS Gate Voltage with UVLO

Activated

V_puv

V_nuv

V_IN=4.5V

V_IN-0.3

V

0.3

I_pdsur

I_pdsin

I_ndsur

I_ndsin

PMOS Gate Drive Source Current⁽⁴⁾

PMOS Gate Drive Sink Current⁽⁴⁾

NMOS Gate Drive Source Current⁽⁴⁾

NMOS Gate Drive Sink Current⁽⁴⁾

V_IN=15V

-300

400

mA

300

-400

Maximum / Minimum Duty Cycle

DC_MIN

DC_MAX

Minimum Duty Cycle⁽⁴⁾

Maximum Duty Cycle⁽⁴⁾

f_osc=100kHz

0

%

45

49

Note:

4. These parameters, although guaranteed, are not 100% tested in production.

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FAN7318A • 1.0.0

8

Typical Performance Characteristics

Figure 3. Start Threshold Voltage vs. Temperature

Figure 4. Start Threshold Voltage Hysteresis vs.

Temperature

Figure 5. Startup Current vs. Temperature

Figure 6. Operating Current vs. Temperature

Figure 7. Standby Current vs. Temperature

Figure 8. 5V Regulation Voltage vs. Temperature

FAN7318A • 1.0.0

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9

Typical Performance Characteristics (Continued)

Figure 9. Oscillation Frequency vs. Temperature

Figure 10. Oscillation Frequency in Striking

vs. Temperature

Figure 11. CT High Voltage vs. Temperature

Figure 12. CT Low Voltage vs. Temperature

Figure 13. Burst Dimming Frequency vs. Temperature

Figure 14. BCT Discharge Current vs. Temperature

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FAN7318A • 1.0.0

10

Typical Performance Characteristics (Continued)

Figure 15. BCT High Voltage vs. Temperature

Figure 16. BCT Low Voltage vs. Temperature

Figure 17. Analog Dimming Reference Voltage 00

vs. Temperature

Figure 18. Analog Dimming Reference Voltage 05

vs. Temperature

Figure 19. Error Amplifier Source Current 1

vs. Temperature

Figure 20. Error Amplifier Source Current 2

vs. Temperature

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FAN7318A • 1.0.0

11

Typical Performance Characteristics (Continued)

Figure 21. Error Amplifier Source Current for OLR

vs. Temperature

Figure 22. Error Amplifier Sink Current

vs. Temperature

Figure 23. Burst CMP Sink Current vs. Temperature

Figure 24. OLR Error Amplifier Sink Current

vs. Temperature

Figure 25. Open-Lamp Protection Voltage 1

vs. Temperature

Figure 26. High-CMP Protection Voltage

vs. Temperature

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FAN7318A • 1.0.0

12

Typical Performance Characteristics (Continued)

Figure 27. Short-Lamp Protection Voltage

vs. Temperature

Figure 28. Open-Lamp Regulation Voltage 1

vs. Temperature

Figure 29. Open-Lamp Regulation Voltage 2

vs. Temperature

Figure 30. Open-Lamp Regulation Voltage 3

vs. Temperature

Figure 31. TIMER Threshold Voltage 1

vs. Temperature

Figure 32. TIMER Threshold Voltage 2

vs. Temperature

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FAN7318A • 1.0.0

13

Typical Performance Characteristics (Continued)

Figure 33. TIMER Current 1 vs. Temperature

Figure 34. TIMER Current 2 vs. Temperature

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FAN7318A • 1.0.0

14

Functional Description

UVLO

The under-voltage lockout (UVLO) circuit guarantees the

stable operation of the IC’s control circuit by stopping

and starting it as a function of the V_INvalue. The UVLO

circuit turns on the control circuit when V_INexceeds

5.2V. When V_INis lower than 4.75V, the IC startup

current is less than 100µA.

1

f_str

=

Hz

[

]

⎛

⎜

⎞

⎟

13.65 + 3I − 4.55I RT

−I ⋅I ⋅RT²

13.65 + 4.55I − 3I RT

(

)

1

2

1

2

RT ⋅CT ⋅ln

(2)

(

)

1

2

⎜

⎟

⎠

−I₁⋅I₂⋅RT

QI₁= 12×10^-6A, I₂= 1.128×10^-3A

⎝

ENA

Burst Dimming Oscillator

Applying voltage higher than 1.4V to the ENA pin

enables the IC. Applying voltage lower than 0.7V to the

ENA pin disables the IC. In terms of the protections,

applying voltage higher than 2.5V to the ENA pin

disables OLP and SLP. Applying voltage lower than

2.1V to the ENA pin enables the OLP and the SLP.

The burst dimming timing capacitor (BCT) is charged by

the current flowing from the reference voltage source,

which is formed by the burst dimming timing resistor

(BRT) and the burst dimming timing capacitor (BCT).

The sawtooth waveform charges up to 2V. Once the

BCT voltage reaches 2V, the capacitor begins

discharging down to 0.5V. Next, the BCT starts charging

again and a new burst dimming cycle begins, as shown

in Figure 36. The burst dimming frequency is

programmed by adjusting the BCT and BRT values. The

burst dimming frequency is calculated as:

Main Oscillator

In normal mode, the external timing capacitor (CT) is

charged by the current flowing from the reference

voltage source, which is formed by the timing resistor

(RT) and the timing capacitor (CT). The sawtooth

waveform charges up to 2V. Once CT voltage reaches

2V, the CT begins discharging down to 0.4V. Next, the

CT starts charging again and a new switching cycle

begins, as shown in Figure 35. The main frequency is

programmed by adjusting the RT and CT value. The

main frequency is calculated as:

1

f_OSCB

=

[

Hz

]

(3)

0.039 ⋅BRT − 4500

0.026 ⋅BRT − 4500

⎛

⎞

⎟

BRT ⋅BCT ⋅ln

⎜

⎝

⎠

To avoid visible flicker, the burst dimming frequency

should be greater than 120Hz.

1

f_OSC

=

Hz

[

]

3.9585⋅RT −13650

2.61⋅RT −13650

⎛

⎞

(1)

RT ⋅CT ⋅ln

⎜

⎝

⎟

⎠

Figure 36. Burst Dimming Oscillator Circuit

Analog Dimming

For analog dimming, the lamp intensity is controlled with

the external dimming signal (V_ADIM) and resistors. Figure

37 shows how to implement an analog dimming circuit.

Figure 35. Main Oscillator Circuit

CMP

In striking mode, the external timing capacitor (CT) is

charged by the current flowing from the reference

voltage source and 12μA current source, which

increases the frequency. If the product of RT and CT

value is constant, the striking frequency is depending on

CT and is calculated as:

Error Amp.

Negative

Analog

Dimming

V

REF

ADIM

+

-

V_ADIM

OLP max.

Figure 37. Analog Circuit Implementation

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15

In full brightness, the maximum rms value of the lamp

current is calculated as:

π

max

i

= V_{ref _max}

A

(4)

[

]

rms

2 2R_S1

The lamp intensity is inversely proportional to V_ADIM. As

V_ADIMincreases, the lamp intensity decreases and the

rms value of the lamp current is calculated as:

π

max

i

= V_ref

A

[

]

rms

2 2R_s

(5)

V_ref= V_{ref _max}− 0.30V_ADIM

A

[

]

Figure 38 shows the lamp current waveform vs. V_ADIMin

an analog dimming mode.

Figure 39. Negative Burst Dimming Waveform Using

DC Voltage

V_REF

2.0

Burst dimming can be implemented, not only DC

voltage, but also using PWM pulse as the BDIM signal.

Figure 40 shows how to implement burst dimming using

PWM pulse as BDIM signal.

1.5

1.0

0.5

0

0.5

1.0

1.5

2.0

2.5

ADIM

15mA

10mA

5mA

0

-5mA

-10mA

-15mA

Lamp Current

Figure 38. Analog Dimming Waveforms

Figure 40. Negative Burst Dimming Implementation

Circuit Using an External Pulse

Figure 41 shows the lamp current waveform vs. an

external pulse in negative burst dimming mode.

Burst Dimming

Lamp intensity is controlled with the BDIM signal over a

wide range. FAN7318A provide polarity selection. When

BDIM is inputted, the DC voltage or PWM pulse signal

and BCT is setting sawtooth waveform or DC voltage,

respectively. This structure can be implemented as

negative dimming polarity. When BDIM voltage is lower

than BCT voltage, the lamp current is turned on; 0V on

BDIM commands full brightness. The duty cycle of the

PWM pulse determines the lamp brightness. The lamp

intensity is inversely proportional to BDIM voltage. As

BDIM voltage increases, the lamp intensity decreases.

Figure 39 shows the lamp current waveform vs. DIM in

negative burst dimming mode.

Figure 41. Negative Burst Dimming Waveform Using

an External Pulse

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16

During striking mode, burst dimming operation is

disabled to guarantee continuous striking time. Figure

42 shows burst dimming disabled during striking mode.

Soft-Start

A soft-start circuit ensures a gradual increase in the

input and output power. FAN7318A has no soft-start pin,

but provides soft-start function using the first BCT

waveform. The first BCT waveform limits CMP voltage at

initial operation, so lamp current increases gradually.

2.5

2

BCT

1.5

BDIM

1

0.5

0

2

3

4

5

6

7

8

9

10

11

12

x 10^-3

2

1.5

1

CMP

0.5

0

3

4

5

6

7

12

x 10^-3

Striking normal mode

i_Lamp

mode

0.01

0.005

0

-0.005

-0.01

-0.015

Figure 45. Soft-Start in Normal Mode

3

4

5

6

7

12

x 10^-3

Figure 42. Burst Dimming During Striking Mode

When BDIM is setting over 2.2V_DCand BCT is inputted

PWM pulse signal, this structure can be implemented as

positive dimming polarity. Figure 43 shows burst

dimming using PWM pulse as BDIM signal.

Figure 46. Soft-Start in Burst Dimming Mode

Output Drives

FAN7318A is designed to drive P-N half-bridge

MOSFETs with symmetric duty cycle. FAN7318A can

drive a P-MOSFET directly without a level-shift capacitor

and a Zener diode. A fixed dead time of 500ns is

introduced between two outputs at maximum duty cycle,

as shown in Figure 47.

Figure 43. Positive Burst Dimming Implementation

Circuit Using an External Pulse

Dead time

500ns at max. duty

CT

CMP

Figure 44 shows the lamp current waveform vs. an

external pulse in positive burst dimming mode.

SYNC

T

OUTA

OUTB

Figure 47. MOSFETs Gate Drive Signal

Figure 44. Positive Burst Dimming Waveform Using

an External Pulse

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17

Open-Lamp Regulation

Lamp Current Feedback Circuit

When the maximum of the rectified OLR input voltages

FAN7318A has two OLP pins for lamp current feedback

and protections. The inputs of two OLP pins are

connected to the internal half-wave and full-wave

rectifier circuits. The half-wave rectified signals of two

OLP inputs are connected the maximum detector circuit.

The full-wave rectified signals of two OLP inputs are

connected to the minimum detector circuit.

max

OLR

( V ) is more than 2V, the IC enters regulation mode

and controls CMP voltage. The IC limits the lamp

max

OLR

voltage by decreasing CMP source current. If V

is

between 1.34V and 2V, CMP source current decreases

max

OLR

to 2.8µA. Then, if V

reaches 2V, CMP source current

decreases to 0µA, so the CMP voltage remains constant

and the lamp voltage also remains constant, as shown

in Figure 49.

The two inputs of the OLP pins should be inverse phase.

Lamp Voltage Feedback Circuit

FAN7318A has two OLR pins for lamp voltage feedback

and protections. The inputs of two OLR pins are

connected to the internal full-wave rectifier circuit. The

full-wave rectified signals of two OLR inputs are

connected to the maximum detector circuit for lamp

voltage feedback and protections. They are connected

to the minimum detector circuit for protections.

Protections

The FAN7318A provides the following latch-mode

protections: Open-Lamp Regulation (OLR), Open-Lamp

Protection (OLP), Short-Lamp Protection (SLP), CMP-

High Protection (CHP), and Thermal Shutdown (TSD).

The latch is reset when V_INfalls to the UVLO voltage or

ENA is pulled down to GND.

The protection delay time can be adjusted by a capacitor

between the TIMER pin and GND.

Figure 49. Open-Lamp Regulation in Striking Mode

max

Finally, if V

is more than 2.2V, the error amplifier for

OLR

OLR is operating and CMP sink current increases, so

CMP voltage decreases and the lamp voltage maintains

the determined value, as shown in Figure 50.

Figure 48. Protection Timing Delay

Assume that the TIMER pin capacitor is 1µF.

The striking time is calculated as:

CΔV_str

I_sur1

1μF •3V

2μA

(6)

(7)

t_strike

=

= 1.5s

The OVP and SLP delay time are calculated as:

Figure 50. 2.2V Open-Lamp Regulation

CΔV_nor

I_{sur 2}

1μF •1V

50μA

t_{OVP _SLP}

=

= 20ms

Over-Voltage Protection

max

OLR

V

The CMP-high protection and OLP delay time are

calculated as:

In normal mode, while

is higher than 1.34V, the

TIMER pin capacitor is charged by an internal current

source of 50µA. Once the TIMER reaches 1V, the IC

enters shutdown, as shown in Figure 51. This protection

is disabled in striking mode to ignite lamps reliably.

CΔV_nor

1μF •1V

2μA

(8)

t_{OLP _CMPH}

=

= 500ms

I_sur1

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18

The IC starts operating in striking mode and remains in

min

OLP

striking mode until 17 pulses of V

higher than 0.7V

and OLR<1.34V occur. If more than 17 pulses and

OLR<1.34V, the IC changes from striking mode into

normal mode, as shown in Figure 54.

Figure 51. Over-Voltage Protection in Normal Mode

max

OLR

In burst dimming mode, while V

is higher than 1.34V,

burst dimming is disabled, so that the TIMER pin

capacitor is charged continuously by an internal current

source of 50µA. Once the TIMER reaches 1V, the IC

enters shutdown, as shown in Figure 52.

Figure 54. Mode Change from Striking to Normal

min

OLP

After ignition, if V

is less than 0.5V for a time

predetermined by the TIMER pin capacitor and an

internal current source, 2µA in normal mode; the IC is

shut down, as shown in Figure 55 and Figure 56.

Figure 52. Over-Voltage Protection in Burst

Dimming Mode

OLP

Open-Lamp Protection

OLP1

Min. & Max.

OLP min.

min

OLP

If the minimum of the rectified OLP voltages ( V ) is

Detector

-

150μs

/Full or Half

Delay

less than 0.7V during initial operation, the IC operates in

striking mode for a time predetermined by the TIMER pin

capacitor and an internal current source, 2µA, as shown

in Figure 53.

0.5V

Wave

Rectifier

+

OLP2

Figure 55. Open-Lamp Protection in Normal Mode

OLP1

OLP2

Tim er

Figure 53. Open-Lamp Protection in Striking Mode

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19

Tim er

OLP1

Lam

p open

OLP1

OLP2

Figure 58. Open-Lamp Protection Disable in

DCR Mode

Tim er

Short-Lamp Protection

min

OLR

If the minimum of the rectified OLR voltages ( V ) is

OLP1

less than 0.3V for a time predetermined by the TIMER

pin capacitor and an internal current source of 50µA in

normal mode; the IC is shut down, as shown in Figure

59. This protection is disabled in striking mode to ignite

lamps reliably.

OLP2

Figure 56. Open-Lamp Protection in Normal Mode

min

OLP

In burst dimming mode, if V

is less than 0.5V for

another time predetermined by the TIMER pin capacitor

and an internal current source, 2µA; the IC is shut down,

as shown in Figure 57. The open-lamp protection delay

in burst dimming mode is shorter than in full-brightness

because short-lamp condition is detected at rising

interval of lamp voltage in burst dimming, then another

internal current source is turned on during the interval.

TIM ER

OLP1

Figure 59. Short-Lamp Protection in Normal Mode

min

OLR

In burst dimming mode, if V

is less than 0.3V for a

time predetermined by the TIMER pin capacitor and a

internal current source of 50µA turned on only burst

dimming on time; the IC is shut down, as shown in

Figure 60. SLP protection delay changes, depending on

burst dimming on duty ratio.

Zoom ofOLP2

OLP2

Figure 57. Open-Lamp Protection in Burst Dimming

Mode

Applying voltage lower than 2.1V to the ENA pin enables

OLP. Applying voltage higher than 2.5V to the ENA pin

disables OLP and is called as DCR mode. Regardless of

DCR mode, OLP is enabled in striking mode.

Figure 60. Short-Lamp Protection in Burst

Dimming Mode

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Applying voltage higher than 2.5V to the ENA pin

disables SLP. Applying voltage lower than 2.1V to the

ENA pin enables SLP.

Figure 63. CMP-High Protection Disable by a

Pull- Down Resistor

Figure 61. Short-Lamp Protection Disable in

DCR Mode

Thermal Shutdown

The IC provides the function to detect the abnormal

over-temperature. If the IC temperature exceeds

approximately 150°C, the thermal shutdown triggers.

CMP-High Protection

If CMP is more than 3.5V for a time predetermined by

the TIMER pin capacitor and a internal current source of

50µA in normal mode; the IC is shut down, as shown in

Figure 62.

Figure 62. CMP-High Protection

This protection is disabled by a pull-down resistor (a few

MΩ) between CMP and GND. If CMP voltage reaches

2.5V, CMP source current decreases to 2µA. Determine

a pull-down resistor value such that the whole of this

current can flow through the resistor. If so, CMP-high

protection can be disabled, as shown Figure 63. This

protection is disabled in striking mode to ignite the

lamps reliably.

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21

Typical Application Circuit (LCD Backlight Inverter)

Application

Device

Input Voltage Range

Number of Lamps

22-Inch LCD Monitor

FAN7318A

15V±10%

2

1. Features

High-Efficiency, Single-Stage Power Conversion

P-N Half-Bridge Topology

Reduces Required External Components

Enhanced System Reliability through Protection Functions

Figure 64. Typical Application Circuit

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22

Physical Dimensions

10.00

9.80

A

8.89

16

9

B

1.75

4.00

3.80

6.00

5.6

1

8

PIN ONE

INDICATOR

0.51

0.35

1.27

(0.30)

1.27

0.65

M

0.25

C B A

LAND PATTERN RECOMMENDATION

1.75 MAX

SEE DETAIL A

1.50

1.25

0.25

0.19

0.25

0.10

C

0.10 C

0.50

0.25

X 45°

NOTES: UNLESS OTHERWISE SPECIFIED

(R0.10)

A) THIS PACKAGE CONFORMS TO JEDEC

MS-012, VARIATION AC, ISSUE C.

B) ALL DIMENSIONS ARE IN MILLIMETERS.

C) DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD

FLASH AND TIE BAR PROTRUSIONS

GAGE PLANE

0.36

8°

0°

D) CONFORMS TO ASME Y14.5M-1994

E) LANDPATTERN STANDARD: SOIC127P600X175-16AM

F) DRAWING FILE NAME: M16AREV12.

SEATING PLANE

0.90

0.50

(1.04)

DETAIL A

SCALE: 2:1

Figure 65. -Lead, Small Outline Integrated Circuit (SOIC) Package

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,

specifically the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

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23

FAN7318A • 1.0.0

www.fairchildsemi.com

24


型号：	FAN7318AMX
厂家：	FAIRCHILD SEMICONDUCTOR
描述：	LCD Backlight Inverter Drive IC LCD背光逆变器驱动IC 显示驱动器驱动程序和接口接口集成电路光电二极管 CD
文件：	总24页 (文件大小：1377K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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