FAN7371_09 [FAIRCHILD]

High-Current High-Side Gate Drive IC; 大电流高边栅极驱动器IC
FAN7371_09
型号: FAN7371_09
厂家: FAIRCHILD SEMICONDUCTOR    FAIRCHILD SEMICONDUCTOR
描述:

High-Current High-Side Gate Drive IC
大电流高边栅极驱动器IC

驱动器 栅极 栅极驱动
文件: 总11页 (文件大小:1630K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
November 2009  
FAN7371  
High-Current High-Side Gate Drive IC  
Features  
Description  
! Floating Channel for Bootstrap Operation to +600V  
! 4A/4A Sourcing/Sinking Current Driving Capability  
! Common-Mode dv/dt Noise Canceling Circuit  
! 3.3V and 5V Input Logic Compatible  
! Output In-phase with Input Signal  
! Under- Voltage Lockout for VBS  
The FAN7371 is a monolithic high-side gate drive IC,  
which can drive high-speed MOSFETs and IGBTs that  
operate up to +600V. It has a buffered output stage with  
all NMOS transistors designed for high pulse current  
driving capability and minimum cross-conduction.  
Fairchild’s high-voltage process and common-mode  
noise canceling techniques provide stable operation of  
the high-side driver under high dv/dt noise circum-  
stances. An advanced level-shift circuit offers high-side  
gate driver operation up to VS=-9.8V (typical) for  
! 25V Shunt Regulator on VDD and VBS  
! 8-Lead Small Outline Package (SOP)  
VBS=15V.  
The UVLO circuit prevents malfunction when VBS is  
lower than the specified threshold voltage.  
Applications  
! High-Speed Gate Driver  
The high-current and low-output voltage drop feature  
makes this device suitable for sustaine switch driver and  
energy recovery switch driver in the Plasma Display  
Panel application, motor drive inverter, switching power  
supply, and high-power DC-DC converter applications.  
! Sustaine Switch Driver in PDP Application  
! Energy-Recovery Circuit Switch Driver in  
PDP Application  
! High-Power Buck Converter  
! Motor Drive Inverter  
8-SOP  
Ordering Information  
Operating  
Temperature Range  
Part Number  
Package  
Eco Status  
Packing Method  
FAN7371M(1)  
FAN7371MX(1)  
Tube  
8-SOP  
-40°C ~ 125°C  
RoHS  
Tape & Reel  
Note:  
1. These devices passed wave soldering test by JESD22A-111.  
For Fairchild’s definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.  
© 2008 Fairchild Semiconductor Corporation  
FAN7371 Rev. 1.0.2  
www.fairchildsemi.com  
Typical Application Diagrams  
15V  
DBOOT3  
RBOOT3  
VS  
15V  
FAN7371  
RBOOT1  
DBOOT1  
VB  
1
2
3
4
8
7
6
5
VDD  
IN  
Q3  
R3  
HO  
VS  
IN3  
D3  
D4  
FAN7371  
CBOOT3  
R4  
NC  
1
2
3
4
VB  
HO  
VS  
VDD  
IN  
8
7
6
5
L1  
NC  
GND  
IN1  
CBOOT1  
D1  
D2  
NC  
R1  
GND  
NC  
To Pannel  
DBOOT2  
R2  
Q1  
FAN7371  
FAN7371  
1
2
3
4
VB  
HO  
VS  
VB  
1
2
3
4
VDD  
IN  
8
7
6
5
8
7
6
5
VDD  
IN  
Q2  
Q4  
R5  
CBOOT2  
R7  
R8  
HO  
VS  
IN2  
IN4  
R6  
NC  
NC  
C1  
C3  
GND  
NC  
NC  
GND  
C2  
Energy Recovery Circuit Part  
Sustain Drive Part  
FAN7371 Rev.03  
Figure 1. Floated Bidirectional Switch and Half-Bridge Driver: PDP application  
15V  
VIN  
RBOOT  
DBOOT  
FAN7371  
VB  
VDD  
1
2
8
R1  
CBOOT  
HO  
IN  
PWM  
7
6
L1  
R2  
NC  
GND  
VS  
3
4
C1  
NC  
C2  
VOUT  
5
D1  
FAN7371 Rev.01  
Figure 2. Step-Down (Buck) DC-DC Converter Application  
© 2008 Fairchild Semiconductor Corporation  
FAN7371 Rev. 1.0.2  
www.fairchildsemi.com  
2
Internal Block Diagram  
VDD  
VDD  
1
4
8
7
6
VB  
25V  
UVLO  
R
GND  
HO  
VS  
R
NOISE  
CANCELLER  
IN  
2
25V  
S
Q
110K  
Pins 3 and 5 are no connection.  
FAN7371 Rev.04  
Figure 3. Functional Block Diagram  
Pin Configuration  
VDD  
IN  
1
2
3
4
8
7
6
5
VB  
HO  
VS  
FAN7371  
NC  
GND  
NC  
FAN7371 Rev.01  
Figure 4. Pin Configuration (Top View)  
Pin Definitions  
Pin #  
Name  
Description  
1
2
3
4
5
6
7
8
VDD  
IN  
Supply Voltage  
Logic Input for High-Side Gate Driver Output  
No Connection  
NC  
GND  
NC  
VS  
Ground  
No Connection  
High-Voltage Floating Supply Return  
High-Side Driver Output  
High-Side Floating Supply  
HO  
VB  
© 2008 Fairchild Semiconductor Corporation  
FAN7371 Rev. 1.0.2  
www.fairchildsemi.com  
3
Absolute Maximum Ratings  
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be opera-  
ble above the recommended operating conditions and stressing the parts to these levels is not recommended. In addi-  
tion, extended exposure to stresses above the recommended operating conditions may affect device reliability. The  
absolute maximum ratings are stress ratings only. TA=25°C unless otherwise specified.  
Symbol  
VS  
Characteristics  
High-Side Floating Offset Voltage  
High-Side Floating Supply Voltage(2)  
High-Side Floating Output Voltage  
Low-Side and Logic Supply Voltage(2)  
Logic Input Voltage  
Min.  
VB-VSHUNT  
-0.3  
Max.  
VB+0.3  
625.0  
VB+0.3  
VSHUNT  
VDD+0.3  
± 50  
Unit  
V
VB  
V
VHO  
VDD  
VIN  
VS-0.3  
-0.3  
V
V
-0.3  
V
dVS/dt  
PD  
Allowable Offset Voltage Slew Rate  
Power Dissipation(3, 4, 5)  
V/ns  
W
0.625  
200  
θJA  
Thermal Resistance  
°C/W  
°C  
°C  
°C  
TJ  
Junction Temperature  
-55  
-55  
-40  
+150  
TSTG  
TA  
Storage Temperature  
+150  
Operating Ambient Temperature  
+125  
Notes:  
2
This IC contains a shunt regulator on VDD and VBS with a normal breakdown voltage of 25V. Please note that this  
supply pin should not be driven by a low-impedance voltage source greater than the VSHUNT specified in the  
Electrical Characteristics section  
3
4
Mounted on 76.2 x 114.3 x 1.6mm PCB (FR-4 glass epoxy material).  
Refer to the following standards:  
JESD51-2: Integral circuits thermal test method environmental conditions, natural convection, and  
JESD51-3: Low effective thermal conductivity test board for leaded surface mount packages.  
5
Do not exceed power dissipation (PD) under any circumstances.  
Recommended Operating Conditions  
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended  
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not  
recommend exceeding them or designing to absolute maximum ratings.  
Symbol  
VBS  
Parameter  
High-Side Floating Supply Voltage  
High-Side Floating Supply Offset Voltage  
High-Side Output Voltage  
Min.  
VS+10  
6-VDD  
VS  
Max.  
VS+20  
600  
Unit  
V
VS  
V
VHO  
VIN  
VB  
V
Logic Input Voltage  
GND  
10  
VDD  
20  
V
VDD  
Supply Voltage  
V
© 2008 Fairchild Semiconductor Corporation  
FAN7371 Rev. 1.0.2  
www.fairchildsemi.com  
4
Electrical Characteristics  
VBIAS(VDD, VBS)=15.0V, TA = 25°C, unless otherwise specified. The VIN and IIN parameters are referenced to GND.  
The VO and IO parameters are relative to VS and are applicable to the respective output HO.  
Symbol  
Characteristics  
Test Condition  
Min. Typ. Max. Unit  
POWER SUPPLY SECTION  
IQDD Quiescent VDD Supply Current  
VIN=0V or 5V  
fIN=20KHz, No Load  
25  
35  
70  
μA  
μA  
IPDD  
Operating VDD Supply Current  
100  
BOOTSTRAPPED SUPPLY SECTION  
VBS Supply Under-Voltage Positive Going  
Threshold Voltage  
VBSUV+  
VBS=Sweep  
VBS=Sweep  
VBS=Sweep  
8.2  
7.5  
9.2 10.2  
V
V
V
VBS Supply Under-Voltage Negative Going  
VBSUV-  
8.5  
0.7  
9.5  
Threshold Voltage  
VBS Supply Under-Voltage Lockout  
VBSHYS  
Hysteresis Voltage  
ILK  
VB=VS=600V  
VIN=0V or 5V  
Offset Supply Leakage Current  
Quiescent VBS Supply Current  
10  
μA  
μA  
IQBS  
60  
120  
CLOAD=1nF, fIN=20KHz, rms  
Value  
IPBS  
Operating VBS Supply Current  
1.0  
2.8  
mA  
SHUNT REGULATOR SECTION  
VDD and VBS Shunt Regulator Clamping  
VSHUNT  
ISHUNT=5mA  
24  
25  
V
Voltage  
INPUT LOGIC SECTION  
VIH  
VIL  
IIN+  
IIN-  
RIN  
Logic “1” Input Voltage  
2.5  
V
V
Logic “0” Input Voltage  
0.8  
70  
2
VIN=5V  
VIN=0V  
Logic Input High Bias Current  
Logic Input Low Bias Current  
45  
μA  
μA  
KΩ  
70  
110  
Input Pull-down Resistance  
GATE DRIVER OUTPUT SECTION  
VOH  
VOL  
IO+  
High Level Output Voltage (VBIAS - VO)  
No Load  
No Load  
1.2  
30  
V
mV  
A
Low Level Output Voltage  
Output High, Short-Circuit Pulsed Current(6)  
Output Low, Short-Circuit Pulsed Current(6)  
V
HO=0V, VIN=5V, PW 10µs  
HO=15V,VIN=0V, PW 10µs  
3.0  
3.0  
4.0  
4.0  
IO-  
V
A
Allowable Negative VS pin Voltage for IN  
Signal Propagation to HO  
VS  
-9.8 -7.0  
V
Note:  
6
These parameters guaranteed by design.  
Dynamic Electrical Characteristics  
VDD=VBS=15V, GND=0V, CLOAD=1000pF, TA=25°C, unless otherwise specified.  
Symbol  
Parameter  
Turn-on Propagation Delay Time  
Turn-off Propagation Delay Time  
Turn-on Rise Time  
Conditions  
Min. Typ. Max. Unit  
ton  
toff  
tr  
VS=0V  
VS=0V  
150  
150  
25  
210  
210  
50  
ns  
ns  
ns  
ns  
tf  
Turn-off Fall Time  
15  
40  
.
© 2008 Fairchild Semiconductor Corporation  
FAN7371 Rev. 1.0.2  
www.fairchildsemi.com  
5
Typical Characteristics  
250  
200  
150  
100  
50  
250  
200  
150  
100  
50  
0
-40  
0
-40  
-20  
0
20  
40  
60  
80  
100  
120  
-20  
0
20  
40  
60  
80  
100  
120  
Temperature [°C]  
Temperature [°C]  
Figure 5. Turn-on Propagation Delay  
vs. Temperature  
Figure 6. Turn-off Propagation Delay  
vs. Temperature  
50  
40  
30  
20  
10  
0
50  
40  
30  
20  
10  
0
-40  
-20  
0
20  
40  
60  
80  
100  
120  
-40  
-20  
0
20  
40  
60  
80  
100  
120  
Temperature [°C]  
Temperature [°C]  
Figure 7. Turn-on Rise Time vs. Temperature  
Figure 8. Turn-off Fall Time vs. Temperature  
100  
80  
60  
40  
20  
0
2.0  
1.5  
1.0  
0.5  
0.0  
-40  
-20  
0
20  
40  
60  
80  
100  
120  
-40  
-20  
0
20  
40  
60  
80  
100  
120  
Temperature [°C]  
Temperature [°C]  
Figure 9. Operating VDD Supply Current  
vs. Temperature  
Figure 10. Operating VBS Supply Current  
vs. Temperature  
© 2008 Fairchild Semiconductor Corporation  
FAN7371 Rev. 1.0.2  
www.fairchildsemi.com  
6
Typical Characteristics (Continued)  
9.5  
9.0  
8.5  
8.0  
7.5  
10.0  
9.5  
9.0  
8.5  
8.0  
-40  
-20  
0
20  
40  
60  
80  
100  
120  
-40  
-20  
0
20  
40  
60  
80  
100  
120  
Temperature [°C]  
Temperature [°C]  
Figure 11. VBS UVLO+ vs. Temperature  
Figure 12. VBS UVLO- vs. Temperature  
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
0.0  
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
0.0  
-40  
-20  
0
20  
40  
60  
80  
100  
120  
-40  
-20  
0
20  
40  
60  
80  
100  
120  
Temperature [°C]  
Temperature [°C]  
Figure 13. Logic High Input Voltage vs. Temperature  
Figure 14. Logic Low Input Voltage vs. Temperature  
280  
240  
200  
160  
120  
80  
1.50  
1.25  
1.00  
0.75  
0.50  
0.25  
0.00  
40  
0
-40  
-20  
0
20  
40  
60  
80  
100  
120  
-40  
-20  
0
20  
40  
60  
80  
100  
120  
Temperature [°C]  
Temperature [°C]  
Figure 15. Input Pull-Down Resistance  
vs.Temperature.  
Figure 16. High-Level Output Voltage  
vs. Temperature  
© 2008 Fairchild Semiconductor Corporation  
FAN7371 Rev. 1.0.2  
www.fairchildsemi.com  
7
Typical Characteristics (Continued)  
6.5  
6.0  
5.5  
5.0  
4.5  
4.0  
3.5  
3.0  
2.5  
6.5  
6.0  
5.5  
5.0  
4.5  
4.0  
3.5  
3.0  
2.5  
-40  
-20  
0
20  
40  
60  
80  
100  
120  
-40  
-20  
0
20  
40  
60  
80  
100  
120  
Temperature [°C]  
Temperature [°C]  
Figure 17. Output High, Short-Circuit Pulsed Current  
vs. Temperature  
Figure 18. Output Low, Short-Circuit Pulsed Current  
vs. Temperature  
7
6
5
4
3
2
7
6
5
4
3
2
10  
12  
14  
16  
18  
20  
10  
12  
14  
16  
18  
20  
VBS [V]  
VBS [V]  
Figure 19. Output High, Short-Circuit Pulsed Current  
vs. Supply Voltage  
Figure 20. Output Low, Short-Circuit Pulsed Current  
vs. Supply Voltage  
80  
120  
100  
60  
-40°C  
25°C  
125°C  
80  
60  
40  
-40°C  
40  
25°C  
125°C  
20  
20  
0
0
10  
12  
14  
16  
18  
20  
10  
12  
14  
16  
18  
20  
Supply Voltage [V]  
Supply Voltage [V]  
Figure 21. Quiescent VDD Supply Current  
vs. Supply Voltage  
Figure 22. Quiescent VBS Supply Current  
vs. Supply Voltage  
© 2008 Fairchild Semiconductor Corporation  
FAN7371 Rev. 1.0.2  
www.fairchildsemi.com  
8
Switching Time Definitions  
Timing Diagram  
15V  
50%  
50%  
VDD  
VB  
IN  
15V  
10nF  
10µF  
10µF  
0.1µF  
VS  
ton  
tr  
toff  
tf  
GND  
IN  
FAN7371  
1000pF  
90%  
90%  
HO  
OUT  
10%  
10%  
(A)  
(B)  
Figure 23. Switching Time Test Circuit and Waveform Definitions  
© 2008 Fairchild Semiconductor Corporation  
FAN7371 Rev. 1.0.2  
www.fairchildsemi.com  
9
Physical Dimensions  
5.00  
4.80  
A
0.65  
3.81  
8
5
B
1.75  
6.20  
5.80  
4.00  
3.80  
5.60  
1
4
PIN ONE  
INDICATOR  
1.27  
1.27  
(0.33)  
M
0.25  
C B A  
LAND PATTERN RECOMMENDATION  
SEE DETAIL A  
0.25  
0.10  
0.25  
0.19  
C
1.75 MAX  
0.10  
C
0.51  
0.33  
OPTION A - BEVEL EDGE  
0.50  
x 45°  
GAGE PLANE  
0.25  
R0.10  
R0.10  
OPTION B - NO BEVEL EDGE  
0.36  
NOTES: UNLESS OTHERWISE SPECIFIED  
8°  
0°  
A) THIS PACKAGE CONFORMS TO JEDEC  
MS-012, VARIATION AA, ISSUE C,  
B) ALL DIMENSIONS ARE IN MILLIMETERS.  
C) DIMENSIONS DO NOT INCLUDE MOLD  
FLASH OR BURRS.  
D) LANDPATTERN STANDARD: SOIC127P600X175-8M.  
E) DRAWING FILENAME: M08AREV13  
SEATING PLANE  
0.90  
(1.04)  
0.406  
DETAIL A  
SCALE: 2:1  
Figure 24. 8-Lead Small Outline Package (SOP)  
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner  
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or  
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,  
specifically the warranty therein, which covers Fairchild products.  
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:  
http://www.fairchildsemi.com/packaging/.  
© 2008 Fairchild Semiconductor Corporation  
FAN7371 Rev. 1.0.2  
www.fairchildsemi.com  
10  
© 2008 Fairchild Semiconductor Corporation  
FAN7371 Rev. 1.0.2  
www.fairchildsemi.com  
12  

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