FAN8400BD3TF [FAIRCHILD]
MOTOR CONTROLLER ; 电机控制器\n
| 型号： | FAN8400BD3TF |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | MOTOR CONTROLLER
|
| 文件： | 总14页 (文件大小：69K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
www.fairchildsemi.com
FAN8400D (FAN8400BD3)
3-Phase BLDC Motor Driver with PLL
Features
Description
• 3-Phase BLDC motor driver IC with speed control
• Phase Locked Loop (PLL) speed control
• Built-in phase locked detector output
• Current linear drive scheme
• External clock for arbitrary motor speed
• Built-in FG amplifier and integrating amplifier
• Auto Gain Control (AGC) circuit for compensation hall
amplifier
The FAN8400D is a monolithic integrated circuit. it is one
driver for laser beam printer (LBP) polygon mirror motor,
which has single chip implementation of all circuits. For
extremely high rotational precision, it employs the phase
locked loop (PLL) speed control scheme.
28-SSOPH-375SG2
• Built-in protection circuits (over-current limit, under
voltage limit, thermal shut down)
Typical application
Ordering Information
• Polygon mirror motor drive IC for laser beam printer
• Polygon mirror motor drive IC for facsimile
• Polygon mirror motor drive IC for duplicator
• Polygon mirror motor drive IC for multi function printer
• General 3 phase BLDC motor drive IC
Device
Package
Operating Temp
−20°C ~ +80°C
−20°C ~ +80°C
FAN8400BD3 28-SSOPH-375SG2
FAN8400BD3TF 28-SSOPH-375SG2
Rev.1.0.1
©2001 Fairchild Semiconductor Corporation
FAN8400D (FAN8400BD3)
Pin Assignments
1
2
3
28
27
26
AGC
HW-
HW+
HU-
FGIN-
FGS
4
5
25
24
HU+
HV-
HV+
FGOUT
S/S
NC
6
7
23
22
NC
W
FIN
FIN
FAN8400D
V
8
9
21
20
19
SGND
U
LD
10
ECLK
RF
11
12
18
17
PD
EI
PGND
VCC
13
14
16
15
VREG
NC
EO
FC
2
FAN8400D (FAN8400BD3)
Pin Definitions
Pin Number
Pin Name
Pin Function Description
AGC amplifier frequency characteristics correction
FG amplifier inverting input
FG pulse output
1
AGC
2
FG
IN-
3
FG
S
4
FG
FG amplifier output
OUT
5
S/S
Stop and start
6
NC
NC
-
7
-
8
SGND
LD
Signal ground
9
Phase locked loop detector output
External clock
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
ECLK
PD
Phase locked loop detector output
Error amplifier inverting input
Error amplifier output
Control amplifier frequency correction
-
E
I
E
F
O
C
NC
V
REG
Regulator voltage stabilization output
Power supply
V
CC
PGND
Power ground
R
Output current detection
U output
F
U
V
V output
W
W output
H
V hall amplifier non inverting input
V hall amplifier inverting input
U hall amplifier non inverting input
U hall amplifier inverting input
W hall amplifier non inverting input
W hall amplifier inverting input
V+
H
V-
H
U+
H
U-
H
W+
H
W-
3
FAN8400D (FAN8400BD3)
Internal Block Diagram
1
2
3
AGC
28
27
26
AGC
HW-
HW+
HU-
-
FGIN-
FGS
+
+
Hall
AMP
Matrix
-
VREG
4
5
25
24
HU+
HV-
HV+
FGOUT
2
S/S
S/S
NC
6
7
23
22
NC
W
PLL
Output
Controller
FIN
FIN
Clock
V
8
9
21
20
19
SGND
V-type
Control
Lock
Detector
U
LD
10
OCL
ECLK
RF
11
12
18
17
PD
EI
PGND
VCC
TSD &
UVLO
-
+
VREG
13
14
16
15
Regulator
VREG
NC
EO
FC
2
4
FAN8400D (FAN8400BD3)
Absolute Maximum Ratings (Ta = 25°C)
Parameter
Symbol
Value
30
Unit
V
Remark
Maximum supply voltage
Maximum output current
Power dissipation
V
-
-
-
-
-
CCMAX
I
0.6
A
OMAX
Pd
1.7
W
Operating temperature
Storage temperature
T
OPR
−20 ~ +80
−50 ~ +150
°C
°C
T
STG
Recommended Operating Conditions (Ta = 25°C)
Parameter
Symbol
Min.
Typ.
24
Max.
Unit
Operating voltage range
V
CC
20
28
V
5
FAN8400D (FAN8400BD3)
Electrical Characteristics (Ta = 25°C)
Parameter
Symbol
Conditions
Min. Typ.
Max.
Unit
POWER SUPPLY CURRENT
Low power supply current
Typical power supply current
High power supply current
I
Stop mode, V =20V
CC
20
21
22
30
31
32
40
41
42
mA
mA
mA
CCL
CCT
CCH
I
Stop mode, V =24V
CC
I
Stop mode, V =28V
CC
OUTPUT POWER TRANSISTOR CHARACTERISTICS (V
= 3.5V)
I =0.6A, R =0Ω
AGC
U source saturation voltage (1)
U source saturation voltage (2)
U sink saturation voltage (1)
U sink saturation voltage (2)
V source saturation voltage (1)
V source saturation voltage (2)
V sink saturation voltage (1)
V sink saturation voltage (2)
W source saturation voltage (1)
W source saturation voltage (2)
W sink saturation voltage (1)
W sink saturation voltage (2)
U output leakage current
V
V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.8
1.6
0.5
0.25
1.8
1.6
0.5
0.25
1.8
1.6
0.5
0.25
-
2.5
2.3
1.0
0.7
2.5
2.3
1.0
0.7
2.5
2.3
1.0
0.7
100
100
100
V
V
SATUU1
O
F
I =0.3A, R =0Ω
O
SATUU2
F
V
V
I =0.6A, R =0Ω
O
V
SATUL1
SATUL2
SATVU1
SATVU2
F
I =0.3A, R =0Ω
O
V
F
V
V
I =0.6A, R =0Ω
O
V
F
I =0.3A, R =0Ω
O
V
F
V
V
I =0.6A, R =0Ω
O
V
SATVL1
SATVL2
F
I =0.3A, R =0Ω
O
V
F
V
V
I =0.6A, R =0Ω
O
V
SATWU1
SATWU2
F
I =0.3A, R =0Ω
O
V
F
V
V
I =0.6A, R =0Ω
O
V
SATWL1
SATWL2
OLEAKU
F
I =0.3A, R =0Ω
O
V
F
I
V
=28V, U=28V
=28V, V=28V
=28V, W=28V
µA
µA
µA
CC
CC
CC
V output leakage current
I
V
V
-
OLEAKV
W output leakage current
UNDER VOLTAGE LIMIT
UVLO operating voltage
I
-
OLEAKW
V
-
-
7.0
1.0
7.6
1.3
8.2
1.6
V
V
SD
UVLO hysteresis
HV
SD
REGULATOR VOLTAGE OUTPUT
Regulator output voltage
V
-
5.8
6.3
6.8
100
100
V
REG
Power supply variation
H
V
=20~28V
-
-
-
-
mV
mV
VREG1
VREG2
CC
Load variation
H
I
=0~10mA
LOAD
HALL AMPLIFIER INPUT BLOCK
H
H
H
H
H
H
hall AMP input bias current
hall AMP input bias current
hall AMP input bias current
hall AMP input bias current
hall AMP input bias current
hall AMP input bias current
I
I
I
I
I
I
-
-
-
-
-
-
-
-
2
2
2
2
2
2
-
10
10
µA
µA
U+
U−
V+
V−
BHA1+
BHA1−
BHA2+
BHA2−
BHA3+
BHA3−
-
10
µA
-
10
µA
-
10
µA
W+
W−
-
10
µA
Hall differential input range
Hall common input range
V
Sine wave input
50
3.5
350
mVp-p
V
HIN
V
Differential input : 50mVp-p
-
V
-3.5
CC
ICM
6
FAN8400D (FAN8400BD3)
Electrical Characteristics (Continued)
Parameter
Symbol
Conditions
Min.
Typ. Max. Unit
FG AMPLIFIER BLOCK
FG AMP. input bias current
FG AMP. DC bias level
FG output high level voltage
FG output low level voltage
I
-
-
-1
-
1
µA
V
BFG
V
2.90
3.15 3.40
BFG
V
No external load
V
-1.1V
-
-
V
OHFG
REG
V
No external load
-
0.8
1.2
V
OLFG
SHL
FG SCHMIDT COMPARATOR BLOCK
FGS high / low input hysteresis
FGS low / high input hysteresis
FGS hysteresis
V
-
-
-
-
-50
100
100
400
-
0
50
mV
mV
V
150 200
SLH
FGL
V
-
-
200
-
mV
FGS input operating level
FGS output saturation voltage
FGS output leakage current
ERROR AMPLIFIER BLOCK
Error AMP. input bias current
Error AMP. DC bias level
V
mVp-p
V
FGSIL
V
I
=4mA
=28V
CC
0.2
-
0.4
10
FGSSAT
FGS
I
V
-
µA
FGSLEAK
I
-
-
-1
-
1
µA
V
BER
V
2.90
3.15 3.40
BER
Error output high level voltage
Error output low level voltage
CURRENT LIMIT OPERATION
V
No external load
No external load
V
REG
-1.1V
-
-
-
V
OHER
V
-
1.0
V
OLER
R output voltage limit
F
V
V
-
0.55
0.60 0.65
V
RF
CONTROLLER BLOCK
Dead zone
-
-
-
-
-
-
50
-
100 300
mV
mV
-
DZ
Output idle voltage
Forward gain
V
-
5
ID
G
G
0.4
-0.6
0.5
0.6
DF+
DF−
STA
STO
Reverse gain
-0.5 -0.4
-
Accelerate command voltage
Decelerate command voltage
Forward limit voltage
Reverse limit voltage
V
V
REG
-1.1V
-
-
1.5
-
V
V
-
-
-
0.8
V
V
R =22Ω
0.60
0.60
V
L+
F
V
R =22Ω
F
-
V
L−
PHASE COMPARATOR OUTPUT BLOCK
PD output high level voltage
PD output low level voltage
PD output source current
PD output sink current
V
No external load
No external load
5.2
-
-
-
-
-
-
0.7
-0.6
-
V
V
PDH
V
PDL
PD+
I
V
V
=0.5*V
=0.5*V
-
mA
mA
PD
PD
REG
REG
I
1.0
PD−
PHASE LOCKED LOOP DETECTOR OUTPUT BLOCK
LD output saturation voltage
LD output leakage current
V
I
=5mA
LD
-
-
0.1
-
0.4
10
V
LDSAT
I
V
=28V
CC
µA
LDLEAK
7
FAN8400D (FAN8400BD3)
Electrical Characteristics (Continued)
Parameter
Symbol
Conditions
Min.
Typ. Max.
Unit
EXTERNAL CLOCK INPUT BLOCK
External input frequency
ECLK input open voltage
ECLK input high level current
ECLK input low level current
S/S BLOCK
F
External clock mode
-
0.5
3.7
-
7.0
4.7
KHz
V
CLK
V
4.2
IOCLK
IHCLK
I
V
V
=V
CLK REG
100
-400
150
-300
200
-200
µA
µA
I
=0V
CLK
ILCLK
S/S input high level voltage
S/S input low level voltage
S/S hysteresis
V
-
-
-
-
3.0
0
-
V
V
V
IHSS
REG
V
-
1.5
ILSS
V
0.3
3.7
100
-400
0.5
4.2
150
-300
0.7
V
ISSS
S/S input open voltage
S/S input high level current
S/S input low level current
VIOSS
4.7
V
I
V
V
=V
SS REG
200
-200
µA
µA
IHSS
I
=0V
SS
ILSS
8
FAN8400D (FAN8400BD3)
Application Information
1. Output Block
• 3 Phase power transistor and free wheeling diodes
• Reverse active type upper side diodes and parasitic lower side diodes
• full wave current linear drive with current feedback
• Connection with external capacitor to prevent voltage spike and oscillation by current drive
• Output transistor commutation by "Winner takes all" method
• Built in over current limit (OCL) circuit
2. Hall AMP Block
• Detection of rotor position using 3 phase hall sensors
• Determination of output commutation by hall signal
Forward torque [ Reverse torque]
Hall U
Hall V
Hall W
Output U
L [H]
Output V
H [L]
Output W
M [M]
H [L]
H
H
H
L
L
L
H
L
L [H]
M [M]
L [M]
H
H
H
L
L
M [M]
H [L]
H [L]
L
L [H]
M [M]
L [H]
L
H
H
H [L]
M [M]
H [L]
L
M [M]
L [H]
3. AGC Block
• This block is remained output amplitude.
• It is controlled by envelope through hall signals.
1
--------------------
VAGC
H
NI – HI
NOTES:
V
AGC
is voltage of AGC output.
H
NI
is hall non inverting input voltage.
H is hall inverting voltage.
I
4. Speed Control Block
• Digital phase locked loop (PLL) circuit
• Generating error pulse between rising edge of clock and falling edge of FG signal.
• High precision stable speed control
9
FAN8400D (FAN8400BD3)
5. FG AMP & FG Schmidt Comparator Block
• This block measures of motor rotation speed and controls motor speed.
• It is determined FG AMP gain and filter by external component.
• FG schmidt block change sine wave form to square wave form
6. Error AMP Block
• It composes of dumping filter and ripple filter by external component.
• It determines output amplitude of error AMP by width error pulse.
• It is determined output current by output amplitude of error AMP.
• Bidirectional torque control
VRF
VDZ
Reverse
Direction
Forward
Direction
VREG/2
VEO
7. Regulator Block
• Power supply of control circuits in inside.
• Band gap reference circuits.
8. Lock Detector
• It is low when FG frequency reaches capture range of clock frequency.
• Open correct
9. FG Pulse Output
• Monitoring pin for motor rotative speed
• Open correct
10. Stop And Start
• Stop mode: Open or high voltage
• Start mode: Low voltage
10
FAN8400D (FAN8400BD3)
Test Circuits
3.5V
VCC
56K
+
0.1u
1
2
3
28
27
26
-
HW
+
1K
-
HU
+
4
5
25
24
1K
-
HV
VCC
+
6
7
23
22
FAN8400D
VCC
VCC
VCC
8
9
21
20
19
10K
10
22
11
12
18
17
VREG
VCC
10u
13
14
16
15
+
0.1u
+
0.1u
11
FAN8400D (FAN8400BD3)
Typical Application Circuits
1
2
3
28
27
26
-
HW
HU
HV
FG
Sensor
+
FGS
S/S
-
+
4
5
25
24
-
+
6
7
23
22
FAN8400D
M
8
9
21
20
19
LD
ECLK
10
11
12
18
17
VCC
+
13
14
16
15
12
FAN8400D (FAN8400BD3)
13
FAN8400D (FAN8400BD3)
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER
DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
11/7/01 0.0m 001
Stock#DSxxxxxxxx
2001 Fairchild Semiconductor Corporation
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