FDD068AN03L [FAIRCHILD]
N-Channel PowerTrench?? MOSFET 30V, 35A, 6.8mз; N沟道的PowerTrench ？ MOSFET 30V ， 35A ， 6.8mз
| 型号： | FDD068AN03L |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | N-Channel PowerTrench?? MOSFET 30V, 35A, 6.8mз |
| 文件： | 总11页 (文件大小：292K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
December 2003
FDD068AN03L / FDU068AN03L
®
N-Channel PowerTrench MOSFET
30V, 35A, 6.8mΩ
Features
Applications
•
•
•
•
•
•
r
= 5.7mΩ (Typ.), V = 4.5V, I = 35A
•
•
•
•
•
12V Automotive Load Control
Starter / Alternator Systems
Electronic Power Steering Systems
ABS
DS(ON)
GS
D
Q
= 24nC (Typ.), V = 5V
GS
g(5)
Low Miller Charge
Low Q Body Diode
RR
UIS Capability (Single Pulse and Repetitive Pulse)
Qualified to AEC Q101
DC-DC Converters
D
S
D
G
G
I-PAK
S
(TO-251AA)
D-PAK
G D S
(TO-252)
MOSFET Maximum Ratings T = 25°C unless otherwise noted
C
Symbol
Parameter
Ratings
Units
V
V
Drain to Source Voltage
Gate to Source Voltage
30
20
V
V
DSS
GS
Drain Current
o
35
35
A
A
Continuous (T < 154 C, V = 10V)
C
GS
o
I
Continuous (T < 150 C, V = 4.5V)
C GS
D
o
o
Continuous (T
= 25 C, V = 10V, with R = 52 C/W)
θJA
17
A
amb
GS
Pulsed
Figure 4
168
A
E
P
Single Pulse Avalanche Energy (Note 1)
Power dissipation
mJ
W
AS
80
D
o
o
Derate above 25 C
0.53
W/ C
o
T , T
Operating and Storage Temperature
-55 to 175
C
J
STG
Thermal Characteristics
o
R
R
R
Thermal Resistance Junction to Case TO-252, TO-251
1.88
100
52
C/W
θJC
θJA
θJA
o
Thermal Resistance Junction to Ambient TO-252, TO-251
C/W
2
o
Thermal Resistance Junction to Ambient TO-252, 1in copper pad area
C/W
This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. For a
copy of the requirements, see AEC Q101 at: http://www.aecouncil.com/
Reliability data can be found at: http://www.fairchildsemi.com/products/discrete/reliability/index.html.
All Fairchild Semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems
certification.
©2003 Fairchild Semiconductor Corporation
FDD068AN03L / FDU068AN03L Rev. B1
Package Marking and Ordering Information
Device Marking
FDD068AN03L
FDU068AN03L
Device
FDD068AN03L
FDU068AN03L
Package
TO-252AA
TO-251AA
Reel Size
13”
Tape Width
12mm
Quantity
2500 units
75 units
Tube
N/A
Electrical Characteristics T = 25°C unless otherwise noted
C
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
B
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
I
= 250µA, V = 0V
30
-
-
-
-
-
-
V
VDSS
D
GS
V
V
V
= 25V
= 0V
1
DS
GS
GS
I
µA
nA
DSS
GSS
o
T
= 150 C
-
250
100
C
I
= 20V
-
On Characteristics
V
Gate to Source Threshold Voltage
V
= V , I = 250µA
1.2
-
2.5
V
GS(TH)
GS
DS
D
I
I
I
= 35A, V = 10V
-
-
0.0047 0.0057
0.0057 0.0068
D
D
D
GS
= 35A, V = 4.5V
GS
r
Drain to Source On Resistance
Ω
DS(ON)
= 35A, V = 10V,
GS
-
0.0075 0.0092
o
T = 175 C
J
Dynamic Characteristics
C
C
C
R
Input Capacitance
-
-
-
-
-
-
-
-
-
-
2525
490
300
2.1
46
-
-
pF
pF
pF
Ω
nC
nC
nC
nC
nC
nC
ISS
OSS
RSS
G
V
= 15V, V = 0V,
GS
DS
Output Capacitance
f = 1MHz
Reverse Transfer Capacitance
Gate Resistance
-
V
= 0.5V, f = 1MHz
-
GS
Q
Q
Q
Q
Q
Q
Total Gate Charge at 10V
Total Gate Charge at 5V
Threshold Gate Charge
Gate to Source Gate Charge
Gate Charge Threshold to Plateau
Gate to Drain “Miller” Charge
V
V
V
= 0V to 10V
= 0V to 5V
= 0V to 1V
60
32
3.0
-
g(TOT)
g(5)
g(TH)
gs
GS
GS
GS
24
V
= 15V
DD
= 35A
2.3
6.9
4.6
9.8
I
D
I = 1.0mA
g
-
gs2
-
gd
Switching Characteristics (V = 4.5V)
GS
t
t
t
t
t
t
Turn-On Time
Turn-On Delay Time
Rise Time
-
-
-
-
-
-
-
18
171
31
61
-
283
ns
ns
ns
ns
ns
ns
ON
-
d(ON)
-
V
V
= 15V, I = 35A
r
DD
GS
D
= 4.5V, R = 6.2Ω
Turn-Off Delay Time
Fall Time
-
-
GS
d(OFF)
f
Turn-Off Time
137
OFF
Drain-Source Diode Characteristics
I
I
I
I
= 35A
= 15A
-
-
-
-
-
-
-
-
1.25
1.0
27
V
V
SD
SD
SD
SD
V
t
Source to Drain Diode Voltage
SD
Reverse Recovery Time
= 35A, dI /dt = 100A/µs
= 35A, dI /dt = 100A/µs
ns
nC
rr
SD
Q
Reverse Recovered Charge
12
RR
SD
Notes:
1: Starting T = 25°C, L = 0.43mH, I = 28A.
J
AS
©2003 Fairchild Semiconductor Corporation
FDD068AN03L / FDU068AN03L Rev. B1
Typical Characteristics T = 25°C unless otherwise noted
C
1.2
125
1.0
100
CURRENT LIMITED
BY PACKAGE
0.8
75
0.6
50
0.4
25
0.2
0
0
0
25
50
75
100
150
175
125
o
25
50
75
100
125
150
175
o
T
, CASE TEMPERATURE ( C)
C
T
, CASE TEMPERATURE ( C)
C
Figure 1. Normalized Power Dissipation vs
Ambient Temperature
Figure 2. Maximum Continuous Drain Current vs
Case Temperature
2
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
1
0.1
0.05
0.02
0.01
P
DM
0.1
t
1
t
2
NOTES:
DUTY FACTOR: D = t /t
1
2
SINGLE PULSE
0.01
PEAK T = P
x Z
x R
+ T
θJC C
J
DM
θJC
-5
-4
-3
-2
-1
0
1
10
10
10
10
t, RECTANGULAR PULSE DURATION (s)
10
10
10
Figure 3. Normalized Maximum Transient Thermal Impedance
1000
o
T
= 25 C
C
FOR TEMPERATURES
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
o
ABOVE 25 C DERATE PEAK
CURRENT AS FOLLOWS:
V
= 5V
GS
175 - T
150
C
I = I
25
100
30
-5
-4
-3
-2
-1
0
1
10
10
10
10
t, PULSE WIDTH (s)
10
10
10
Figure 4. Peak Current Capability
©2003 Fairchild Semiconductor Corporation
FDD068AN03L / FDU068AN03L Rev. B1
Typical Characteristics T = 25°C unless otherwise noted
C
1000
100
10
500
If R = 0
= (L)(I )/(1.3*RATED BV
t
AV
- V
DD
)
AS
DSS
10µs
If R ≠ 0
t
= (L/R)ln[(I *R)/(1.3*RATED BV
- V ) +1]
DD
AV
AS
DSS
100
100µs
o
STARTING T = 25 C
J
OPERATION IN THIS
AREA MAY BE
10
LIMITED BY r
DS(ON)
1ms
1
10ms
DC
SINGLE PULSE
T
= MAX RATED
o
J
STARTING T = 150 C
J
o
T
= 25 C
C
1
0.01
0.1
1
10
, DRAIN TO SOURCE VOLTAGE (V)
60
0.1
1
10
t , TIME IN AVALANCHE (ms)
AV
100
V
DS
NOTE: Refer to Fairchild Application Notes AN7514 and AN7515
Figure 6. Unclamped Inductive Switching
Capability
Figure 5. Forward Bias Safe Operating Area
100
100
PULSE DURATION = 80µs
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
V
= 4V
GS
DUTY CYCLE = 0.5% MAX
V
= 15V
o
DD
80
60
40
20
0
T = 25 C
C
80
60
40
20
0
V
= 5V
GS
V
= 3V
GS
o
V
= 10V
GS
T
= 25 C
J
V
= 2.5V
o
GS
o
T
= 175 C
J
T
= -55 C
J
0
0.2
V , DRAIN TO SOURCE VOLTAGE (V)
DS
0.4
0.6
0.8
1.5
2.0
2.5
3.0
3.5
V
, GATE TO SOURCE VOLTAGE (V)
GS
Figure 7. Transfer Characteristics
Figure 8. Saturation Characteristics
14
1.6
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
I
= 35A
D
12
10
8
1.4
1.2
1.0
0.8
0.6
6
I
= 1A
D
V
= 5V, I = 35A
D
GS
4
2
4
6
8
10
-80
-40
0
40
80
120
160
200
o
V
, GATE TO SOURCE VOLTAGE (V)
T , JUNCTION TEMPERATURE ( C)
GS
J
Figure 9. Drain to Source On Resistance vs Gate
Voltage and Drain Current
Figure 10. Normalized Drain to Source On
Resistance vs Junction Temperature
©2003 Fairchild Semiconductor Corporation
FDD068AN03L / FDU068AN03L Rev. B1
Typical Characteristics T = 25°C unless otherwise noted
C
1.2
1.0
0.8
0.6
0.4
1.2
1.1
1.0
0.9
I
= 250µA
V
= V , I = 250µA
DS D
D
GS
-80
-40
0
40
80
120
160
200
-80
-40
0
40
80
120
160
200
o
o
T , JUNCTION TEMPERATURE ( C)
T , JUNCTION TEMPERATURE ( C)
J
J
Figure 11. Normalized Gate Threshold Voltage vs
Junction Temperature
Figure 12. Normalized Drain to Source
Breakdown Voltage vs Junction Temperature
5000
10
C
= C + C
GS GD
V
= 15V
ISS
DD
8
6
4
2
0
C
≅ C + C
GD
OSS
DS
1000
C
= C
GD
RSS
WAVEFORMS IN
DESCENDING ORDER:
I
I
= 35A
= 5A
D
D
V
= 0V, f = 1MHz
GS
100
0.1
0
10
20
30
40
50
1
10
30
V
, DRAIN TO SOURCE VOLTAGE (V)
Q , GATE CHARGE (nC)
DS
g
Figure 13. Capacitance vs Drain to Source
Voltage
Figure 14. Gate Charge Waveforms for Constant
Gate Current
©2003 Fairchild Semiconductor Corporation
FDD068AN03L / FDU068AN03L Rev. B1
Test Circuits and Waveforms
V
DS
BV
DSS
t
P
L
V
DS
I
VARY t TO OBTAIN
P
AS
+
-
V
DD
R
REQUIRED PEAK I
G
AS
V
DD
V
GS
DUT
t
P
I
0V
AS
0
0.01Ω
t
AV
Figure 15. Unclamped Energy Test Circuit
Figure 16. Unclamped Energy Waveforms
V
DS
V
Q
DD
g(TOT)
V
GS
V
L
DS
V
= 10V
GS
Q
V
g(5)
GS
+
-
Q
gs2
V
V
= 5V
DD
GS
DUT
V
= 1V
GS
I
g(REF)
0
Q
g(TH)
Q
Q
gs
gd
I
g(REF)
0
Figure 17. Gate Charge Test Circuit
Figure 18. Gate Charge Waveforms
V
DS
t
t
ON
OFF
t
d(OFF)
t
d(ON)
R
L
t
t
f
r
V
DS
90%
90%
+
-
V
GS
V
DD
10%
10%
0
DUT
90%
50%
R
GS
V
GS
50%
PULSE WIDTH
V
10%
GS
0
Figure 19. Switching Time Test Circuit
Figure 20. Switching Time Waveforms
©2003 Fairchild Semiconductor Corporation
FDD068AN03L / FDU068AN03L Rev. B1
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, T , and the
thermal resistance of the heat dissipating path determines
JM
125
100
75
R
= 33.32+ 23.84/(0.268+Area) EQ.2
= 33.32+ 154/(1.73+Area) EQ.3
θJA
the maximum allowable device power dissipation, P , in an
DM
R
application.
Therefore the application’s ambient
θJA
o
o
temperature, T ( C), and thermal resistance R
must be reviewed to ensure that T
( C/W)
A
θJA
is never exceeded.
JM
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.
(T
– T )
A
JM
(EQ. 1)
P
= -----------------------------
50
DM
RθJA
In using surface mount devices such as the TO-252
package, the environment in which it is applied will have a
significant influence on the part’s current and maximum
25
0.01
(0.0645)
0.1
(0.645)
1
10
(6.45)
(64.5)
power dissipation ratings. Precise determination of P
complex and influenced by many factors:
is
DM
2
2
AREA, TOP COPPER AREA in (cm )
Figure 21. Thermal Resistance vs Mounting
Pad Area
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
2. The number of copper layers and the thickness of the
board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
Fairchild provides thermal information to assist the
designer’s preliminary application evaluation. Figure 21
defines the R
for the device as a function of the top
θJA
copper (component side) area. This is for a horizontally
positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Fairchild device
Spice thermal model or manually utilizing the normalized
maximum transient thermal impedance curve.
Thermal resistances corresponding to other copper areas
can be obtained from Figure 21 or by calculation using
Equation 2 or 3. Equation 2 is used for copper area defined
in inches square and equation 3 is for area in centimeters
square. The area, in square inches or square centimeters is
the top copper area including the gate and source pads.
23.84
(0.268 + Area)
R
= 33.32 + ------------------------------------
(EQ. 2)
θJA
θJA
Area in Inches Squared
154
R
= 33.32 + ---------------------------------
(EQ. 3)
(1.73 + Area)
Area in Centimeters Squared
©2003 Fairchild Semiconductor Corporation
FDD068AN03L / FDU068AN03L Rev. B1
PSPICE Electrical Model
.SUBCKT FDD068AN03L 2 1 3 ; rev December 2003
Ca 12 8 2.3e-9
Cb 15 14 2.3e-9
Cin 6 8 2.3e-9
LDRAIN
DPLCAP
5
DRAIN
2
10
RLDRAIN
RSLC1
51
Dbody 7 5 DbodyMOD
Dbreak 5 11 DbreakMOD
Dplcap 10 5 DplcapMOD
DBREAK
11
+
RSLC2
5
ESLC
51
-
+
50
Ebreak 11 7 17 18 32.6
Eds 14 8 5 8 1
Egs 13 8 6 8 1
Esg 6 10 6 8 1
Evthres 6 21 19 8 1
-
17
DBODY
RDRAIN
6
8
EBREAK 18
-
ESG
EVTHRES
+
16
21
+
-
19
8
MWEAK
LGATE
EVTEMP
RGATE
Evtemp 20 6 18 22 1
GATE
1
6
+
-
18
22
MMED
9
20
MSTRO
8
It 8 17 1
RLGATE
LSOURCE
CIN
SOURCE
3
Lgate 1 9 4.6e-9
Ldrain 2 5 1.0e-9
Lsource 3 7 1.7e-9
7
RSOURCE
RLSOURCE
S1A
S2A
RBREAK
12
RLgate 1 9 46
RLdrain 2 5 10
RLsource 3 7 17
15
13
8
14
13
17
18
RVTEMP
19
S1B
S2B
13
CB
CA
Mmed 16 6 8 8 MmedMOD
Mstro 16 6 8 8 MstroMOD
Mweak 16 21 8 8 MweakMOD
IT
14
-
+
+
VBAT
6
8
5
8
EGS
EDS
+
-
-
8
22
Rbreak 17 18 RbreakMOD 1
Rdrain 50 16 RdrainMOD 2.2e-3
Rgate 9 20 2.1
RVTHRES
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
Rsource 8 7 RsourceMOD 2e-3
Rvthres 22 8 RvthresMOD 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2a 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2BMOD
Vbat 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*500),10))}
.MODEL DbodyMOD D (IS=5E-12 IKF=10 N=1.01 RS=2.6e-3 TRS1=8e-4 TRS2=2e-7
+ CJO=8.8e-10 M=0.57 TT=1e-16 XTI=0.9)
.MODEL DbreakMOD D (RS=8e-2 TRS1=1e-3 TRS2=-8.9e-6)
.MODEL DplcapMOD D (CJO=9.4e-10 IS=1e-30 N=10 M=0.4)
.MODEL MmedMOD NMOS (VTO=1.85 KP=10 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=2.1 T_ABS=25)
.MODEL MstroMOD NMOS (VTO=2.34 KP=350 IS=1e-30 N=10 TOX=1 L=1u W=1u T_ABS=25)
.MODEL MweakMOD NMOS (VTO=1.55 KP=0.05 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=21 RS=0.1 T_ABS=25)
.MODEL RbreakMOD RES (TC1=8.3e-4 TC2=-4e-7)
.MODEL RdrainMOD RES (TC1=1e-4 TC2=8e-6)
.MODEL RSLCMOD RES (TC1=9e-4 TC2=1e-6)
.MODEL RsourceMOD RES (TC1=7.5e-3 TC2=1e-6)
.MODEL RvthresMOD RES (TC1=-1.7e-3 TC2=-8.8e-6)
.MODEL RvtempMOD RES (TC1=-2.6e-3 TC2=2e-7)
.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4 VOFF=-3)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3 VOFF=-4)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2 VOFF=-0.5)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.5 VOFF=-2)
.ENDS
Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
©2003 Fairchild Semiconductor Corporation
FDD068AN03L / FDU068AN03L Rev. B1
SABER Electrical Model
rev December 2003
template FDD068AN03L n2,n1,n3 =m_temp
electrical n2,n1,n3
number m_temp=25
{
var i iscl
dp..model dbodymod = (isl=5e-12,ikf=10,nl=1.01,rs=2.6e-3,trs1=8e-4,trs2=2e-7,cjo=8.8e-10,m=0.57,tt=1e-16,xti=0.9)
dp..model dbreakmod = (rs=8e-2,trs1=1e-3,trs2=-8.9e-6)
dp..model dplcapmod = (cjo=9.4e-10,isl=10e-30,nl=10,m=0.4)
m..model mmedmod = (type=_n,vto=1.85,kp=10,is=1e-30, tox=1)
m..model mstrongmod = (type=_n,vto=2.34,kp=350,is=1e-30, tox=1)
m..model mweakmod = (type=_n,vto=1.55,kp=0.05,is=1e-30, tox=1,rs=0.1)
LDRAIN
sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-4,voff=-3)
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-3,voff=-4)
sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-2,voff=-0.5)
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=-0.5,voff=-2)
c.ca n12 n8 = 2.3e-9
c.cb n15 n14 = 2.3e-9
c.cin n6 n8 = 2.3e-9
DPLCAP
5
DRAIN
2
10
RLDRAIN
RSLC1
51
RSLC2
ISCL
DBREAK
11
50
-
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
RDRAIN
6
8
ESG
DBODY
EVTHRES
+
16
21
+
-
19
8
MWEAK
LGATE
EVTEMP
spe.ebreak n11 n7 n17 n18 = 32.6
RGATE
GATE
1
+
6
-
18
22
EBREAK
+
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evthres n6 n21 n19 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
MMED
9
20
MSTRO
8
17
18
-
RLGATE
LSOURCE
CIN
SOURCE
3
7
RSOURCE
RLSOURCE
i.it n8 n17 = 1
S1A
S2A
RBREAK
12
15
13
8
14
13
17
18
l.lgate n1 n9 = 4.6e-9
l.ldrain n2 n5 = 1.0e-9
l.lsource n3 n7 = 1.7e-9
RVTEMP
19
S1B
S2B
13
CB
CA
IT
14
-
+
+
res.rlgate n1 n9 = 46
res.rldrain n2 n5 = 10
res.rlsource n3 n7 = 17
VBAT
6
8
5
8
EGS
EDS
+
-
-
8
22
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u, temp=m_temp
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u, temp=m_temp
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u, temp=m_temp
RVTHRES
res.rbreak n17 n18 = 1, tc1=8.3e-4,tc2=-4e-7
res.rdrain n50 n16 = 2.2e-3, tc1=1e-4,tc2=8e-6
res.rgate n9 n20 = 2.1
res.rslc1 n5 n51 = 1e-6, tc1=9e-4,tc2=1e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 2e-3, tc1=7.5e-3,tc2=1e-6
res.rvthres n22 n8 = 1, tc1=-1.7e-3,tc2=-8.8e-6
res.rvtemp n18 n19 = 1, tc1=-2.6e-3,tc2=2e-7
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/500))** 10))
}
}
©2003 Fairchild Semiconductor Corporation
FDD068AN03L / FDU068AN03L Rev. B1
PSPICE Thermal Model
JUNCTION
th
REV 23 December 2003
FDD068AN03LT
CTHERM1 TH 6 9e-4
CTHERM2 6 5 1e-3
CTHERM3 5 4 2e-3
CTHERM4 4 3 3e-3
CTHERM5 3 2 7e-3
CTHERM6 2 TL 8e-2
RTHERM1
RTHERM2
RTHERM3
RTHERM4
RTHERM5
RTHERM6
CTHERM1
6
RTHERM1 TH 6 3.0e-2
RTHERM2 6 5 1.0e-1
RTHERM3 5 4 1.8e-1
RTHERM4 4 3 2.8e-1
RTHERM5 3 2 4.5e-1
RTHERM6 2 TL 4.6e-1
CTHERM2
CTHERM3
CTHERM4
CTHERM5
CTHERM6
5
SABER Thermal Model
SABER thermal model FDD068AN03LT
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 =9e-4
ctherm.ctherm2 6 5 =1e-3
ctherm.ctherm3 5 4 =2e-3
ctherm.ctherm4 4 3 =3e-3
ctherm.ctherm5 3 2 =7e-3
ctherm.ctherm6 2 tl =8e-2
4
3
2
rtherm.rtherm1 th 6 =3.0e-2
rtherm.rtherm2 6 5 =1.0e-1
rtherm.rtherm3 5 4 =1.8e-1
rtherm.rtherm4 4 3 =2.8e-1
rtherm.rtherm5 3 2 =4.5e-1
rtherm.rtherm6 2 tl =4.6e-1
}
tl
CASE
©2003 Fairchild Semiconductor Corporation
FDD068AN03L / FDU068AN03L Rev. B1
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not
intended to be an exhaustive list of all such trademarks.
ACEx™
FACT Quiet Series™ LittleFET™
Power247™
SuperSOT™-6
SuperSOT™-8
SyncFET™
ActiveArray™
Bottomless™
CoolFET™
FAST®
MICROCOUPLER™ PowerTrench®
FASTr™
FRFET™
MicroFET™
MicroPak™
QFET®
QS™
TinyLogic®
CROSSVOLT™ GlobalOptoisolator™ MICROWIRE™
QT Optoelectronics™ TINYOPTO™
DOME™
GTO™
HiSeC™
I2C™
MSX™
Quiet Series™
TruTranslation™
UHC™
EcoSPARK™
E2CMOS™
EnSigna™
FACT™
MSXPro™
OCX™
RapidConfigure™
RapidConnect™
UltraFET®
ImpliedDisconnect™ OCXPro™
SILENT SWITCHER® VCX™
SMART START™
SPM™
ISOPLANAR™
OPTOLOGIC®
Across the board. Around the world.™ OPTOPLANAR™
The Power Franchise™
PACMAN™
POP™
Stealth™
SuperSOT™-3
Programmable Active Droop™
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR
CORPORATION.
As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, or (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or In
Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Obsolete
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. I5
相关型号：
FDD09PG1EL-K1019
D Subminiature Connector, 9 Contact(s), Male, 0.108 inch Pitch, Solder Terminal, Locking, Receptacle
MOLEX
FDD09PG2ER-K1019
D Subminiature Connector, 9 Contact(s), Male, 0.108 inch Pitch, Solder Terminal, Locking, Receptacle
MOLEX
©2020 ICPDF网 联系我们和版权申明