首页 |元器件品牌

FDU8896_F085 [FAIRCHILD]

Power Field-Effect Transistor, 17A I(D), 30V, 0.0068ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-251AA, ROHS COMPLIANT, IPAK-3;
FDU8896_F085
型号： FDU8896_F085
厂家： FAIRCHILD SEMICONDUCTOR    FAIRCHILD SEMICONDUCTOR
描述：

Power Field-Effect Transistor, 17A I(D), 30V, 0.0068ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-251AA, ROHS COMPLIANT, IPAK-3

开关 晶体管
文件： 总11页 (文件大小：218K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
 查看货源
July 2010  
FDD8896_F085 / FDU8896_F085  
®
N-Channel PowerTrench MOSFET  
30V, 94A, 5.7mΩ  
General Description  
Features  
This N-Channel MOSFET has been designed specifically to  
improve the overall efficiency of DC/DC converters using  
either synchronous or conventional switching PWM  
controllers. It has been optimized for low gate charge, low  
•
•
•
r
= 5.7mΩ, V = 10V, I = 35A  
DS(ON)  
GS D  
r
= 6.8mΩ, V = 4.5V, I = 35A  
DS(ON)  
GS  
D
High performance trench technology for extremely low  
r
r
and fast switching speed.  
DS(ON)  
DS(ON)  
•
Low gate charge  
•
•
•
High power and current handling capability  
Qualified to AEC Q101  
Applications  
•
DC/DC converters  
RoHS Compliant  
D
D
G
S
G
I-PAK  
(TO-251AA)  
D-PAK  
S
G D S  
(TO-252)  
MOSFET Maximum Ratings T = 25°C unless otherwise noted  
C
Symbol  
Parameter  
Ratings  
30  
Units  
V
V
V
V
Drain to Source Voltage  
Gate to Source Voltage  
DSS  
GS  
20  
Drain Current  
Continuous (T = 25 C, V = 10V) (Note 1)  
Continuous (T = 25 C, V = 4.5V) (Note 1)  
C GS  
Continuous (T  
o
94  
85  
A
A
C
GS  
o
I
D
o
o
= 25 C, V = 10V, with R = 52 C/W)  
θJA  
17  
A
amb  
GS  
Pulsed  
Figure 4  
168  
80  
0.53  
A
E
P
Single Pulse Avalanche Energy (Note 2)  
Power dissipation  
Derate above 25 C  
mJ  
W
AS  
D
o
o
W/ C  
o
T , T  
Operating and Storage Temperature  
-55 to 175  
C
J
STG  
Thermal Characteristics  
o
R
R
R
Thermal Resistance Junction to Case TO-252, TO-251  
1.88  
100  
52  
C/W  
θJC  
θJA  
θJA  
o
Thermal Resistance Junction to Ambient TO-252, TO-251  
C/W  
2
o
Thermal Resistance Junction to Ambient TO-252, 1in copper pad area  
C/W  
©2010 Fairchild Semiconductor Corporation  
FDD8896_F085 / FDU8896_F085 Rev. A  
Package Marking and Ordering Information  
Device Marking  
FDD8896  
FDU8896  
Device  
FDD8896_F085  
FDU8896_F085  
Package  
TO-252AA  
TO-251AA  
Reel Size  
13”  
Tube  
Tape Width  
12mm  
Quantity  
2500 units  
75 units  
N/A  
Electrical Characteristics T = 25°C unless otherwise noted  
C
Symbol  
Parameter  
Test Conditions  
Min  
Typ  
Max  
Units  
Off Characteristics  
B
Drain to Source Breakdown Voltage  
Zero Gate Voltage Drain Current  
Gate to Source Leakage Current  
I
= 250μA, V = 0V  
30  
-
-
-
-
-
-
-
1
250  
100  
V
VDSS  
D
GS  
V
V
V
= 24V  
= 0V  
DS  
GS  
GS  
I
I
μA  
nA  
DSS  
o
T
= 150 C  
C
= 20V  
-
GSS  
On Characteristics  
V
Gate to Source Threshold Voltage  
V
= V , I = 250μA  
1.2  
-
2.5  
V
GS(TH)  
GS  
DS  
D
I
I
I
= 35A, V = 10V  
-
-
0.0047 0.0057  
0.0057 0.0068  
D
D
D
GS  
= 35A, V = 4.5V  
GS  
r
Drain to Source On Resistance  
Ω
DS(ON)  
= 35A, V = 10V,  
GS  
-
0.0075 0.0092  
o
T = 175 C  
J
Dynamic Characteristics  
C
C
C
R
Q
Q
Q
Q
Q
Q
Input Capacitance  
Output Capacitance  
Reverse Transfer Capacitance  
Gate Resistance  
Total Gate Charge at 10V  
Total Gate Charge at 5V  
Threshold Gate Charge  
Gate to Source Gate Charge  
Gate Charge Threshold to Plateau  
Gate to Drain “Miller” Charge  
-
-
-
-
-
-
-
-
-
-
2525  
490  
300  
2.1  
46  
-
-
-
pF  
pF  
pF  
Ω
nC  
nC  
nC  
nC  
nC  
nC  
ISS  
OSS  
RSS  
G
V
= 15V, V = 0V,  
GS  
DS  
f = 1MHz  
V
V
V
V
= 0.5V, f = 1MHz  
= 0V to 10V  
-
GS  
GS  
GS  
GS  
60  
32  
3.0  
-
-
-
g(TOT)  
g(5)  
g(TH)  
gs  
= 0V to 5V  
= 0V to 1V  
24  
V
D
= 15V  
DD  
= 35A  
2.3  
6.9  
4.6  
9.8  
I
I = 1.0mA  
g
gs2  
gd  
Switching Characteristics (V = 10V)  
GS  
t
t
t
t
t
t
Turn-On Time  
Turn-On Delay Time  
Rise Time  
Turn-Off Delay Time  
Fall Time  
-
-
-
-
-
-
-
9
106  
53  
41  
-
171  
-
-
-
-
ns  
ns  
ns  
ns  
ns  
ns  
ON  
d(ON)  
V
V
= 15V, I = 35A  
r
DD  
GS  
D
= 10V, R = 6.2Ω  
GS  
d(OFF)  
f
Turn-Off Time  
143  
OFF  
Drain-Source Diode Characteristics  
I
I
I
I
= 35A  
= 15A  
-
-
-
-
-
-
-
-
1.25  
1.0  
27  
V
V
ns  
nC  
SD  
SD  
SD  
SD  
V
Source to Drain Diode Voltage  
SD  
t
Reverse Recovery Time  
Reverse Recovered Charge  
= 35A, dI /dt = 100A/μs  
= 35A, dI /dt = 100A/μs  
rr  
SD  
Q
12  
RR  
SD  
Notes:  
1: Package current limitation is 35A.  
2: Starting T = 25°C, L = 0.43mH, I = 28A, V = 27V, V = 10V.  
J
AS  
DD  
GS  
©2010 Fairchild Semiconductor Corporation  
FDD8896_F085 / FDU8896_F085 Rev. A  
Typical Characteristics T = 25°C unless otherwise noted  
C
1.2  
100  
CURRENT LIMITED  
BY PACKAGE  
1.0  
75  
0.8  
0.6  
50  
0.4  
25  
0.2  
0
0
0
25  
50  
75  
100  
150  
175  
125  
o
25  
50  
75  
100  
125  
150  
175  
T
, CASE TEMPERATURE ( C)  
o
C
T
, CASE TEMPERATURE ( C)  
C
Figure 1. Normalized Power Dissipation vs Case  
Temperature  
Figure 2. Maximum Continuous Drain Current vs  
Case Temperature  
2
DUTY CYCLE - DESCENDING ORDER  
0.5  
1
0.2  
0.1  
0.05  
0.02  
0.01  
P
DM  
0.1  
t
1
t
2
NOTES:  
DUTY FACTOR: D = t /t  
1
2
SINGLE PULSE  
0.01  
PEAK T = P  
x Z  
x R  
+ T  
θJC C  
J
DM  
θJC  
-5  
-4  
-3  
-2  
-1  
0
1
10  
10  
10  
10  
t, RECTANGULAR PULSE DURATION (s)  
10  
10  
10  
Figure 3. Normalized Maximum Transient Thermal Impedance  
1000  
o
T
= 25 C  
C
FOR TEMPERATURES  
ABOVE 25 C DERATE PEAK  
CURRENT AS FOLLOWS:  
TRANSCONDUCTANCE  
MAY LIMIT CURRENT  
IN THIS REGION  
o
V
= 4.5V  
GS  
175 - T  
150  
C
I = I  
25  
100  
30  
-5  
-4  
-3  
-2  
-1  
0
1
10  
10  
10  
10  
t, PULSE WIDTH (s)  
10  
10  
10  
Figure 4. Peak Current Capability  
©2010 Fairchild Semiconductor Corporation  
FDD8896_F085 / FDU8896_F085 Rev. A  
Typical Characteristics T = 25°C unless otherwise noted  
C
1000  
100  
10  
500  
If R = 0  
= (L)(I )/(1.3*RATED BV  
t
- V  
DD  
)
AV  
If R ≠ 0  
AS  
DSS  
10μs  
t
= (L/R)ln[(I *R)/(1.3*RATED BV  
- V ) +1]  
DD  
AV  
AS  
DSS  
100  
100μs  
o
STARTING T = 25 C  
J
OPERATION IN THIS  
AREA MAY BE  
10  
1
LIMITED BY r  
DS(ON)  
1ms  
1
10ms  
DC  
SINGLE PULSE  
T
T
= MAX RATED  
= 25 C  
o
J
STARTING T = 150 C  
J
o
C
0.1  
1
10  
, DRAIN TO SOURCE VOLTAGE (V)  
60  
0.01  
0.1  
1
10  
t , TIME IN AVALANCHE (ms)  
AV  
100  
V
DS  
NOTE: Refer to Fairchild Application Notes AN7514 and AN7515  
Figure 6. Unclamped Inductive Switching  
Capability  
Figure 5. Forward Bias Safe Operating Area  
100  
100  
PULSE DURATION = 80μs  
PULSE DURATION = 80μs  
V
= 4V  
GS  
DUTY CYCLE = 0.5% MAX  
DUTY CYCLE = 0.5% MAX  
o
V
= 15V  
DD  
80  
60  
40  
20  
0
T = 25 C  
C
80  
60  
40  
20  
0
V
= 5V  
GS  
V
= 3V  
GS  
o
V
= 10V  
GS  
T
= 25 C  
J
V
= 2.5V  
o
GS  
o
T
= 175 C  
J
T
= -55 C  
J
0
0.2  
V , DRAIN TO SOURCE VOLTAGE (V)  
DS  
0.4  
0.6  
0.8  
1.5  
2.0  
2.5  
3.0  
3.5  
V
, GATE TO SOURCE VOLTAGE (V)  
GS  
Figure 7. Transfer Characteristics  
Figure 8. Saturation Characteristics  
14  
1.6  
PULSE DURATION = 80μs  
DUTY CYCLE = 0.5% MAX  
PULSE DURATION = 80μs  
DUTY CYCLE = 0.5% MAX  
I
= 35A  
D
12  
10  
8
1.4  
1.2  
1.0  
0.8  
0.6  
6
I
= 1A  
D
V
= 10V, I = 35A  
D
GS  
4
2
4
6
8
10  
-80  
-40  
0
40  
80  
120  
160  
200  
o
V
, GATE TO SOURCE VOLTAGE (V)  
T , JUNCTION TEMPERATURE ( C)  
GS  
J
Figure 9. Drain to Source On Resistance vs Gate  
Voltage and Drain Current  
Figure 10. Normalized Drain to Source On  
Resistance vs Junction Temperature  
©2010 Fairchild Semiconductor Corporation  
FDD8896_F085 / FDU8896_F085 Rev. A  
Typical Characteristics T = 25°C unless otherwise noted  
C
1.2  
1.0  
0.8  
0.6  
0.4  
1.2  
1.1  
1.0  
0.9  
I
= 250μA  
V
= V , I = 250μA  
DS D  
D
GS  
-80  
-40  
0
40  
80  
120  
160  
200  
-80  
-40  
0
40  
80  
120  
o
160  
200  
o
T , JUNCTION TEMPERATURE ( C)  
T , JUNCTION TEMPERATURE ( C)  
J
J
Figure 11. Normalized Gate Threshold Voltage vs  
Junction Temperature  
Figure 12. Normalized Drain to Source  
Breakdown Voltage vs Junction Temperature  
5000  
10  
C
= C + C  
GS GD  
V
= 15V  
ISS  
DD  
8
6
4
2
0
C
≅ C + C  
GD  
OSS  
DS  
1000  
C
= C  
GD  
RSS  
WAVEFORMS IN  
DESCENDING ORDER:  
I
I
= 35A  
= 5A  
D
D
V
= 0V, f = 1MHz  
GS  
100  
0.1  
0
10  
20  
30  
40  
50  
1
10  
30  
V
, DRAIN TO SOURCE VOLTAGE (V)  
Q , GATE CHARGE (nC)  
DS  
g
Figure 13. Capacitance vs Drain to Source  
Voltage  
Figure 14. Gate Charge Waveforms for Constant  
Gate Current  
©2010 Fairchild Semiconductor Corporation  
FDD8896_F085 / FDU8896_F085 Rev. A  
Test Circuits and Waveforms  
V
DS  
BV  
DSS  
t
P
L
V
DS  
I
VARY t TO OBTAIN  
P
AS  
+
-
V
DD  
R
REQUIRED PEAK I  
G
AS  
V
DD  
V
GS  
DUT  
t
P
I
0V  
AS  
0
0.01Ω  
t
AV  
Figure 15. Unclamped Energy Test Circuit  
Figure 16. Unclamped Energy Waveforms  
V
DS  
V
Q
DD  
g(TOT)  
V
GS  
V
L
DS  
V
= 10V  
GS  
Q
V
g(5)  
GS  
+
-
Q
gs2  
V
V
= 5V  
DD  
GS  
DUT  
V
= 1V  
GS  
I
g(REF)  
0
Q
g(TH)  
Q
Q
gs  
gd  
I
g(REF)  
0
Figure 17. Gate Charge Test Circuit  
Figure 18. Gate Charge Waveforms  
V
DS  
t
t
ON  
OFF  
t
d(OFF)  
t
d(ON)  
R
L
t
t
f
r
V
DS  
90%  
90%  
+
-
V
GS  
V
DD  
10%  
10%  
0
DUT  
90%  
50%  
R
GS  
V
GS  
50%  
PULSE WIDTH  
V
10%  
GS  
0
Figure 19. Switching Time Test Circuit  
Figure 20. Switching Time Waveforms  
©2010 Fairchild Semiconductor Corporation  
FDD8896_F085 / FDU8896_F085 Rev. A  
Thermal Resistance vs. Mounting Pad Area  
The maximum rated junction temperature, T , and the  
JM  
125  
100  
75  
thermal resistance of the heat dissipating path determines  
R
= 33.32+ 23.84/(0.268+Area) EQ.2  
= 33.32+ 154/(1.73+Area) EQ.3  
θJA  
the maximum allowable device power dissipation, P , in an  
DM  
R
application.  
Therefore the application’s ambient  
θJA  
o
o
temperature, T ( C), and thermal resistance R  
( C/W)  
A
θJA  
must be reviewed to ensure that T  
is never exceeded.  
JM  
Equation 1 mathematically represents the relationship and  
serves as the basis for establishing the rating of the part.  
(T  
– T )  
JM  
A
(EQ. 1)  
P
= -----------------------------  
50  
DM  
RθJA  
In using surface mount devices such as the TO-252  
package, the environment in which it is applied will have a  
significant influence on the part’s current and maximum  
25  
0.01  
0.1  
(0.645)  
1
10  
(0.0645)  
(6.45)  
(64.5)  
power dissipation ratings. Precise determination of P  
complex and influenced by many factors:  
is  
DM  
2
2
AREA, TOP COPPER AREA in (cm )  
Figure 21. Thermal Resistance vs Mounting  
Pad Area  
1. Mounting pad area onto which the device is attached and  
whether there is copper on one side or both sides of the  
board.  
2. The number of copper layers and the thickness of the  
board.  
3. The use of external heat sinks.  
4. The use of thermal vias.  
5. Air flow and board orientation.  
6. For non steady state applications, the pulse width, the  
duty cycle and the transient thermal response of the part,  
the board and the environment they are in.  
Fairchild provides thermal information to assist the  
designer’s preliminary application evaluation. Figure 21  
defines the R  
for the device as a function of the top  
θJA  
copper (component side) area. This is for a horizontally  
positioned FR-4 board with 1oz copper after 1000 seconds  
of steady state power with no air flow. This graph provides  
the necessary information for calculation of the steady state  
junction temperature or power dissipation. Pulse  
applications can be evaluated using the Fairchild device  
Spice thermal model or manually utilizing the normalized  
maximum transient thermal impedance curve.  
Thermal resistances corresponding to other copper areas  
can be obtained from Figure 21 or by calculation using  
Equation 2 or 3. Equation 2 is used for copper area defined  
in inches square and equation 3 is for area in centimeters  
square. The area, in square inches or square centimeters is  
the top copper area including the gate and source pads.  
23.84  
R
= 33.32 + ------------------------------------  
(EQ. 2)  
θJA  
θJA  
(0.268 + Area)  
Area in Inches Squared  
154  
R
= 33.32 + ---------------------------------  
(EQ. 3)  
(1.73 + Area)  
Area in Centimeters Squared  
©2010 Fairchild Semiconductor Corporation  
FDD8896_F085 / FDU8896_F085 Rev. A  
PSPICE Electrical Model  
.SUBCKT FDD8896 2 1 3 ; rev July 2003  
Ca 12 8 2.3e-9  
Cb 15 14 2.3e-9  
Cin 6 8 2.3e-9  
LDRAIN  
DPLCAP  
5
DRAIN  
2
10  
RLDRAIN  
RSLC1  
51  
Dbody 7 5 DbodyMOD  
Dbreak 5 11 DbreakMOD  
Dplcap 10 5 DplcapMOD  
DBREAK  
11  
+
RSLC2  
5
ESLC  
51  
-
50  
+
17  
Ebreak 11 7 17 18 32.6  
Eds 14 8 5 8 1  
-
DBODY  
RDRAIN  
6
8
EBREAK 18  
-
ESG  
Egs 13 8 6 8 1  
EVTHRES  
+
16  
Esg 6 10 6 8 1  
21  
+
-
19  
MWEAK  
Evthres 6 21 19 8 1  
LGATE  
EVTEMP  
8
RGATE  
Evtemp 20 6 18 22 1  
GATE  
1
6
+
-
18  
22  
MMED  
9
20  
MSTRO  
8
It 8 17 1  
RLGATE  
LSOURCE  
CIN  
SOURCE  
3
Lgate 1 9 4.6e-9  
Ldrain 2 5 1.0e-9  
Lsource 3 7 1.7e-9  
7
RSOURCE  
RLSOURCE  
S1A  
S2A  
RBREAK  
12  
RLgate 1 9 46  
RLdrain 2 5 10  
RLsource 3 7 17  
15  
13  
14  
17  
18  
8
13  
RVTEMP  
19  
S1B  
S2B  
13  
CB  
+
CA  
Mmed 16 6 8 8 MmedMOD  
Mstro 16 6 8 8 MstroMOD  
Mweak 16 21 8 8 MweakMOD  
IT  
14  
-
+
VBAT  
6
8
5
8
EGS  
EDS  
+
-
-
8
22  
Rbreak 17 18 RbreakMOD 1  
Rdrain 50 16 RdrainMOD 2.2e-3  
Rgate 9 20 2.1  
RSLC1 5 51 RSLCMOD 1e-6  
RSLC2 5 50 1e3  
RVTHRES  
Rsource 8 7 RsourceMOD 2e-3  
Rvthres 22 8 RvthresMOD 1  
Rvtemp 18 19 RvtempMOD 1  
S1a 6 12 13 8 S1AMOD  
S1b 13 12 13 8 S1BMOD  
S2a 6 15 14 13 S2AMOD  
S2b 13 15 14 13 S2BMOD  
Vbat 22 19 DC 1  
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*500),10))}  
.MODEL DbodyMOD D (IS=5E-12 IKF=10 N=1.01 RS=2.6e-3 TRS1=8e-4 TRS2=2e-7  
+ CJO=8.8e-10 M=0.57 TT=1e-16 XTI=0.9)  
.MODEL DbreakMOD D (RS=8e-2 TRS1=1e-3 TRS2=-8.9e-6)  
.MODEL DplcapMOD D (CJO=9.4e-10 IS=1e-30 N=10 M=0.4)  
.MODEL MmedMOD NMOS (VTO=1.85 KP=10 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=2.1 T_ABS=25)  
.MODEL MstroMOD NMOS (VTO=2.34 KP=350 IS=1e-30 N=10 TOX=1 L=1u W=1u T_ABS=25)  
.MODEL MweakMOD NMOS (VTO=1.55 KP=0.05 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=21 RS=0.1 T_ABS=25)  
.MODEL RbreakMOD RES (TC1=8.3e-4 TC2=-4e-7)  
.MODEL RdrainMOD RES (TC1=1e-4 TC2=8e-6)  
.MODEL RSLCMOD RES (TC1=9e-4 TC2=1e-6)  
.MODEL RsourceMOD RES (TC1=7.5e-3 TC2=1e-6)  
.MODEL RvthresMOD RES (TC1=-1.7e-3 TC2=-8.8e-6)  
.MODEL RvtempMOD RES (TC1=-2.6e-3 TC2=2e-7)  
.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4 VOFF=-3)  
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3 VOFF=-4)  
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2 VOFF=-0.5)  
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.5 VOFF=-2)  
.ENDS  
Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global  
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank  
Wheatley.  
©2010 Fairchild Semiconductor Corporation  
FDD8896_F085 / FDU8896_F085 Rev. A  
SABER Electrical Model  
rev July 2003  
template FDD8896 n2,n1,n3 =m_temp  
electrical n2,n1,n3  
number m_temp=25  
{
var i iscl  
dp..model dbodymod = (isl=5e-12,ikf=10,nl=1.01,rs=2.6e-3,trs1=8e-4,trs2=2e-7,cjo=8.8e-10,m=0.57,tt=1e-16,xti=0.9)  
dp..model dbreakmod = (rs=8e-2,trs1=1e-3,trs2=-8.9e-6)  
dp..model dplcapmod = (cjo=9.4e-10,isl=10e-30,nl=10,m=0.4)  
m..model mmedmod = (type=_n,vto=1.85,kp=10,is=1e-30, tox=1)  
m..model mstrongmod = (type=_n,vto=2.34,kp=350,is=1e-30, tox=1)  
m..model mweakmod = (type=_n,vto=1.55,kp=0.05,is=1e-30, tox=1,rs=0.1)  
LDRAIN  
sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-4,voff=-3)  
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-3,voff=-4)  
sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-2,voff=-0.5)  
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=-0.5,voff=-2)  
c.ca n12 n8 = 2.3e-9  
DPLCAP  
5
DRAIN  
2
10  
RLDRAIN  
RSLC1  
51  
RSLC2  
c.cb n15 n14 = 2.3e-9  
ISCL  
c.cin n6 n8 = 2.3e-9  
DBREAK  
11  
50  
-
dp.dbody n7 n5 = model=dbodymod  
RDRAIN  
6
8
dp.dbreak n5 n11 = model=dbreakmod  
dp.dplcap n10 n5 = model=dplcapmod  
ESG  
DBODY  
EVTHRES  
+
16  
21  
+
-
19  
MWEAK  
LGATE  
EVTEMP  
8
spe.ebreak n11 n7 n17 n18 = 32.6  
RGATE  
GATE  
+
6
-
18  
22  
EBREAK  
+
spe.eds n14 n8 n5 n8 = 1  
spe.egs n13 n8 n6 n8 = 1  
spe.esg n6 n10 n6 n8 = 1  
spe.evthres n6 n21 n19 n8 = 1  
spe.evtemp n20 n6 n18 n22 = 1  
MMED  
1
9
20  
MSTRO  
8
17  
RLGATE  
18  
LSOURCE  
CIN  
-
SOURCE  
3
7
RSOURCE  
RLSOURCE  
i.it n8 n17 = 1  
S1A  
S2A  
RBREAK  
12  
15  
13  
14  
17  
18  
l.lgate n1 n9 = 4.6e-9  
l.ldrain n2 n5 = 1.0e-9  
l.lsource n3 n7 = 1.7e-9  
8
13  
RVTEMP  
19  
S1B  
S2B  
13  
CB  
+
CA  
IT  
14  
-
+
res.rlgate n1 n9 = 46  
res.rldrain n2 n5 = 10  
res.rlsource n3 n7 = 17  
VBAT  
6
8
5
8
EGS  
EDS  
+
-
-
8
22  
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u, temp=m_temp  
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u, temp=m_temp  
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u, temp=m_temp  
RVTHRES  
res.rbreak n17 n18 = 1, tc1=8.3e-4,tc2=-4e-7  
res.rdrain n50 n16 = 2.2e-3, tc1=1e-4,tc2=8e-6  
res.rgate n9 n20 = 2.1  
res.rslc1 n5 n51 = 1e-6, tc1=9e-4,tc2=1e-6  
res.rslc2 n5 n50 = 1e3  
res.rsource n8 n7 = 2e-3, tc1=7.5e-3,tc2=1e-6  
res.rvthres n22 n8 = 1, tc1=-1.7e-3,tc2=-8.8e-6  
res.rvtemp n18 n19 = 1, tc1=-2.6e-3,tc2=2e-7  
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod  
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod  
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod  
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod  
v.vbat n22 n19 = dc=1  
equations {  
i (n51->n50) +=iscl  
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/500))** 10))  
}
}
©2010 Fairchild Semiconductor Corporation  
FDD8896_F085 / FDU8896_F085 Rev. A  
PSPICE Thermal Model  
JUNCTION  
th  
REV 23 July 2003  
FDD8896T  
CTHERM1 TH 6 9e-4  
CTHERM2 6 5 1e-3  
CTHERM3 5 4 2e-3  
CTHERM4 4 3 3e-3  
CTHERM5 3 2 7e-3  
CTHERM6 2 TL 8e-2  
RTHERM1  
RTHERM2  
RTHERM3  
RTHERM4  
RTHERM5  
RTHERM6  
CTHERM1  
6
5
RTHERM1 TH 6 3.0e-2  
RTHERM2 6 5 1.0e-1  
RTHERM3 5 4 1.8e-1  
RTHERM4 4 3 2.8e-1  
RTHERM5 3 2 4.5e-1  
RTHERM6 2 TL 4.6e-1  
CTHERM2  
CTHERM3  
CTHERM4  
CTHERM5  
CTHERM6  
SABER Thermal Model  
SABER thermal model FDD8896T  
template thermal_model th tl  
thermal_c th, tl  
{
ctherm.ctherm1 th 6 =9e-4  
ctherm.ctherm2 6 5 =1e-3  
ctherm.ctherm3 5 4 =2e-3  
ctherm.ctherm4 4 3 =3e-3  
ctherm.ctherm5 3 2 =7e-3  
ctherm.ctherm6 2 tl =8e-2  
4
3
2
rtherm.rtherm1 th 6 =3.0e-2  
rtherm.rtherm2 6 5 =1.0e-1  
rtherm.rtherm3 5 4 =1.8e-1  
rtherm.rtherm4 4 3 =2.8e-1  
rtherm.rtherm5 3 2 =4.5e-1  
rtherm.rtherm6 2 tl =4.6e-1  
}
tl  
CASE  
©2010 Fairchild Semiconductor Corporation  
FDD8896_F085 / FDU8896_F085 Rev. A  
TRADEMARKS  
The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not  
intended to be an exhaustive list of all such trademarks.  
®
*
AccuPowerA  
Auto-SPMA  
Build it NowA  
CorePLUSA  
CorePOWERA  
CROSSVOLTA  
CTLA  
F-PFSA  
Power-SPMA  
PowerTrench®  
PowerXS™  
FRFET®  
The Power Franchise®  
Global Power ResourceSM  
Green FPSA  
Green FPSA e-SeriesA  
GmaxA  
GTOA  
IntelliMAXA  
Programmable Active DroopA  
QFET®  
QSA  
Quiet SeriesA  
RapidConfigureA  
A
TinyBoostA  
TinyBuckA  
TinyCalcA  
Current Transfer LogicA  
DEUXPEED®  
Dual Cool™  
TinyLogic®  
ISOPLANARA  
MegaBuckA  
MICROCOUPLERA  
MicroFETA  
TINYOPTOA  
TinyPowerA  
TinyPWMA  
TinyWireA  
TriFault DetectA  
TRUECURRENTA*  
ꢀSerDesA  
Saving our world, 1mW/W/kW at a time™  
SignalWiseA  
EcoSPARK®  
EfficientMaxA  
SmartMaxA  
ESBCA  
MicroPakA  
SMART STARTA  
®
SPM®  
MicroPak2A  
MillerDriveA  
MotionMaxA  
Motion-SPMA  
OptoHiT™  
Fairchild®  
STEALTHA  
Fairchild Semiconductor®  
FACT Quiet SeriesA  
FACT®  
SuperFETA  
SuperSOTA-3  
SuperSOTA-6  
SuperSOTA-8  
SupreMOSA  
OPTOLOGIC®  
UHC®  
FAST®  
OPTOPLANAR®  
Ultra FRFETA  
UniFETA  
VCXA  
FastvCoreA  
®
SyncFETA  
Sync-Lock™  
FETBenchA  
FlashWriter®  
*
PDP SPM™  
VisualMaxA  
XS™  
FPSA  
* Trademarks of System General Corporation, used under license by Fairchild Semiconductor.  
DISCLAIMER  
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE  
RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR  
CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE  
SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN,  
WHICH COVERS THESE PRODUCTS.  
LIFE SUPPORT POLICY  
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE  
EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.  
As used herein:  
1. Life support devices or systems are devices or systems which, (a) are  
intended for surgical implant into the body or (b) support or sustain life,  
and (c) whose failure to perform when properly used in accordance  
with instructions for use provided in the labeling, can be reasonably  
expected to result in a significant injury of the user.  
2. A critical component in any component of a life support, device, or  
system whose failure to perform can be reasonably expected to  
cause the failure of the life support device or system, or to affect its  
safety or effectiveness.  
ANTI-COUNTERFEITING POLICY  
Fairchild Semiconductor Corporation's Anti-Counterfeiting Policy. Fairchild's Anti-Counterfeiting Policy is also stated on our external website, www.fairchildsemi.com,  
under Sales Support.  
Counterfeiting of semiconductor parts is a growing problem in the industry. All manufacturers of semiconductor products are experiencing counterfeiting of their parts.  
Customers who inadvertently purchase counterfeit parts experience many problems such as loss of brand reputation, substandard performance, failed applications,  
and increased cost of production and manufacturing delays. Fairchild is taking strong measures to protect ourselves and our customers from the proliferation of  
counterfeit parts. Fairchild strongly encourages customers to purchase Fairchild parts either directly from Fairchild or from Authorized Fairchild Distributors who are  
listed by country on our web page cited above. Products customers buy either from Fairchild directly or from Authorized Fairchild Distributors are genuine parts, have  
full traceability, meet Fairchild's quality standards for handling and storage and provide access to Fairchild's full range of up-to-date technical and product information.  
Fairchild and our Authorized Distributors will stand behind all warranties and will appropriately address any warranty issues that may arise. Fairchild will not provide  
any warranty coverage or other assistance for parts bought from Unauthorized Sources. Fairchild is committed to combat this global problem and encourage our  
customers to do their part in stopping this practice by buying direct or from authorized distributors.  
PRODUCT STATUS DEFINITIONS  
Definition of Terms  
Datasheet Identification Product Status  
Definition  
Datasheet contains the design specifications for product development. Specifications may change in  
any manner without notice.  
Datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild  
Semiconductor reserves the right to make changes at any time without notice to improve design.  
Datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes  
at any time without notice to improve the design.  
Datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor.  
The datasheet is for reference information only.  
Advance Information  
Preliminary  
Formative / In Design  
First Production  
Full Production  
Not In Production  
No Identification Needed  
Obsolete  
Rev. I48  
© Fairchild Semiconductor Corporation  
www.fairchildsemi.com  

相关型号：

FDUE0640

 Fixed Inductors for Surface Mounting
TOKO

FDUE0640-H-KR15M

 Metal Alloy Inductors
TOKO

FDUE0640-H-KR15M

 Inductor
MURATA

FDUE0640-H-R24M

 Metal Alloy Inductors
TOKO

FDUE0640-H-R42M

 Metal Alloy Inductors
TOKO

FDUE0640-H-R42M

 Inductor
MURATA

FDUE0640-R22M

 Fixed Inductors for Surface Mounting
TOKO

FDUE0640-R42M

 Fixed Inductors for Surface Mounting
TOKO

FDUE0640_16

 Metal Alloy Inductors
TOKO

FDUE0650

 Low audible core noise
TOKO

FDUE0650-H-1R0M

 Low audible core noise
TOKO

FDUE0650-H-R60M

 Low audible core noise
TOKO
©2020 ICPDF网 联系我们和版权申明