FIN24AC [FAIRCHILD]
22-Bit Bi-Directional Serializer/Deserializer; 22位双向串行器/解串器
| 型号： | FIN24AC |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | 22-Bit Bi-Directional Serializer/Deserializer |
| 文件： | 总25页 (文件大小：390K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
January 2007
FIN24AC
tm
22-Bit Bi-Directional Serializer/Deserializer
Features
General Description
■ Low power for minimum impact on battery life
– Multiple power-down modes
The FIN24AC µSerDes™ is a low-power Serializer/
Deserializer (SerDes) that can help minimize the cost
and power of transferring wide signal paths. Through the
use of serialization, the number of signals transferred
from one point to another can be significantly reduced.
Typical reduction is 4:1 to 6:1 for unidirectional paths.
For bi-directional operation, using half duplex for multiple
sources, it is possible to increase the signal reduction to
close to 10:1. Through the use of differential signaling,
shielding and EMI filters can also be minimized, further
reducing the cost of serialization. The differential signal-
ing is also important for providing a noise-insensitive sig-
nal that can withstand radio and electrical noise sources.
Major reduction in power consumption allows minimal
impact on battery life in ultra-portable applications. A
unique word boundary technique assures that the actual
word boundary is identified when the data is deserial-
ized. This guarantees that each word is correctly aligned
at the deserializer on a word-by-word basis through a
unique sequence of clock and data that is not repeated
except at the word boundary. A single PLL is adequate
for most applications, including bi-directional operation.
– AC coupling with DC balance
■ 100nA in standby mode, 5mA typical operating
conditions
■ Cable reduction: 25:4 or greater
■ Bi-directional operation 50:7 reduction or greater
■ Differential signaling:
– -90dBm EMI when using CTL in lab conditions
using a near field probe
– Minimized shielding
– Minimized EMI filter
– Minimum susceptibility to external interference
■ Up to 22 bits in either direction
■ Up to 20MHz parallel interface operation
■ Voltage translation from 1.65V to 3.6V
■ Ultra-small and cost-effective packaging
■ High ESD protection: >8kV HBM
■ Parallel I/O power supply (VDDP) range between
1.65V to 3.6V
Applications
■ Micro-controller or pixel interfaces
■ Image sensors
■ Small displays
– LCD, cell phone, digital camera, portable gaming,
printer, PDA, video camera, automotive
Ordering Information
Package
Order Number
Number
Pb-Free
Package Description
FIN24ACGFX
BGA042
Yes
42-Ball Ultra Small Scale Ball Grid Array (USS-BGA),
JEDEC MO-195, 3.5mm Wide
FIN24ACMLX
MLP040
Yes
40-Terminal Molded Leadless Package (MLP), Quad,
JEDEC MO-220, 6mm Square
Pb-Free package per JEDEC J-STD-020B. BGA and MLP packages available in tape and reel only.
TM
µSerDes is a trademark of Fairchild Semiconductor Corporation.
© 2005 Fairchild Semiconductor Corporation
FIN24AC Rev. 1.0.3
www.fairchildsemi.com
Functional Block Diagram
+
–
CKS0+
CKS0-
Word
Boundary
Generator
PLL
CKREF
0
I
STROBE
cksint
Serializer
DP[21:22]
DP[1:20]
Control
DSO+/DSI-
DSO-/DSI+
+
–
Serializer
oe
100Ω Gated
Termination
+
–
Deserializer
Deserializer
Control
cksint
+
CKSI+
CKSI-
DP[23:24]
CKP
–
100Ω
Termination
WORD CK
Generator
Control Logic
S1
DIRO
Freq.
Control
Direction
Control
S2
oe
DIRI
Power Down
Control
Figure 1. Block Diagram
© 2005 Fairchild Semiconductor Corporation
FIN24AC Rev. 1.0.3
www.fairchildsemi.com
2
Terminal Description
Terminal
Number of
I/O Type Terminals
Name
DP[1:20]
DP[21:22]
DP[23:24]
CKREF
STROBE
CKP
Description of Signals
LVCMOS Parallel I/O, direction controlled by DIRI pin
LVCMOS Parallel Unidirectional Inputs
I/O
20
2
I
O
2
LVCMOS Unidirectional Parallel Outputs
LVCMOS Clock Input and PLL Reference
LVCMOS Strobe Signal for Latching Data into the Serializer
LVCMOS Word Clock Output
CTL Differential Serial I/O Data Signals(1)
DSO: Refers to output signal pair
IN
1
IN
1
OUT
DIFF-I/O
1
DSO+ / DSI–
DSO– / DSI+
2
DSI: Refers to input signal pair
DSO(I)+: Positive signal of DSO(I) pair
DSO(I)–: Negative signal of DSO(I) pair
CKSI+, CKSI–
DIFF-IN
2
2
CTL Differential Deserializer Input Bit Clock
CKSI: Refers to signal pair
CKSI+: Positive signal of CKSI pair
CKSI–: Negative signal of CKSI pair
CKSO+, CKSO– DIFF-OUT
CTL Differential Serializer Output Bit Clock
CKSO: Refers to signal pair
CKSO+: Positive signal of CKSO pair
CKSO–: Negative signal of CKSO pair
S1
S2
IN
IN
IN
1
1
1
LVCMOS Mode Selection terminals used to select
Frequency Range for the RefClock, CKREF
DIRI
LVCMOS Control Input
Used to control direction of Data Flow:
DIRI = “1” Serializer, DIRI = “0” Deserializer
DIRO
OUT
1
LVCMOS Control Output
Inversion of DIRI
VDDP
VDDS
VDDA
GND
Supply
Supply
Supply
Supply
1
1
1
0
Power Supply for Parallel I/O and Translation Circuitry
Power Supply for Core and Serial I/O
Power Supply for Analog PLL Circuitry
Use Bottom Ground Plane for Ground Signals
Note:
1. The DSO/DSI serial port terminals have been arranged such that when one device is rotated 180° to the other device,
the serial connections properly align without the need for any traces or cable signals to cross. Other layout
orientations may require that traces or cables cross.
© 2005 Fairchild Semiconductor Corporation
FIN24AC Rev. 1.0.3
www.fairchildsemi.com
3
Connection Diagrams
DP[9]
DP[10]
DP[11]
DP[12]
VDDP
1
2
3
4
5
6
7
8
9
30 DIRO
29 CKSO+
28 CDSO-
27 DSO+/DSI-
26 DSO-/DSI+
25 CKSI-
24 CKSI+
23 DIRI
CKP
DP[13]
DP[14]
DP[15]
22 S2
21 VDDS
DP[16] 10
Figure 2. Terminal Assignments for MLP (Top View)
Pin Assignments
1
2
3
4
5
6
A
B
C
D
E
F
J
1
2
3
4
5
6
A
B
C
D
E
F
J
DP[9]
DP[11]
CKP
DP[7]
DP[5]
DP[6]
DP[8]
VDDP
GND
DP[3]
DP[2]
DP[4]
GND
VDDS
VDDA
DP[23]
DP[1]
CKREF
DIRO
DP[10]
DP[12]
DP[14]
DP[16]
DP[18]
DP[20]
STROBE
CKSO+
CKSO-
DP[13]
DP[15]
DP[17]
DP[19]
DSO- / DSI+ DSO+ / DSI-
CKSI+
S2
CKSI-
DIRI
S1
DP[21]
DP[22]
DP[24]
(Top View)
Figure 3. Terminal Assignments for µBGA
© 2005 Fairchild Semiconductor Corporation
FIN24AC Rev. 1.0.3
www.fairchildsemi.com
4
Turn-Around Functionality
Control Logic Circuitry
The device passes and inverts the DIRI signal through
the device asynchronously to the DIRO signal. Care
must be taken during design to ensure that no contention
occurs between the deserializer outputs and the other
devices on this port. Optimally the peripheral device driv-
ing the serializer should be in a HIGH-impedance state
prior to the DIRI signal being asserted.
The FIN24AC has the ability to be used as a 24-bit Seri-
alizer or a 24-bit Deserializer. Pins S1 and S2 must be
set to accommodate the clock reference input frequency
range of the serializer. Table 1 shows the pin program-
ming of these options based on the S1 and S2 control
pins. The DIRI pin controls whether the device is a serial-
izer or a deserializer. When DIRI is asserted LOW, the
device is configured as a deserializer. When the DIRI pin
is asserted HIGH, the device is configured as a serial-
izer. Changing the state on the DIRI signal reverses the
direction of the I/O signals and generates the opposite
state signal on DIRO. For unidirectional operation, the
DIRI pin should be hardwired to the HIGH or LOW state
and the DIRO pin should be left floating. For bi-
directional operation, the DIRI of the master device is
driven by the system and the DIRO signal of the master
is used to drive the DIRI of the slave device.
When a device with dedicated data outputs turns from a
deserializer to a serializer, the dedicated outputs remain
at the last logical value asserted. This value only changes
if the device is once again turned around into a deserial-
izer and the values are overwritten.
Power-Down Mode: (Mode 0)
Mode 0 is used for powering down and resetting the
device. When both of the mode signals are driven to a
LOW state, the PLL and references are disabled, differen-
tial input buffers are shut off, differential output buffers are
placed into a HIGH-impedance state, LVCMOS outputs
are placed into a HIGH-impedance state, LVCMOS
inputs are driven to a valid level internally, and all internal
circuitry is reset. The loss of CKREF state is also enabled
to ensure that the PLL only powers up if there is a valid
CKREF signal.
Serializer/Deserializer with Dedicated I/O
Variation
The serialization and deserialization circuitry is setup for
24 bits. Because of the dedicated inputs and outputs,
only 22 bits of data are ever serialized or deserialized.
Regardless of the mode of operation, the serializer is
always sending 24 bits of data and two boundary bits
and the deserializer is always receiving 24 bits of data
and two word boundary bits. Bits 23 and 24 of the serial-
izer always contain the value of zero and are discarded
by the deserializer. DP[21:22] input to the serializer is
deserialized to DP[23:24] respectively.
In a typical application, signals do not change states other
than between the desired frequency range and the power-
down mode. This allows for system-level power-down
functionality to be implemented via a single wire for a
SerDes pair. The S1 and S2 selection signals that have
their operating mode driven to a “logic 0” should be hard-
wired to GND. The S1 and S2 signals that have their
operating mode driven to a “logic 1” should be connected
to a system level power-down signal.
Table 1. Control Logic Circuitry
Mode
Number
S2
S1
DIRI
Description
0
1
0
0
x
1
0
1
0
1
0
Power-Down Mode
0
1
24-Bit Serializer, 2MHz to 5MHz CKREF
24-Bit Deserializer
0
1
2
3
1
0
24-Bit Serializer, 5MHz to 15MHz CKREF
24-Bit Deserializer
1
0
1
1
24-Bit Serializer, 10MHz to 20MHz CKREF
24-Bit Deserializer
1
1
© 2005 Fairchild Semiconductor Corporation
FIN24AC Rev. 1.0.3
www.fairchildsemi.com
5
Serializer Operation Mode
The serializer configurations are described in the following sections. The basic serialization circuitry works essentially
the same in these modes, but the actual data and clock streams differ depending on if CKREF is the same as the
STROBE signal or not. When the CKREF equals STROBE, the CKREF and STROBE signals have an identical fre-
quency of operation, but may or may not be phase aligned. When CKREF does not equal STROBE, each signal is dis-
tinct and CKREF must be running at a frequency high enough to avoid any loss of data condition. CKREF must never
be a lower frequency than STROBE.
The Phase-Locked Loop (PLL) must receive a stable CKREF signal to achieve
lock prior to any valid data being sent. The CKREF signal can be used as the data
STROBE signal, provided that data can be ignored during the PLL lock phase.
Serializer Operation: (Figure 4)
MODE 1, 2, or 3
DIRI = 1,
CKREF = STROBE
Once the PLL is stable and locked, the device can begin to capture and serialize
data. Data is captured on the rising edge of the STROBE signal and serialized.
The serialized data stream is synchronized and sent source synchronously with a
bit clock with an embedded word boundary. When in this mode, the internal dese-
rializer circuitry is disabled; including the serial clock, serial data input buffers, the
bi-directional parallel outputs, and the CKP word clock. The CKP word clock is
driven HIGH.
DPI[1:24] WORD n-1
CKREF
WORD n
WORD n+1
b
b
b
24 25 26
b
b
b
b
b
b
b
b
b
22 23 24 25 26
b
b
b
b
b
5
DSO
1
2
3
4
1
2
3
4
CKS0
WORD n-2
WORD n-1
WORD n
Figure 4. Serializer Timing Diagram (CKREF equals STROBE)
Serializer Operation: (Figure 5),
DIRI = 1,
CKREF does not = STROBE
If the same signal is not used for CKREF and STROBE, the CKREF signal must
be run at a higher frequency than the STROBE rate to serialize the data correctly.
The actual serial transfer rate remains at 26 times the CKREF frequency. A data
bit value of zero is sent when no valid data is present in the serial bit stream. The
operation of the serializer otherwise remains the same.
The exact frequency that the reference clock needs is dependent upon the stabil-
ity of the CKREF and STROBE signal. If the source of the CKREF signal imple-
ments spread spectrum technology, the maximum frequency of this spread
spectrum clock should be used in calculating the ratio of STROBE frequency to
the CKREF frequency. Similarly if the STROBE signal has significant cycle-to-
cycle variation, the maximum cycle-to-cycle time needs to be factored into the
selection of the CKREF frequency.
CKREF
DP[1:24]
STROBE
WORD n-1
WORD n
WORD n+1
DSO
b
b
b
b
b
b
b
b
b
b
b
22 23 24 25 26
b
b
b
b
2 3
1
2
3
4
5
6
7
1
CKS0
No Data
No Data
WORD n-1
WORD n
Figure 5. Serializer Timing Diagram (CKREF does not equal STROBE)
© 2005 Fairchild Semiconductor Corporation
FIN24AC Rev. 1.0.3
www.fairchildsemi.com
6
Serializer Operation Mode (Continued)
A third method of serialization can be accomplished with a free running bit clock
on the CKSI signal. This mode is enabled by grounding the CKREF signal and
driving the DIRI signal HIGH.
Serializer Operation: (Figure 6),
DIRI = 1,
No CKREF
At power-up, the device is configured to accept a serialization clock from CKSI. If
a CKREF is received, this device enables the CKREF serialization mode. The
device remains in this mode even if CKREF is stopped. To re-enable this mode,
the device must be powered down and powered back up with a “logic 0” on
CKREF.
CKSI
DP[1:24]
STROBE
WORD n-1
WORD n
WORD n+1
DSO
b
b
b
b
b
b
b
b
b
b
b
22 23 24 25 26
b
b
b
b
2 3
1
2
3
4
5
6
7
1
CKS0
WORD n-1
WORD n
No Data
No Data
Figure 6. Serializer Timing Diagram Using Provided Bit Clock (No CKREF)
© 2005 Fairchild Semiconductor Corporation
FIN24AC Rev. 1.0.3
www.fairchildsemi.com
7
Deserializer Operation Mode
The operation of the deserializer is only dependent upon the data received on the DSI data signal pair and the CKSI
clock signal pair. The following two sections describe the operation of the deserializer under two distinct serializer
source conditions. References to the CKREF and STROBE signals refer to the signals associated with the serializer
device used in generating the serial data and clock signals that are inputs to the deserializer.
When operating in this mode, the internal serializer circuitry is disabled; including the parallel data input buffers. If there
is a CKREF signal provided, the CKSO serial clock continues to transmit bit clocks. Upon device power-up (S1 or S2 =
1), all deserializer output data pins are driven LOW until valid data is passed through the deserializer.
When the DIRI signal is asserted LOW, the device is configured as a deserializer.
Data is captured on the serial port and deserialized through use of the bit clock
sent with the data. The word boundary is defined in the actual clock and data sig-
nal. Parallel data is generated at the time the word boundary is detected. The fall-
ing edge of CKP occurs approximately six bit times after the falling edge of CKSI.
The rising edge of CKP goes high approximately 13 bit times after CKP goes
LOW. The rising edge of CKP is generated approximately 13 bit times later. When
no embedded word boundary occurs, no pulse is generated on CKP and CKP
remains HIGH.
Deserializer Operation: DIRI = 0
(Serializer Source:
CKREF = STROBE)
WORD n-1
WORD n
WORD n+1
DSI
b
b
b
25 26
b
b
b
b
b
b
b
b
b
b
25 26
b
b
2
24
1
6
7
8
9
19
20
24
1
CKSI
CKPO
DP[1:24]
WORD n-2
WORD n-1
WORD n
Figure 7. Deserializer Timing Diagram (Serializer Source: CKREF equals STROBE)
Deserializer Operation: DIRI = 0
(Serializer Source:
CKREF does not = STROBE)
The logical operation of the deserializer remains the same if the CKREF is equal
in frequency to the STROBE or at a higher frequency than the STROBE. The
actual serial data stream presented to the deserializer, however, differs because it
has non-valid data bits sent between words. The duty cycle of CKP varies based
on the ratio of the frequency of the CKREF signal to the STROBE signal. The fre-
quency of the CKP signal is equal to the STROBE frequency. The falling edge of
CKP will occurs six bit times after the data transition. The LOW time of the CKP
signal is equal to half (13 bit times) of the CKREF period. The CKP HIGH time is
equal to STROBE period – half of the CKREF period. Figure 8 is representative of
a waveform that could be seen when CKREF is not equal to STROBE. If CKREF
is significantly faster, additional non-valid data bits occur between data words.
WORD n-1
WORD n
WORD n+1
b
b
b
25 26
bj bj+1
bj+13 bj+14
b
b b
25 26
0
0
0
0
DSI
24
24
CKSI
13 bit times
WORD n-1
CKPO
6 bit times
DP[1:24]
WORD n-2
WORD n
Figure 8. Deserializer Timing Diagram (Serializer Source: CKREF does not equal STROBE)
© 2005 Fairchild Semiconductor Corporation
FIN24AC Rev. 1.0.3
www.fairchildsemi.com
8
Embedded Word Clock Operation
The FIN24AC sends and receives serial data source
synchronously with a bit clock. The bit clock has been
modified to create a word boundary at the end of each
data word. The word boundary has been implemented
by skipping a low clock pulse. This appears in the serial
clock stream as 3 consecutive bit times where signal
CKSO remains HIGH.
resistor. If a FIN24AC device is configured as an unidi-
rectional serializer, unused data I/O can be treated as
unused inputs. If the FIN24AC is hardwired as a deseri-
alizer, unused data I/O can be treated as unused out-
puts.
From
Deserializer
DP[n]
To implement this sort of scheme, two extra data bits are
required. During the word boundary phase, the data tog-
gles either HIGH-then-LOW or LOW-then-HIGH depen-
dent upon the last bit of the actual data word. Table 2
provides some examples of the actual data word and the
data word with the word boundary bits added. Note that
a 24-bit word is extended to 26-bits during serial trans-
mission. Bit 25 and Bit 26 are defined with-respect-to Bit
24. Bit 25 is always the inverse of Bit 24, and Bit 26 is
always the same as Bit 24. This ensures that a “0” →
“1” and a “1” → “0” transition always occurs during the
embedded word phase where CKSO is HIGH.
To
Serializer
From
Control
Figure 9. LVCMOS I/O
Differential I/O Circuitry
The serializer generates the word boundary data bits
and the boundary clock condition and embeds them into
the serial data stream. The deserializer looks for the end
of the word boundary condition to capture and transfer
the data to the parallel port. The deserializer only uses
the embedded word boundary information to find and
capture the data. These boundary bits are stripped prior
to the word being sent out the parallel port.
The FIN24AC employs FSC proprietary CTL I/O technol-
ogy. CTL is a low-power, low-EMI, differential swing I/O
technology. The CTL output driver generates a constant
output source and sink current. The CTL input receiver
senses the current difference and direction from the out-
put buffer to which it is connected. This differs from
LVDS, which uses a constant current source output, but
a voltage sense receiver. Like LVDS, an input source ter-
mination resistor is required to properly terminate the
transmission line. The FIN24AC device incorporates an
internal termination resistor on the CKSI receiver and a
gated internal termination resistor on the DS input
receiver. The gated termination resistor ensures proper
termination regardless of direction of data flow. The rela-
tively greater sensitivity of the current sense receiver of
CTL allows it to work at much lower current drive and a
much lower voltage.
LVCMOS Data I/O
The LVCMOS input buffers have a nominal threshold
value equal to half VDDP. The input buffers are only oper-
ational when the device is operating as a serializer.
When the device is operating as a deserializer, the inputs
are gated off to conserve power.
The LVCMOS 3-STATE output buffers are rated for a
source/sink current of 2mA at 1.8V. The outputs are
active when the DIRI signal is asserted LOW. When the
DIRI signal is asserted HIGH, the bi-directional LVCMOS
I/Os are in a HIGH-Z state. Under purely capacitive load
During power-down mode, the differential inputs are dis-
abled and powered down and the differential outputs are
placed in a HIGH-Z state. CTL inputs have an inherent
fail-safe capability that supports floating inputs. When
the CKSI input pair of the serializer is unused, it can reli-
ably be left floating. Alternately both of the inputs can be
connected to ground. CTL inputs should never be con-
nected to VDD. When the CKSO output of the deserial-
izer is unused, it should be allowed to float.
conditions, the output swings between GND and VDDP
.
Unused LVCMOS input buffers must be tied off to either a
valid logic LOW or a valid logic HIGH level to prevent
static current draw due to a floating input. Unused LVC-
MOS output should be left floating. Unused bi-directional
pins should be connected to GND through a high-value
Table 2. Word Boundary Data Bits
24-Bit Data Words
24-Bit Data Word with Word Boundary
Hex
3FFFFFh
155555h
xxxxxxh
Binary
Hex
1FFFFFFh
1155555h
1xxxxxxh
Binary
0011 1111 1111 1111 1111 1111b
0101 0101 0101 0101 01010 0101b
0xxx xxxx xxxx xxxx xxxx xxxxb
01 1111 1111 1111 1111 1111 1111b
01 0101 0101 0101 0101 0101 0101b
01 0xxx xxxx xxxx xxxx xxxx xxxxb
© 2005 Fairchild Semiconductor Corporation
FIN24AC Rev. 1.0.3
www.fairchildsemi.com
9
There are two ways to disable the PLL: by entering the
Mode 0 state (S1 = S2 = 0) or by detecting a LOW on
both the S1 and S2 signals. When any of the other
modes are entered by asserting either S1 or S2 HIGH
and by providing a CKREF signal. The PLL powers up
and goes through a lock sequence. Wait the specified
number of clock cycles prior to capturing valid data into
the parallel port. When the µSerDes chipset transitions
from a power-down state (S1, S2 = 0, 0) to a powered
state (example S1, S2 = 1, 1), CKP on the deserializer
transitions LOW for a short duration, then returns HIGH.
Following this, the signal level of the deserializer at CKP
corresponds to the serializer signal levels.
+
–
DS+
DS-
From
Serializer
From
Control
Gated
Termination
(DS Pins Only)
+
–
To
Deserializer
Figure 10. Bi-Directional Differential I/O Circuitry
PLL Circuitry
An alternate way of powering down the PLL is by stop-
ping the CKREF signal either HIGH or LOW. Internal cir-
cuitry detects the lack of transitions and shuts the PLL
and serial I/O down. Internal references,however, are not
disabled, allowing the PLL to power-up and re-lock in a
lesser number of clock cycles than when exiting Mode 0.
When a transition is seen on the CKREF signal, the PLL
is reactivated.
The CKREF input signal is used to provide a reference to
the PLL. The PLL generates internal timing signals capa-
ble of transferring data at 26 times the incoming CKREF
signal. The output of the PLL is a bit clock that is used to
serialize the data. The bit clock is also sent source syn-
chronously with the serial data stream.
© 2005 Fairchild Semiconductor Corporation
FIN24AC Rev. 1.0.3
www.fairchildsemi.com
10
Application Mode Diagrams Unidirectional Data Transfer
BIT CK
Gen.
+
–
+
–
Work CK
Gen
PLL
CKREF_M
CKP_S
Serializer
Control
CKSO
CKSI
Deserializer
Control
STROBE_M
DP[1:12]_M
DS
+
DP[1:12]_S
+
–
Deserializer
Serializer
–
Master Device Operating as a Serializer
DIR = “1”
Slave Device Operating as a Deserializer
DIR = “0”
S2 = S1 = “0”
S2 = S1 = “0”
Figure 11. Simplified Block Diagram for Unidirectional Serializer and Deserializer
Figure 11 shows basic operation when a pair of SerDes is configured in an unidirectional operation mode.
In Master Operation, the device:
In Slave Operation, the device:
1. Is configured as a serializer at power-up based on the
value of the DIRI signal.
1. Is configured as a deserializer at power-up based on
the value of the DIRI signal.
2. Accepts CKREF_M word clock and generates a bit
clock with embedded word boundary. This bit clock is
sent to the slave device through the CKSO port.
2. Accepts an embedded word boundary bit clock on
CKSI.
3. Deserializes the DS data stream using the CKSI input
clock.
3. Receives parallel data on the rising edge of
STROBE_M.
4. Writes parallel data onto the DP_S port and generates
the CKP_S. CKP_S is only generated when a valid
data word occurs.
4. Generates and transmits serialized data on the
DS signals source synchronously with CKSO.
5. Generates an embedded word clock for each strobe
signal.
REFCK
FIN24AC
FIN24AC
CKREF
CKSO
CKSI
DS
CKP
STROBE
DP[21:22]
CNTL[0:1]
CNTL[0:1]
DS
DP[23:24]
DP[1:20]
Sending
Unit
Receiving
Unit
DATA [0:19]
DATA [0:19]
DP[1:20]
VDD
DIRI
S1
DIRI
S1
S2
S2
Note:
Data on serializer pins DP[21:22] is output on pins DP[23:24] of the deserializer.
Figure 12. Unidirectional Serializer and Deserializer
© 2005 Fairchild Semiconductor Corporation
FIN24AC Rev. 1.0.3
www.fairchildsemi.com
11
Base
Unit
FIN24AC
FIN24AC
CKP
DP[23:24]
CKREF
CKSO
DS
CKSI
DS
STROBE
DP[21:22]
DP[1:20]
LCD
Unit
LCD
Camera
Disable
CKSO DP[1:20]
DP[21:22]
CKSI
VSYNC/HSYNC
STROBE
CKREF
VSYNC/HSYNC
DP[23:24]
DIRO
S1
Camera
Unit
DIRO
DIRI
DIRI
S1
S2
S2
GPIO
PwrDwn
Camera/LCD Select
Figure 13. Multiple Units, Unidirectional Signals in Each Direction
Figure 13 shows a half-duplex connectivity diagram. This
connectivity allows for two unidirectional data streams to
be sent across a single pair of SerDes devices. Data is
sent on a frame-by-frame basis. For this mode, there
must be some synchronization between when the cam-
era sends its data frame and when the LCD sends its
data. One option is to have the LCD send data during the
camera blanking period. External logic may be needed
for this mode of operation.
right-hand FIN24AC goes LOW, is sent from the base-
band process to the LCD. The direction is then changed
at DIRO on the right-hand FIN24AC, indicating to the
left-hand FIN24AC to change direction. Data is sent
from the base LCD unit to the LCD. The DIRO pin on the
left-hand FIN24AC is used to indicate to the base control
unit that the signals are changing direction and the LCD
is available to receive data. DIRI on the right-hand
FIN24AC could typically use a timing reference signal,
such as VSYNC from the camera interface, to indicate
direction change. A derivative of this signal may be
required to make sure that no data is lost in the final data
transfer.
Devices alternate frames of data controlled by a direction
control and a direction sense. When DIRI on the right-
hand FIN24AC is HIGH, data is sent from the camera to
the camera interface at the base. When DIRI on the
Flex Circuit Design Guidelines
The serial I/O information is transmitted at a high serial rate. Care must be taken implementing this serial I/O flex
cable. The following best practices should be used when developing the flex cabling or Flex PCB:
■ Keep all four differential wires the same length.
■ Allow no noisy signals over or near differential serial wires. Example: No LVCMOS traces over differential wires.
■ Use only one ground plane or wire over the differential serial wires. Do not run ground over top and bottom.
■ Do not place test points on differential serial wires.
■ Use differential serial wires a minimum of 2cm away from the antenna.
© 2005 Fairchild Semiconductor Corporation
FIN24AC Rev. 1.0.3
www.fairchildsemi.com
12
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be opera-
ble above the recommended operating conditions and stressing the parts to these levels is not recommended. In addi-
tion, extended exposure to stresses above the recommended operating conditions may affect device reliability. The
absolute maximum ratings are stress ratings only.
Symbol
Parameter
Min.
-0.5
-0.5
Max.
+4.6
+4.6
Unit
V
VDD
Supply Voltage
ALL Input/Output Voltage
V
LVDS Output Short-Circuit Duration
Storage Temperature Range
Continuous
TSTG
TJ
-65
+150
+150
+260
°C
°C
°C
kV
kV
Maximum Junction Temperature
Lead Temperature (Soldering, 4 seconds)
TL
All Pins
> 2
ESD
Human Body Model, 1.5kΩ, 100pF
CKSO, CKSI, DSO to GND
> 7.5
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
VDDA, VDDS
VDDP
Parameter
Min.
2.5
Max.
2.9
Unit
V
Supply Voltage
Supply Voltage
1.65
-30
3.6
V
TA
Operating Temperature
Supply Noise Voltage
+70
100
°C
VDDA-PP
mVp-p
© 2005 Fairchild Semiconductor Corporation
FIN24AC Rev. 1.0.3
www.fairchildsemi.com
13
DC Electrical Characteristics
Values are provided for over-supply voltage and operating temperature ranges, unless otherwise specified.
Symbol
Parameter
Test Conditions
Min.
Typ.(2)
Max.
Unit
LVCMOS I/O
V
Input High Voltage
Input Low Voltage
0.65 x V
V
DDP
IH
DDP
V
GND
0.35 x V
V
V
IL
DDP
V
V
V
V
V
V
= 3.3 ± 0.3
= 2.5 ± 0.2
= 1.8 ± 0.15
= 3.3 ± 0.3
= 2.5 ± 0.2
= 1.8 ± 0.15
DDP
DDP
DDP
DDP
DDP
DDP
V
Output High Voltage
I
I
= –2.0 mA
0.75 x V
DDP
OH
OH
V
Output Low Voltage
Input Current
= 2.0 mA
0.25 x V
5.0
V
OL
OL
DDP
I
V
= 0V to 3.6V
–5.0
µA
IN
IN
DIFFERENTIAL I/O
Output High Source
I
V
V
= 1.0V, Figure 14
= 1.0V, Figure 14
–1.75
0.950
±0.1
mA
mA
µA
ODH
OS
Current
I
Output Low Sink Current
ODL
OS
Disabled Output Leakage
Current
CKSO, DSO = 0V to V
S2 = S1 = 0V
,
DDS
I
±5.0
±5.0
OZ
Disabled Input Leakage
Current
CKSI, DSI = 0V to V
S2 = S1 = 0V
,
DDS
I
±0.1
µA
V
IZ
V
Input Common Mode Range V
Input Voltage Ground
= 2.775 ± 5%
V
+ 0.80
ICM
DDS
GO
V
See Figure 15
= 50mV, V = 925mV, DIRI =
0
V
(3)
GO
Off-set Relative to Driver
CKSI Internal Receiver
Termination Resistor
V
ID
IC
R
80.0
80.0
100
100
120
120
Ω
Ω
TRM
TRM
0, | CKSI+ – CKSI- | = V
ID
DSI Internal Receiver,
Termination Resistor
V
= 50mV, V = 925mV, DIRI =
ID IC
R
0, | DSI+ – DSI- | = V
ID
Notes:
2. Typical Values are given for V = 2.775V and T = 25°C. Positive current values refer to the current flowing into device
DD
A
and negative values means current flowing out of pins. Voltage is referenced to GROUND unless otherwise specified
(except ΔV and V ).
OD
OD
3. V
is the difference in device ground levels between the CTL driver and the CTL receiver.
GO
© 2005 Fairchild Semiconductor Corporation
FIN24AC Rev. 1.0.3
www.fairchildsemi.com
14
Power Supply Currents
Symbol
Parameter
Test Conditions
Min.
Typ. Max. Units
V
Serializer Static
All DP and Control Inputs at 0V or V
No CKREF, S2 = 0, S1 = 1, DIR = 1
,
,
,
,
DDA
DD
DD
DD
DD
I
I
I
I
450
550
4.0
4.5
0.1
µA
µA
DDA1
DDA2
DDS1
DDS2
Supply Current
V
Deserializer Static
All DP and Control Inputs at 0V or V
No CKREF, S2 = 0, S1 = 1, DIR = 0
DDA
Supply Current
V
Serializer Static Supply
All DP and Control Inputs at 0V or V
No CKREF, S2 = 0, S1 = 1, DIR = 1
DDS
mA
mA
µA
Current
V
Deserializer Static Supply
All DP and Control Inputs at 0V or V
No CKREF, S2 = 0, S1 = 1, DIR = 0
DDS
Current
V
Power-Down Supply Current
DD
I
S1 = S2 = 0, All Inputs at GND or V
DD
DD_PD
I
= I
+ I
+ I
DD_PD
DDA
DDS DDP
2MHz
5MHz
5MHz
9.0
14.0
9.5
S2 = L
S1 = H
26:1 Dynamic Serializer Power
Supply Current
CKREF = STROBE
DIRI = H
See Figure 16
S2 = H
S1 = L
I
mA
DD_SER1
15MHz
10MHz
20MHz
2MHz
17.0
11.0
15.5
5.5
I
= I
+ I
+ I
DD_SER1
DDA
DDS
DDP
S2 = H
S1 = H
S2 = L
S1 = H
5MHz
6.0
1:26 Dynamic Deserializer Power CKREF = STROBE
5MHz
4.0
S2 = H
S1 = L
I
I
Supply Current
= I
DIRI = L
See Figure 16
mA
mA
DD_DES1
15MHz
10MHz
20MHz
2MHz
5.5
I
+ I
+ I
DDP
DD_DES1
DDA
DDS
7.5
S2 = H
S1 = H
10.0
8.0
NO CKREF
STROBE → Active
CKSI = 15X Strobe
26:1 Dynamic Serializer Power
Supply Current
5MHz
8.5
DD_SER2
10MHz
15MHz
10.0
12.0
I
= I
+ I
+ I
DD_SER2
DDA
DDS DDP
DIRI = H, See Figure 16
AC Electrical Characteristics
Values are provided for over-supply voltage and operating temperature ranges, unless otherwise specified.
Symbol
Parameter
Test Conditions
Min.
Typ.(4)
Max.
Units
SERIALIZER INPUT OPERATING CONDITIONS
t
CKREF Clock Period
(2MHz–20MHz)
See Figure 20
CKREF = STROBE
S2 = 0 S1 = 1
S2 = 1 S1 = 0
S2 = 1 S1 = 1
200
66.0
50.0
T
500
200
100
5.0
ns
TCP
REF
f
CKREF Frequency Relative to CKREF
S2 = 0 S1 = 1 1.1 x f
MHz
ST
Strobe Frequency
does not equal
STROBE
S2 = 1 S1 = 0
15.0
20.0
S2 = 1 S1 = 1
t
CKREF Clock High Time
CKREF Clock Low Time
0.2
0.2
0.5
0.5
T
T
CPWH
t
CPWL
t
LVCMOS Input Transition
Time
See Figure 20
See Figure 20
90.0
ns
CLKT
t
STROBE Pulse Width
HIGH/LOW
(T x 4) / 26
(Tx22) /
26
ns
SPWH
© 2005 Fairchild Semiconductor Corporation
FIN24AC Rev. 1.0.3
www.fairchildsemi.com
15
Symbol
Parameter
Test Conditions
Min.
52.0
130
260
2.5
Typ.(4)
Max.
130
Units
f
Maximum Serial Data Rate
CKREF x 26
S2 = 0 S1 = 1
Mb/s
MAX
S2 = 1 S1 = 0
S2 = 1 S1 = 1
390
520
t
DP Setup to STROBE
DIRI = 1
ns
ns
STC
(n)
t
DP Hold to STROBE
See Figure 9 (f = 5MHz)
2.0
HTC
(n)
f
CKREF Frequency Relative to CKREF Does Not Equal STROBE
Strobe Frequency
1.1 x
20.0
MHz
REF
f
STROBE
SERIALIZER AC ELECTRICAL CHARACTERISTICS
t
Transmitter Clock Input to
Clock Output Delay
See Figure 23, DIRI = 1,
CKREF = STROBE
(5)
33a + 1.5
–50.0
35a + 6.5
250
ns
ps
TCCD
t
CKSO Position Relative to DS See Figure 26
SPOS
PLL AC ELECTRICAL CHARACTERISTICS
t
Serializer PLL Stabilization
Time
See Figure 22
See Figure 27
See Figure 28
200
30.0
20.0
µs
µs
ns
TPLLS0
TPLLD0
TPLLD1
t
t
PLL Disable Time Loss of
Clock
(6)
PLL Power-Down Time
DESERIALIZER INPUT OPERATION CONDITIONS
(7)
(7)
t
Serial Port Setup Time,
DS-to-CKSI
See Figure 25
1.4
ns
ps
S_DS
t
Serial Port Hold Time,
DS-to-CKS
See Figure 25
–250
H_DS
DESERIALIZER AC ELECTRICAL CHARACTERISTICS
t
Deserializer Clock Output
(CKP OUT) Period
See Figure 21
50.0
T
500
ns
RCOP
t
CKP OUT Low Time
CKP OUT High Time
See Figure 21 (Rising Edge Strobe)
Serializer Source STROBE = CKREF
where a = (1/f) / 26
13a-3
13a-3
13a+3
13a+3
ns
ns
RCOL
t
RCOH
(8)
t
Data Valid to CKP LOW
See Figure 21 (Rising Edge Strobe)
where a = (1/f) / 26
8a-6
8a+1
ns
ns
ns
PDV
(8)
t
t
Output Rise Time
(20% to 80%)
C = 5pF, See Figure 18
2.5
2.5
ROLH
ROHL
L
Output Fall Time
(80% to 20%)
Notes:
4. Typical Values are given for VDD = 2.775V and TA = 25°C. Positive current values refer to the current flowing into
device and negative values refer to current flowing out of pins. Voltage is referenced to GROUND unless otherwise
specified (except ΔVOD and VOD).
5. Skew is measured form either the rising or falling edge of CKSO clock to the rising or falling edge of data (DSO).
Signals are edge aligned. Both outputs should have identical load conditions for this test to be valid.
6. The power-downtime is a function of the CKREF frequency prior to CKREF being stopped HIGH or LOW and the
state of the S1/S2 mode pins. The specific number of clock cycles required for the PLL to be disabled varies based
on the operating mode of the device.
7. Signals are transmitted from the serializer source synchronously. In some cases, data is transmitted when the clock
remains at a high state. Skew should only be measured when data and clock are transitioning at the same time. Total
measured input skew is a combination of output skew from the serializer, load variations, and ISI and jitter effects.
8. Rising edge of CKP appears approximately 13 bit times after the falling edge of the CKP output. Falling edge of CKP
occurs approximately eight bit times after a data transition or six bit times after the falling edge of CKSO. Variation of
the data with respect of the CKP signal is due to internal propagation delay differences of the data and CKP path and
propagation delay differences on the various data pins. If the CKREF is not equal to STROBE for the serializer, the
CKP signal does not maintain a 50% duty cycle. The low time of CKP remains 13 bit times.
© 2005 Fairchild Semiconductor Corporation
FIN24AC Rev. 1.0.3
www.fairchildsemi.com
16
Control Logic Timing Controls
Symbol
tPHL_DIR
tPLH_DIR DIRI-to-DIRO
Parameter
Test Conditions
Min. Typ. Max. Units
,
Propagation Delay
DIRI LOW-to-HIGH or HIGH-to-LOW
17.0
25.0
25.0
25.0
2.0
ns
ns
ns
ns
µs
ns
ns
tPLZ, tPHZ Propagation Delay
DIRI-to-DP
DIRI LOW-to-HIGH
DIRI HIGH-to-LOW
tPZL, tPZH Propagation Delay
DIRI-to-DP
tPLZ, tPHZ Deserializer Disable Time: DIRI = 0,
S0 or S1 to DP
S1(2) = 0 and S2(1) = LOW-to-HIGH, Figure 29
tPZL, tPZH Deserializer Enable Time: DIRI = 0,(9)
S0 or S1 to DP
S1(2) = 0 and S2(1) = LOW-to-HIGH, Figure 29
tPLZ, tPHZ Serializer Disable Time:
DIRI = 1,
25.0
65.0
S0 or S1 to CKSO, DS
S1(2) = 0 and S2(1) = HIGH-to-LOW, Figure 28
tPZL, tPZH Serializer Enable Time:
S0 or S1 to CKSO, DS
DIRI = 1,
S1(2) and S2(1) = LOW-to-HIGH, Figure 28
Note:
9. Deserializer Enable Time includes the amount of time required for internal voltage and current references to stabilize.
This time is significantly less than the PLL lock time and does not impact overall system startup time.
Capacitance
Symbol
Parameter
Test Conditions
Min. Typ. Max. Units
CIN
Capacitance of Input Only Signals,
CKREF, STROBE, S1, S2, DIRI
DIRI = 1, S1 = S2 = 0,
VDD = 2.5V
2.0
2.0
2.0
pF
pF
pF
CIO
Capacitance of Parallel Port Pins DP1:12 DIRI = 1, S1 = S2 = 0,
VDD = 2.5V
CIO-DIFF
Capacitance of Differential I/O Signals
DIRI = 0, S1 = S2 = 0,
VDD = 2.775V
© 2005 Fairchild Semiconductor Corporation
FIN24AC Rev. 1.0.3
www.fairchildsemi.com
17
AC Loading and Waveforms
DS+
DUT
DUT
RL/2
+
–
+
–
VOD
Input
RL/2
+
–
VOS
VGO
100Ω Termination
DS-
Figure 15. CTL Input Common Mode Test Circuit
Figure 14. Differential CTL Output DC Test Circuit
T
DP[1:12]
666h
999h
666h
CKREF
CKS0-
CKS0+
DS+
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
2
13
14
1
2
6
7
8
11
12
1
2
6
7
8
11
12
1
DS-
0
1
0
1
0
0
1
1
0
1
0
1
1
0
Note:
The “worst-case” test pattern produces a maximum toggling of internal digital circuits, CTL I/O and LVCMOS I/O with the PLL operating at the reference
frequency, unless otherwise specified. Maximum power is measured at the maximum VDD values. Minimum values are measured at the minimum VDD values.
Typical values are measured at VDD = 2.5V.
Figure 16. “Worst-Case” Serializer Test Pattern
tROHL
tROLH
tTLH
tTHL
80% 80%
80% 80%
20%
20%
DPn
20%
20%
VDIFF
DPn
5pF
VDIFF = (DS+) – (DS-)
DS+
+
1000Ω
5 pF
100Ω
–
DS-
Figure 17. CTL Output Load and Transition Times
Figure 18. LVCMOS Output Load
and Transition Times
© 2005 Fairchild Semiconductor Corporation
FIN24AC Rev. 1.0.3
www.fairchildsemi.com
18
AC Loading and Waveforms (Continued)
Setup Time
tCLKT
tCLKT
tSTC
90%
90%
STROBE
DP[1:12]
Data
10%
10%
tHTC
Hold Time
tTCP
VIH
STROBE
DP[1:12]
CKREF
50%
50%
VIL
tCPWL
Data
tCPWH
Setup: MODE0 = “0” or “1”, MODE1 = “1”, SER/DES = “1”
Figure 20. LVCMOS Clock Parameters
Figure 19. Serial Setup and Hold Time
Data Valid
tPDV
CKP
Data
DP[1:12]
tTPLS0
t
VDD/VDDA
RCOP
S1 or S2
CKREF
75%
50%
50%
CKP
25%
tRCOH
tRCOL
CKS0
EN_DES = “1”, CKSI, and DSI are valid signals.
Setup:
Note: CKREF signal is free running.
Figure 22. Serializer PLL Lock Time
Figure 21. Deserializer Data Valid Window Time
and Clock Output Parameters
tTCCD
STROBE
VDD/2
tRCCD
CKSI-
VDIFF = 0
CKSI+
CKS0-
CKS0+
VDIFF = 0
CKP
VDD/2
Note: STROBE = CKREF
Figure 24. Deserializer Clock Propagation Delay
Figure 23. Serializer Clock Propagation Delay
© 2005 Fairchild Semiconductor Corporation
FIN24AC Rev. 1.0.3
www.fairchildsemi.com
19
AC Loading and Waveforms (Continued)
CKSO-
CKSO+
DSO+
V
= 0
t
t
DIFF
H_DS
S_DS
CKSI-
CKSI+
V
DIFF=0
V
/2
V
= 0
ID
DIFF
DSO-
DSI+
DSI-
t
SK(P-P)
V
V /2
ID
DIFF=0
Note: Data is typically edge aligned with the clock.
Figure 26. Differential Output Signal Skew
Figure 25. Differential Input Setup and Hold Times
tTPPLD0
CKREF
tTPPLD1
S1 or S2
CKS0
CKS0
Note: CKREF Signal can be stopped either HIGH or LOW.
Figure 27. PLL Loss of Clock Disable Time
Figure 28. PLL Power-Down Time
tPLZ(HZ)
S1 or S2
tPZL(ZH)
tPZL(ZH)
tPLZ(HZ)
S1 or S2
DS+,CKS0+
DS-,CKS0-
DP
HIGH-Z
Note: CKREF must be active and PLL must be stable.
Note: If S1(2) transitioning, S2(1) must = 0 for test to be valid.
Figure 29. Serializer Enable and Disable Time
Figure 30. Deserializer Enable and Disable Times
© 2005 Fairchild Semiconductor Corporation
FIN24AC Rev. 1.0.3
www.fairchildsemi.com
20
Tape and Reel Specification
Dimensions are in millimeters unless otherwise noted.
BGA Embossed Tape Dimension
D
P
0
P
2
T
E
F
K
0
W
W
c
B
0
Tc
A
0
D
1
P
1
User Direction of Feed
A
B
D
D
E
F
K
P
P
P
T
T
W
W
C
0
0
1
0
1
0
2
C
±0.1 ±0.1 ±0.05 Min. ±0.1 ±0.1 ±0.1 Typ. Typ. ±0/05 Typ. ±0.005 ±0.3 Typ.
3.5 x 4.5 TBD TBD 1.55 1.5 1.75 5.5 1.1 8.0 4.0 2.0 0.3 0.07 12.0 9.3
Note:
Package
lateral movement requirements (see sketches A, B,
and C).
10. A0, B0, and K0 dimensions are determined with
respect to the EIA/JEDEC RS-481 rotational and
1.0mm
maximum
10° maximum
Typical component
cavity center line
1.0mm
maximum
B0
Typical component
center line
10°maximum component rotation
Sketch A (Side or Front Sectional View)
Sketch C (Top View)
A0
Component Rotation
Component lateral movement
Sketch B (Top View)
Component Rotation
Shipping Reel Dimension
W1 Measured at Hub
W2 max Measured at Hub
B Min
Dia C
Dia D
min
Dia A
max
Dia N
DETAIL AA
See detail AA
W3
Tape
Width
Dia A
Max.
Dim B
Min.
Dia C
+0.5/–0.2
Dia D
Min.
Dim N
Dim W1
+2.0/–0
Dim W2
Max.
Dim W3
(LSL–USL)
Min.
178
178
178
8
330
330
330
1.5
1.5
1.5
13.0
20.2
20.2
20.2
8.4
14.4
18.4
22.4
7.9 ~ 10.4
11.9 ~ 15.4
15.9 ~ 19.4
12
16
13.0
12.4
13.0
16.4
© 2005 Fairchild Semiconductor Corporation
FIN24AC Rev. 1.0.3
www.fairchildsemi.com
21
Tape and Reel Specification (Continued)
Dimensions are in millimeters unless otherwise noted.
MLP Embossed Tape Dimension
D
P
0
P
2
T
E
F
K
0
W
W
c
B
0
Tc
A
0
D
1
P
1
User Direction of Feed
A
B
D
D
E
F
K
P
P
P
T
T
W
W
C
0
0
1
0
1
0
2
C
±0.1 ±0.1 ±0.05 Min. ±0.1 ±0.1 ±0.1 Typ. Typ. ±0/05 Typ. ±0.005 ±0.3 Typ.
Package
5 x 5
6 x 6
5.35 5.35 1.55
6.30 6.30 1.55
1.5
1.5
1.75
1.75
5.5
5.5
1.4
1.4
8
8
4
4
2.0
2.0
0.3
0.3
0.07
0.07
12
12
9.3
9.3
Note:
11. Ao, Bo, and Ko dimensions are determined with respect to the EIA/JEDEC RS-481 rotational and lateral movement
requirements (see sketches A, B, and C).
1.0mm
maximum
10° maximum
Typical component
cavity center line
1.0mm
maximum
B0
Typical component
center line
10° maximum component rotation
Sketch A (Side or Front Sectional View)
Sketch C (Top View)
A0
Sketch B (Top View)
Component Rotation
Component lateral movement
Component Rotation
Shipping Reel Dimension
W1 Measured at Hub
W2 max Measured at Hub
B Min
Dia C
Dia D
min
Dia A
max
Dia N
DETAIL AA
See detail AA
W3
Tape
Width
Dia A
Dim B
Min.
Dia C
+0.5/–0.2
Dia D
Min.
Dim N
Dim W1
+2.0/–0
Dim W2
Max.
Dim W3
(LSL–USL)
Max.
330
330
330
Min.
178
178
178
8
1.5
1.5
1.5
13
13
13
20.2
20.2
20.2
8.4
14.4
18.4
22.4
7.9 ~ 10.4
11.9 ~ 15.4
15.9 ~ 19.4
12
16
12.4
16.4
© 2005 Fairchild Semiconductor Corporation
FIN24AC Rev. 1.0.3
www.fairchildsemi.com
22
Physical Dimensions
Dimensions are in millimeters unless otherwise noted.
2X
0.10
C
3.50
2X
(0.35)
(0.5)
0.10
C
(0.6)
2.5
(0.75)
TERMINAL
A1 CORNER
INDEX AREA
4.50
3.0
0.5
0.5
Ø0.3±0.05
X42
BOTTOM VIEW
0.15
C
C
A B
0.05
0.89±0.082
0.45±0.05
(QA CONTROL VALUE)
1.00 MAX
0.21±0.04
0.10
C
0.08
C
+0.1
0.2
C
0.23±0.05
-0.0
SEATING PLANE
LAND PATTERN
RECOMMENDATION
Figure 31. Pb-Free, 42-Ball, Ultra Small Scale Ball Grid Array (USS-BGA), JEDEC MO-195, 3.5mm Wide
© 2005 Fairchild Semiconductor Corporation
FIN24AC Rev. 1.0.3
www.fairchildsemi.com
23
Physical Dimensions (Continued)
Dimensions are in millimeters unless otherwise noted.
(DATUM A)
Figure 32. Pb-Free, 40-Terminal, Molded Leadless Package (MLP), Quad, JEDEC MO-220, 6mm Square
© 2005 Fairchild Semiconductor Corporation
FIN24AC Rev. 1.0.3
www.fairchildsemi.com
24
© 2005 Fairchild Semiconductor Corporation
FIN24AC Rev. 1.0.3
www.fairchildsemi.com
25
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