FIN424C [FAIRCHILD]
20-Bit Ultra-Low-Power Serializer / Deserializer for μController and RGB Displays; 20位超低功耗串行器/解串器的μController和RGB显示器
| 型号： | FIN424C |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | 20-Bit Ultra-Low-Power Serializer / Deserializer for μController and RGB Displays |
| 文件： | 总10页 (文件大小：327K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
November 2009
FIN424C / FIN425C
20-Bit Ultra-Low-Power Serializer / Deserializer for µController and
RGB Displays
Features
Description
The FIN424C and FIN425C μSerDes™ are a low-power
serializer/ deserializer pair that can help minimize the cost
and power of an LCD interface. They are designed to
operate transparently between the baseband processor and
LCD. /WE and chip-select timing is maintained from the
serializer to the deserializer. Through the use of
serialization, the number of signals transferred from one
point to another can be significantly reduced. Typical
reduction is 5:1. Through the use of differential signaling,
shielding, and EMI filters can also be minimized, further
reducing the cost of serialization. Differential signaling is
important for providing a noise-insensitive signal that can
withstand radio and electrical noise sources. Major reduction
in power consumption allows minimal impact on battery life
in mobile applications.
Data & Control Bits
Frequency
Capability
20
10MHz
QVGA
Interface
Microcontroller / RGB
I86 & m68
µController Usage
Selectable Edge Rates
Dynamic Current
Standby Current
Yes
9mA / Pair
10µA
2.5 to 3.0V
Core Voltage (VDDA/S
)
I/O Voltage (VDDP
)
1.6V to VDDA/S
15KV (IEC)
MLP-32 (5 x 5mm)
FIN424CMLX
FIN425CMLX
ESD
Package
Ordering Information
Applications
Related Resources
Slider, Folder, and Clamshell Mobile Handsets
GSM and CDMA Phones
For more information, please visit:
http://www.fairchildsemi.com/products/interface/userdes.html
Typical Application
Simple Interface
Built-in voltage
translation
Serializer
Deserializer
70-130
Ohms
+
-
+
-
2
2
Main
Baseband
Display
+
-
+
-
Internal
Termination
Figure 1.
Mobile Phone Example
© 2009 Fairchild Semiconductor Corporation
FIN424C / FIN425C • Rev. 1.0.0
www.fairchildsemi.com
FIN424C Serializer Pin Descriptions
Pin Name
Description
STRB
LVCMOS Strobe Signal for Latching Data into the Serializer (On Rising Edge)
LVCMOS Data Input
DP[19:0]
0
1
0
1
Serializer Low Power
/RES
Low-Power Mode
SerDes Standby
Serializer Enabled
Serializer and Deserializer in Low Power
Serializer and Deserializer Enabled
/STBY
Test
Internal Use (Should be GND)
Serial Data Output
DS+, DS-
CKS+, CKS-
VDDP
Serial Clock Output
Power Supply for Parallel I/O and Internal Circuitry
Power Supply for Serial I/O
Power Supply for Core
VDDS
VDDA
GND
Ground Pins
Notes:
1. 0 = VIL; 1 = VIH.
2. All GND and VDDP pins must be connected to ground and VDDP, respectively.
DP[12]
DP[11]
DP[10]
VDDP
DP[9]
CKS+ 1
CKS- 2
VDDS 3
VDDA 4
DS- 5
24
23
22
21
20
GND PAD
Must be Grounded
DS+ 6
19 DP[8]
DP[7]
/RES 7
VDDP 8
18
17 DP[6]
Figure 2.
FIN424CMLX MLP-32 Pinout (Top Through View)
© 2009 Fairchild Semiconductor Corporation
FIN424C / FIN425C • Rev. 1.0.0
www.fairchildsemi.com
2
FIN425C Deserializer Pin Descriptions
Pin Name
Description
WCLK
LVCMOS STRB Output
LVCMOS Data Output
DP[19:0]
0
1
0
1
Deserializer Low Power
Deserializer Enabled
/RES
Low-Power Mode
Slow Output Edge Rates
Fast Output Edge Rates
SLEW
Parallel Output Edge Rate Control
Test
Internal Use (Should be GND)
Serial Data Input
DS+, DS-
CKS+, CKS-
VDDP
Serial Clock Input
Power Supply for Parallel I/O and internal circuitry
Power Supply for Serial I/O
Power Supply for Core
VDDS
VDDA
GND
Ground Pins
Notes:
3. 0 = VIL; 1 = VIH.
4. All GND and VDDP pins must be connected to ground and VDDP, respectively.
DP[12]
DP[11]
DP[10]
VDDP
DP[9]
CKS+ 1
CKS- 2
VDDS 3
24
23
22
21
20
VDDA 4
DS- 5
GND PAD
Must be Grounded
DS+ 6
19 DP[8]
DP[7]
/RES 7
VDDP 8
18
17 DP[6]
Figure 3.
FIN425CMLX MLP-32 Pinout (Top Through View)
© 2009 Fairchild Semiconductor Corporation
FIN424C / FIN425C • Rev. 1.0.0
www.fairchildsemi.com
3
Table 1. Reset and Standby Modes / States
/RES
FIN424C
FIN425C
/STBY
FIN424C
FIN424C Parallel
Input State
FIN425C Parallel
Output State
Mode
Pins
DP[19:0]
Disabled
LOW
0
1
1
X
0
1
Reset Mode
Standby Mode
Operating Mode
STRB / WCLK
DP[19:0]
Disabled
Disabled
Disabled
Enabled
Enabled
HIGH
LAST STATE
HIGH
STRB / WCLK
DP[19:0]
ENABLED
ENABLED
STRB / WCLK
Application Diagram
FIN424C
FIN425C
Main Display
16-Bit µController
/WE
1.8V
2.8V
2.8V
VDDP VDDS/A
WCLK
2.8V
Baseband
Processor
VDDP VDDS/A
A0
DATA[15:0]
RESET
/CS
/WE
STRB
DP[15:0]
DP[16]
DP[17]
DP[18]
DP[19]
DP[15:0]
A0
DP[15:0]
DP[16]
DP[17]
DP[18]
DP[19]
CKS+
CKS-
CKS+
CKS-
Sub-Display
8-Bit µController
/WE
CS1
CS2
DS+
DS-
DS+
DS-
A0
DATA[7:0]
RESET
/CS
Reset
/STBY
/RES
/STBY
Test
Slew
Test
/RES
GND
GND
Figure 4.
Dual-Display, 16-Bit, µController Interface
© 2009 Fairchild Semiconductor Corporation
FIN424C / FIN425C • Rev. 1.0.0
www.fairchildsemi.com
4
FIN424C
FIN425C
1.8V
2.8V
2.8V
2.8V
Baseband
Processor
Main Display
18-Bit µController
VDDP VDDS/A
VDDP VDDS/A
/WE
STRB
WCLK
/WE
DP[17:0]
A0
DP[17:0]
DP[18]
DP[19]
DP[17:0]
DP[18]
DP[19]
CKS+
CKS-
CKS+
CKS-
DATA[17:0]
/A0
CS
CS
DS+
DS-
DS+
DS-
RESET
Reset
/STBY
/RES
/STBY
Test
Slew
Test
/RES
GND
GND
Figure 5.
FIN424C
Single–Display, 18-Bit, µController Interface
FIN425C
1.8V
2.8V
2.8V
VDDP VDDS/A
WCLK
2.8V
Baseband
Processor
Main Display
18-Bit RGB
VDDP VDDS/A
PCLK
STRB
PCLK
DP[17:0]
HSYNC
VSYNC
/CS
DP[17:0]
DP[18]
DP[19]
DP[17:0]
DP[18]
DP[19]
CKS+
CKS-
CKS+
CKS-
DATA[17:0]
HSYNC
VSYNC
/CS
DS+
DS-
DS+
DS-
RESET
Reset
/STBY
/RES
/STBY
Test
Slew
Test
/RES
GND
GND
Figure 6.
Single-Display, 18-Bit, RGB Interface
Additional Application Information
Flex Cabling: The serial I/O information is transmitted at a high serial rate. Care must be taken implementing this serial I/O
flex cable. The following best practices should be used when developing the flex cabling or Flex PCB.
Keep all four differential serial wires the same length.
Do not allow noisy signals over or near differential serial wires. Example: No CMOS traces over differential serial wires.
Use a design goal of 70 to 130Ω differential characteristic impedance.
Do not place test points on differential serial wires.
Design differential serial wires a minimum of 2cm away from the antenna.
Visit Fairchild’s website at http://www.fairchildsemi.com/products/interface/userdes.html, contact your sales
representative, or contact Fairchild directly at interface@fairchildsemi.com for applications notes or flex guidelines.
© 2009 Fairchild Semiconductor Corporation
FIN424C / FIN425C • Rev. 1.0.0
www.fairchildsemi.com
5
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable
above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition,
extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute
maximum ratings are stress ratings only.
Symbol
Parameter
Min.
Max.
Unit
VDD
VIO
TSTG
TJ
Supply Voltage
-0.5
-0.5
-65
+3.6
VDDP+0.5
+150
+150
+260
15.0
V
V
All Input / Output Voltage
Storage Temperature Range
Maximum Junction Temperature
°C
°C
°C
TL
Lead Temperature (Soldering, Four Seconds)
IEC 61000 Board Level
ESD
All Pins
7.5
kV
Human Body Model, JESD22-A114
Serial I/O, /RES, PAR/SPI to GND
14.0
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating
conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend
exceeding them or designing to absolute maximum ratings.
Symbol
Parameter
Min.
Max.
Unit
(5)
VDDA, VDDS
VDDP
Supply Voltage
Supply Voltage
2.5
1.6
-30
3.0
VDDA/S
+85
V
V
TA
Operating Temperature
°C
Notes:
5. VDDA and VDDS supplies must be hardwired together to the same power supply. VDDP must be less than or equal to
DDA/VDDS
V
.
6. Typical values are tested at TA=25°C and 2.75V.
© 2009 Fairchild Semiconductor Corporation
FIN424C / FIN425C • Rev. 1.0.0
www.fairchildsemi.com
6
Electrical Specifications
Values valid for over-supply voltage and operating temperature ranges unless otherwise specified.
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
DC Parallel I/O and Serial Characteristics
VIH
VIL
Input High Voltage
Input Low Voltage
0.7 x VDDP
GND
VDDP
V
V
0.3 x VDDP
SLEW=0 IOH=-250µA
VOH
Output High Voltage
0.8 x VDDP
V
V
SLEW=1 IOH=-1mA
SLEW=0 IOL=250µA
SLEW=1 IOL=1mA
VOL
Output Low Voltage
Input Current
0.2 x VDDP
5
IIN
VGO
Z
-5
µA
V
Serial Input Voltage Ground
Offset
FIN425C to FIN424C
0
Serial Transmission Line Impedance
70
100
130
Ω
Power Characteristics
V
DDA/S=2.75V, VDDP=1.8V,
IDYN_FIN424C Dynamic Current FIN424C
5.44MHz
5.44MHz
4
5
mA
mA
/STBY=1, /RES=1
V
DDA/S=2.75V VDDP=1.8V,
IDYN_FIN425C Dynamic Current FIN425C
/STBY=1, /RES=1, CL=0pF
V
DDA/S=2.75V, VDDP=1.8V, /STBY=1,
IBRST_FIN424C Burst Standby Current FIN424C
IBRST_FIN425C Burst Standby Current FIN425C
1.3
1.8
mA
mA
µA
/RST=1, No STROBE Signal,
V
DDA/S=2.75V, VDDP=1.8V, /STBY=1,
/RST=1, No STROBE Signal, CL=0pF
FIN424C / FIN425C VDDS/A=VDDP=3.0V,
/STBY=0, /RST=1
ISTBY
IRES
Standby Current
Reset Current
10
10
FIN424C / FIN425C VDDS/A=VDDP=3.0V,
/RST=0
µA
AC FIN424C Specifications
fWSTRB0
tR, tF
tS1
Strobe Frequency
Input Edge Rates
DP Setup Time
DP Hold Time
0
10
40
MHz
ns
DP Before STRBn ↑(7)
DP After STRBn ↑(7)
5
ns
tH1
15
ns
AC FIN425C Specifications
SLEW=0, CL=5pF 20% to 80%(7)
SLEW=1, CL=5pF 20% to 80%(7)
SLEW=0, CL=5pF 20% to 80%(7)
SLEW=1, CL=5pF 20% to 80%(7)
8
8
17
10
22
17
tR0, tF0
Output Edge Rates of WCLK
ns
ns
tR1, tF1
Output Edge Rates of DP[19:0]
DP[19:0] to Falling edge of WCLK
CL=5pF 20% to 80%
tcs
0
4
DP
tPWL
WCLK Output Pulse Width Low,
Measured 30% to 30%(7)
tPWL
50
56
ns
WCLK
tCS
AC Oscillator Specifications
fOSC
Serial Operating Frequency
240
275
15
310
30
MHz
µs
VDDA=VDDS=2.75V
/RES=1, /STBY ↑ Transition
Oscillator Stabilization Time After
Standby
tOSC-STBY
© 2009 Fairchild Semiconductor Corporation
FIN424C / FIN425C • Rev. 1.0.0
www.fairchildsemi.com
7
Symbol
Parameter
Test Conditions
VDDA=VDDS=2.75V
/STBY=1, /RES ↑ Transition
Min.
Typ.
Max.
Unit
Oscillator Stabilization Time After
Reset
tOSC-RES
30
50
µs
AC Reset and Standby Timing
tSTRB-RES
tSTRB-RES
0
ns
ns
/RES after last STRBn ↑
/RES
/STBY
STRB
tSTRB-STBY Standby Time After Last Strobe
200
tSTRB-
STBY
tVDD-SKEW
tVDD-RES
tRES-STBY
tOSC-STBY
Allowed Power up Skew between
tVDD-SKEW
-∞
+∞
ms
µs
VDDP and VDDA/S
VDDA/S
VDDP
/RES
Minimum Reset Low Time After
VDD Stable
tVDD-RES
20
/STBY Wait Time After
/RES ↑
/STBY
STRB
tRES-STBY
20
µs
Note:
7. Characterized, but not production tested.
© 2009 Fairchild Semiconductor Corporation
FIN424C / FIN425C • Rev. 1.0.0
www.fairchildsemi.com
8
Physical Dimensions
0.15
C
5.00
B
A
5.00
(0.76)
(0.25 )
PIN #1 IDENT
5.38 MIN
0.15
C
3.37 MAX
3.86 MIN
0.80 MAX
0.20MIN
X4
0.10
C
(0.20)
0.08
C
0.05
0.00
0.28 MAX
X40
0.50TYP
C
SEATING
PLANE
E
3.70
3.50
0.45
0.35
PIN #1 IDENT
PIN #1 ID
0.50
3.70
3.50
PIN #1 ID
(DATUM B)
(DATUM A)
0.18-0.30
0.10
0.05
C
C
A B
0.50
NOTES:
A. CONFORMS TO JEDEC REGISTRATION MO-220, VARIATION
WHHD-4. THIS PACKAGE IS ALSO FOOTPRINT COMPATIBLE WITH
WHHD-5.
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M-1994.
D. LAND PATTERN PER IPC SM-782.
E. WIDTH REDUCED TO AVOID SOLDER BRIDGING.
F. DIMENSIONS ARE NOT INCLUSIVE OF BURRS, MOLD FLASH, OR
TIE BAR PROTRUSIONS.
G. DRAWING FILENAME: MKT-MLP32Arev3.
Figure 7.
32-Lead, Molded Leadless Package (MLP), QUAD, JEDEC MO-220, Variation WHHD-4, 5mm Square
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without
notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the
most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein,
which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
Ordering Information
Operating
Temperature Range
Part Number
Package
Packing Method
Eco Status
Green
32-Lead, Molded Leadless Package (MLP), QUAD,
JEDEC MO-220, Variation WHHD-4, 5mm Square
FIN424CMLX
FIN425CMLX
-30 to +85°C
Tape and Reel
Tape and Reel
32-Lead, Molded Leadless Package (MLP), QUAD,
JEDEC MO-220, Variation WHHD-4, 5mm Square
-30 to +85°C
Green
For Fairchild’s definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.
© 2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FIN424C / FIN425C • Rev. 1.0.0
9
© 2009 Fairchild Semiconductor Corporation
FIN424C / FIN425C • Rev. 1.0.0
www.fairchildsemi.com
10
相关型号：
FIN425CMLX
20-Bit Ultra-Low-Power Serializer / Deserializer for μController and RGB Displays
FAIRCHILD
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