FM27C010V70 [FAIRCHILD]
OTP ROM, 128KX8, 70ns, CMOS, PQCC32, PLASTIC, LCC-32;
| 型号： | FM27C010V70 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | OTP ROM, 128KX8, 70ns, CMOS, PQCC32, PLASTIC, LCC-32 OTP只读存储器 内存集成电路 |
| 文件： | 总14页 (文件大小：142K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
January 2000
FM27C010
1,048,576-Bit (128K x 8) High Performance
CMOS EPROM
TheFM27C010ismanufacturedusingFairchild’sadvancedCMOS
AMG™ EPROM technology.
General Description
The FM27C010 is a high performance, 1,048,576-bit Electrically
Programmable UV Erasable Read Only Memory. It is organized
as 128K-words of 8 bits each. Its pin-compatibility with byte-wide
JEDEC EPROMs enables upgrades through 8 Mbit EPROMs.
The “Don’t Care” feature during read operations allows memory
expansions from 1M to 8M bits with no printed circuit board
changes.
The FM27C010 is one member of a high density EPROM Family
which range in densities up to 4 Megabit.
Features
I High performance CMOS
—70 ns access time
TheFM27C010candirectlyreplacelowerdensity28-pinEPROMs
by adding an A16 address line and VCC jumper. During the normal
read operation PGM and VPP are in a “Don’t Care” state which
allows higher order addresses, such as A17, A18, and A19 to be
connected without affecting the normal read operation. This
allows memory upgrades to 8M bits without hardware changes.
The FM27C010 is also offered in a 32-pin plastic DIP with the
same upgrade path.
I Fast turn-off for microprocessor compatibility
I Simplified upgrade path
—VPP and PGM are “Don’t Care” during normal read
operation
I Manufacturers identification code
I Fast programming
I JEDEC standard pin configurations
—32-pin PDIP package
—32-pin PLCC package
The FM27C010 provides microprocessor-based systems exten-
sive storage capacity for large portions of operating system and
application software. Its 70 ns access time provides no-wait-state
operation with high-performance CPUs. The FM27C010 offers a
single chip solution for the code storage requirements of 100%
firmware-based equipment. Frequently-used software routines
are quickly executed from EPROM storage, greatly enhancing
system utility.
—32-pin CERDIP package
Block Diagram
Data Outputs O - O
0
7
V
CC
GND
V
PP
OE
CE
Output Enable,
Chip Enable, and
Program Logic
Output
Buffers
PGM
Y Decoder
1,048,576-Bit
Cell Matrix
A
- A
16
0
Address
Inputs
X Decoder
DS800032-1
© 2000 Fairchild Semiconductor Corporation
FM27C010
1
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Connection Diagrams
DIP PIN CONFIGURATIONS
DIP
27C256 27C512 27C040
FM27C010
27C040 27C512 27C256
VCC
A18
A17
A14
A13
A8
XX/VPP
A16
XX/VPP
A16
A15
A12
A7
1
VCC
XX/PGM
XX
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
2
VCC
A14
A13
A8
VCC
A14
A15
A12
A7
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
O0
O1
O2
VPP
A12
A7
A6
A5
A4
A3
A2
A1
A0
O0
O1
O2
3
4
A14
A13
A8
A13
5
A8
A6
A6
6
A9
A9
A9
A5
A5
7
A9
A11
OE
A10
A11
A11
OE
A10
A4
A4
8
A11
OE
A10
CE
O7
OE/VPP
A10
A3
A3
9
A2
A2
10
11
12
13
14
15
16
CE/PGMCE/PGM CE/PGM
A1
A1
O7
O6
O5
O4
O3
O7
O6
O5
O4
O3
O7
O6
O5
O4
O3
A0
A0
O0
O1
O2
GND
O0
O6
O1
O5
O2
O4
GND GND
GND
O3
DS800032-10
Note:
Compatible EPROM pin configurations are shown in the blocks adjacent to the FM27C010 pins.
Commercial Temperature Range
(0°C to +70°C) VCC = 5V 10%
Extended Temperature Range
(-40°C to +85°C) VCC = 5V 10%
Parameter/Order Number Access Time (ns)
Parameter/Order Number Access Time (ns)
FM27C010 Q, V, N 90
FM27C010 Q, V, N 120
FM27C010 Q, V, N 150
90
FM27C010 QE, VE, NE 90
FM27C010 QE, VE, NE 120
FM27C010 QE, VE, NE 150
90
120
150
120
150
Pin Names
Package Types: FM27C010 Q, N, V XXX
Q = Quartz-Windowed Ceramic DIP package
V = PLCC package
A0–A16
Addresses
CE
Chip Enable
Output Enable
Outputs
OE
N = Plastic DIP package
O0–O7
PGM
XX
•
•
All packages conform to JEDEC standard.
All versions are guaranteed to function at slower speeds.
Program
Don’t Care (During Read)
PLCC Pin Configuration
4
3
2
1 32 31 30
5
6
7
8
29
28
27
26
25
24
23
22
21
A
A
A
A
A
OE
A
10
CE
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
O
0
14
13
8
9
9
11
10
11
12
13
O
7
14 15 16 17 18 19 20
DS800032-3
Top View
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FM27C010
All Output Voltages with
Absolute Maximum Ratings (Note 1)
Respect to Ground (Note 10) VCC + 1.0V to GND - 0.6V
Storage Temperature
-65°C to +150°C
Operating Range
All Input Voltages Except A9 with
Respect to Ground (Note 10)
-0.6V to +7V
-0.6V to +14V
Range
Commercial
Extended
Temperature
0°C to +70°C
VCC
+5V
+5V
Tolerance
10%
VPP and A9 with Respect to Ground
VCC Supply Voltage with
Respect to Ground
-40°C to +85°C
10%
-0.6V to +7V
>2000V
ESD Protection
DC Read Characteristics Over Operating Range with VPP = VCC
Symbol
VIL
Parameter
Test Conditions
Min
-0.5
2.0
Max
0.8
Units
Input Low Level
V
VIH
Input High Level
VCC +1
0.4
V
VOL
Output Low Voltage
Output High Voltage
IOL = 2.1 mA
V
VOH
IOH = -2.5 mA
3.5
V
ISB1
VCC Standby Current
(CMOS)
CE = VCC 0.3V
100
µA
ISB2
ICC
VCC Standby Current (TTL)
VCC Active Current
CE = VIH
1
mA
mA
CE = OE = VIL
I/O = 0 mA
f = 5 MHz
30
IPP
VPP
ILI
VPP Supply Current
VPP Read Voltage
VPP = VCC
10
VCC
1
µA
V
VCC - 0.7
-1
Input Load Current
Output Leakage Current
VIN = 5.5 or GND
µA
µA
ILO
VOUT = 5.5V or GND
-10
10
AC Read Characteristics Over Operating Range with VPP = VCC
Symbol
Parameter
70
MinMax
90
Min Max
120
150
Units
Min Max
Min Max
tACC
tCE
Address to Output Delay
CE to Output Delay
OE to Output Delay
70
90
120
120
50
150
70
35
30
90
40
35
150
50
tOE
tDF
(Note 2)
Output Disable to Output
Float
35
45
ns
tOH
Output Hold from
(Note 2)
Addresses, CE or OE ,
Whichever Occurred First
0
0
0
0
Capacitance TA = +25°C, f = 1 MHz (Note 2)
Symbol
CIN
Parameter
Input Capacitance
Output Capacitance
Conditions
VIN = 0V
Typ
6
Max Units
15
pF
COUT
VOUT = 0V
10
15
pF
3
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FM27C010
AC Test Conditions
Output Load
1 TTL Gate and CL = 100 pF (Note 8)
Input Rise and Fall Times
Input Pulse Levels
≤5 ns
0.45V to 2.4V
Timing Measurement Reference Level
Inputs
Outputs
0.8V and 2V
0.8V and 2V
AC Waveforms (Note 6), (Note 7), and (Note 9)
2V
0.8V
ADDRESS
Address Valid
2V
0.8V
t
CE
OE
CF
(Note 4, 5)
t
CE
2V
0.8V
t
DF
t
OE
(Note 4, 5)
(Note 3)
2V
Hi-Z
Hi-Z
Valid Output
OUTPUT
0.8V
t
ACC
t
OH
(Note 3)
DS800032-4
Note 1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Note 2: This parameter is only sampled and is not 100% tested.
Note 3: OE may be delayed up to tACC - tOE after the falling edge of CE without impacting tACC
.
Note 4: The tDF and tCF compare level is determined as follows:
High to TRI-STATE®, the measured VOH1 (DC) - 0.10V;
Low to TRI-STATE, the measured VOL1 (DC) + 0.10V.
Note 5: TRI-STATE may be attained using OE or CE.
Note 6: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1 µF ceramic capacitor be used on every device
between VCC and GND.
Note 7: The outputs must be restricted to VCC + 1.0V to avoid latch-up and device damage.
Note 8: 1 TTL Gate: IOL = 1.6 mA, IOH = -400 µA.
CL: 100 pF includes fixture capacitance.
Note 9:
VPP may be connected to VCC except during programming.
Note 10: Inputs and outputs can undershoot to -2.0V for 20 ns Max.
Programming Characteristics (Note 11), (Note 12), (Note 13), and (Note 14)
Symbol
tAS
Parameter
Conditions
Min
1
Typ
Max Units
Address Setup Time
µs
µs
µs
µs
µs
µs
µs
µs
tOES
tCES
tDS
OE Setup Time
1
CE Setup Time
OE = VIH
1
Data Setup Time
1
tVPS
tVCS
tAH
VPP Setup Time
1
VCC Setup Time
1
Address Hold Time
Data Hold Time
0
tDH
1
tDF
Output Enable to Output Float Delay
Program Pulse Width
CE = VIL
0
60
ns
tPW
45
50
105
µs
4
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FM27C010
Programming Characteristics (Note 11), (Note 12), (Note 13), and (Note 14) (Continued)
Symbol
Parameter
Conditions
Min
Typ
Max Units
tOE
Data Valid from OE
CE = VIL
100
ns
IPP
VPP Supply Current during
Programming Pulse
CE = VIL
PGM = VIL
15
mA
ICC
TA
VCC Supply Current
20
30
mA
°C
V
Temperature Ambient
Power Supply Voltage
Programming Supply Voltage
Input Rise, Fall Time
20
6.2
12.5
5
25
6.5
VCC
VPP
tFR
6.75
13.0
12.75
V
ns
V
VIL
VIH
tIN
Input Low Voltage
0.0
4.0
0.45
Input High Voltage
2.4
0.8
0.8
V
Input Timing Reference Voltage
Output Timing Reference Voltage
2.0
2.0
V
tOUT
V
Programming Waveforms (Note 13)
Note 11: Fairchild’s standard product warranty applies only to devices programmed to specifications described herein.
Program
Verify
Program
2V
ADDRESS
DATA
Address N
0.8V
t
t
AS
DS
t
AH
2V
Hi-Z
Data Out Valid
Data In Stable
ADD
N
ADD
N
0.8V
t
t
DH
DF
6.25V
t
V
CC
VCS
12.75V
V
PP
t
VPS
CE
0.8V
t
CES
2V
0.8V
PGM
t
t
OE
t
OES
PW
OE
2V
0.8V
DS800032-5
Note 12: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. The EPROM must not be inserted into or removed from a board with
voltage applied to VPP or VCC
.
Note 13: The maximum absolute allowable voltage which may be applied to the VPP pin during programming is 14V. Care must be taken when switching the VPP supply to
prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1 µF capacitor is required across VPP, VCC to GND to suppress spurious voltage transients
which may damage the device.
Note 14: During power up the PGM pin must be brought high (≥VIH) either coincident with or before power is applied to VPP
.
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FM27C010
Turbo Programming Algorithm Flow Chart
VCC = 6.5V VPP = 12.75V
n = 0
ADDRESS = FIRST LOCATION
PROGRAM ONE 50µs PULSE
INCREMENT n
NO
YES
FAIL
DEVICE
FAILED
VERIFY
BYTE
n = 10?
PASS
INCREMENT
ADDRESS
n = 0
LAST
ADDRESS
?
NO
YES
ADDRESS = FIRST LOCATION
FAIL
VERIFY
BYTE
PASS
PROGRAM ONE
50 µs
INCREMENT
ADDRESS
PULSE
LAST
NO
ADDRESS
?
YES
CHECK ALL BYTES
1ST: VCC = VPP = 6.0V
2ND: VCC = VPP = 4.3V
Note:
The standard National Semiconductor Algorithm may also be used but it will have longer programming time.
DS800032-6
FIGURE 1.
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FM27C010
The EPROM is in the programming mode when the VPP power
supply is at 12.75V and OE is at VIH. It is required that at least a
0.1 µF capacitor be placed across VPP, VCC to ground to suppress
spurious voltage transients which may damage the device. The
data to be programmed is applied 8 bits in parallel to the data
output pins. The levels required for the address and data inputs
are TTL.
Functional Description
DEVICE OPERATION
The six modes of operation of the EPROM are listed in Table 1. It
should be noted that all inputs for the six modes are at TTL levels.
The power supplies required are VCC and VPP. The VPP power
supply must be at 12.75V during the three programming modes,
andmustbeat5Vintheotherthree modes. TheVCC powersupply
must be at 6.5V during the three programming modes, and at 5V
in the other three modes.
Whentheaddressanddataarestable,anactivelow,TTLprogram
pulse is applied to the PGM input. A program pulse must be
applied at each address location to be programmed. The EPROM
is programmed with the Turbo Programming Algorithm shown in
Figure 1. Each Address is programmed with a series of 50 µs
pulses until it verifies good, up to a maximum of 10 pulses. Most
memory cells will program with a single 50 µs pulse.
Read Mode
The EPROM has two control functions, both of which must be
logically active in order to obtain data at the outputs. Chip Enable
(CE) is the power control and should be used for device selection.
Output Enable (OE) is the output control and should be used to
gate data to the output pins, independent of device selection.
Assuming that the addresses are stable, address access time
(tACC)isequaltothedelayfromCEtooutput(tCE).Dataisavailable
at the outputs tOE after the falling edge of OE , assuming that CE
The EPROM must not be programmed with a DC signal applied to
the PGM input.
Programming multiple EPROM in parallel with the same data can
be easily accomplished due to the simplicity of the programming
requirements. Like inputs of the parallel EPROM may be con-
nected together when they are programmed with the same data.
A low level TTL pulse applied to the PGM input programs the
paralleled EPROM.
has been low and addresses have been stable for at least tACC
tOE
–
.
Standby Mode
Program Inhibit
The EPROM has a standby mode which reduces the active power
dissipation by over 99%, from 165 mW to 0.55 mW. The EPROM
is placed in the standby mode by applying a CMOS high signal to
the CE input. When in standby mode, the outputs are in a high
impedance state, independent of the OE input.
Programming multiple EPROM’s in parallel with different data is
also easily accomplished. Except for CE all like inputs (including
OE and PGM) of the parallel EPROM may be common. A TTL low
level program pulse applied to an EPROM’s PGM input with CE at
V
IL and VPP at 12.75V will program that EPROM. A TTL high level
Output Disable
CE input inhibits the other EPROM’s from being programmed.
The EPROM is placed in output disable by applying a TTL high
signal to the OE input. When in output disable all circuitry is
enabled, except the outputs are in a high impedance state (TRI-
STATE).
Program Verify
Averifyshouldbeperformedontheprogrammedbitstodetermine
whether they were correctly programmed. The verify may be
performed with VPP at 12.75V. VPP must be at VCC, except during
programming and program verify.
Output OR-Tying
Because the EPROM is usually used in larger memory arrays,
Fairchild has provided a 2-line control function that accommo-
dates this use of multiple memory connections. The 2-line control
function allows for:
AFTER PROGRAMMING
Opaque labels should be placed over the EPROM window to
prevent unintentional erasure. Covering the window will also
preventtemporaryfunctionalfailureduetothegenerationofphoto
currents.
1. the lowest possible memory power dissipation, and
2. complete assurance that output bus contention will not
occur.
MANUFACTURER’S IDENTIFICATION CODE
To most efficiently use these two control lines, it is recommended
that CE be decoded and used as the primary device selecting
function, while OE be made a common connection to all devices
in the array and connected to the READ line from the system
control bus. This assures that all deselected memory devices are
in their low power standby modes and that the output pins are
active only when data is desired from a particular memory device.
The EPROM has a manufacturer’s indentification code to aid in
programming. When the device is inserted in an EPROM pro-
grammer socket, the programmer reads the code and then
automatically calls up the specific programming algorithm for the
part. This automatic programming control is only possible with
programmers which have the capability of reading the code.
The Manufacturer’s Identification code, shown in Table 2, specifi-
cally identifies the manufacturer and device type. The code for the
FM27C010 is “8F86”, where “8F” designates that it is made by
Fairchild Semiconductor, and “86” designates a 1 Megabit (128K
x 8) part.
Programming
CAUTION: Exceeding 14V on the VPP or A9 pin will damage the
EPROM.
Initially, and after each erasure, all bits of the EPROM are in the
“1’s” state. Data is introduced by selectively programming “0’s”
into the desired bit locations. Although only “0’s” will be pro-
grammed, both “1’s” and “0’s” can be presented in the data word.
The only way to change a “0” to a “1” is by ultraviolet light erasure.
The code is accessed by applying 12V 0.5V to address pin A9.
Addresses A1–A8, A10–A16, and all control pins are held at VIL.
Address pin A0 is held at VIL for the manufacturer’s code, and held
at VIH for the device code. The code is read on the eight data pins,
O0–07. Proper code access is only guaranteed at 25°C 5°C.
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FM27C010
be checked to make certain full erasure is occurring. Incomplete
erasure will cause symptoms that can be misleading. Program-
mers, components and even system designs have been errone-
ously suspected when incomplete erasure was the problem.
Functional Description (Continued)
ERASURE CHARACTERISTICS
The erasure characteristics of the device are such that erasure
begins to occur when exposed to light with wavelengths shorter
than approximately 4000 Angstroms (Å). It should be noted that
sunlight and certain types of fluorescent lamps have wavelengths
in the 3000Å – 4000Å range.
SYSTEM CONSIDERATION
The power switching characteristics of EPROMs require careful
decoupling of the devices. The supply current, ICC, has three
segments that are of interest to the system designer: the standby
current level, the active current level, and the transient current
peaks that are produced by voltage transitions on input pins. The
magnitude of these transient current peaks is dependent on the
output capacitance loading of the device. The associated VCC
transient voltage peaks can be suppressed by properly selected
decoupling capacitors. It is recommended that at least a 0.1 µF
ceramic capacitor be used on every device between VCC and
GND. This should be a high frequency capacitor of low inherent
inductance. In addition, at least a 4.7 µF bulk electrolytic capacitor
shouldbeusedbetweenVCC andGNDforeacheightdevices.The
bulk capacitor should be located near where the power supply is
connected to the array. The purpose of the bulk capacitor is to
overcome the voltage drop caused by the inductive effects of the
PC board traces.
The recommended erasure procedure for the EPROM is expo-
sure to short wave ultraviolet light which has a wavelength of
2537Å. Theintegrateddose(i.e., UVintensityxexposuretime)for
erasure should be a minimum of 15W-sec/cm2.
The EPROM should be placed within 1 inch of the lamp tubes
during erasure. Some lamps have a filter on their tubes which
should be removed before erasure.
Anerasuresystemshouldbecalibratedperiodically.Thedistance
fromlamptodeviceshouldbemaintainedatoneinch.Theerasure
time increases as the square of the distance from the lamp. (if
distance is doubled the erasure time increases by factor of 4).
Lamps lose intensity as they age. When a lamp is changed, the
distance has changed, or the lamp has aged, the system should
MODE SELECTION
The modes of operation of the FM27C010 are listed in Table 1. A single 5V power supply is required in the read mode. All inputs are TTL
levels except for VPP and A9 for device signature.
TABLE 1. Modes Selection
Pins
CE
OE
PGM
VPP
VCC
Outputs
Mode
Read
VIL
VIL
X
X
5.0V
DOUT
(Note 15)
Output Disable
Standby
X
VIH
X
X
X
X
5.0V
5.0V
High Z
High Z
DIN
VIH
VIL
VIL
VIH
X
Programming
Program Verify
Program Inhibit
VIH
VIL
X
VIL
VIH
X
12.75V
12.75V
12.75V
6.25V
6.25V
6.25V
DOUT
High Z
Note 15: X can be VIL or VIH
.
TABLE 2. Manufacturer’s Identification Code
A0 A9 O7 O6 O5 O4 O3
(26) (21) (20) (19) (18) (17)
Pin
s
O2
(15) (14)
O1
O0
Hex
(12)
VIL
(13) Data
Manufacturer Code
Device Code
12V
1
0
0
0
1
1
1
1
8F
VIH
12V
1
0
0
0
0
1
1
0
86
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FM27C010
Physical Dimensions inches (millimeters) unless otherwise noted
1.660
(42.16)
MAX
32
17
0.025
(0.64)
R
0.585
(14.86)
MAX
1
16
UV WINDOW SIZE AND
R 0.030-0.055
(0.76 - 1.40)
TYP
CONFIGURATION DETERMINED
BY DEVICE SIZE
0.050-0.060
(1.27 - 1.52)
Glass Sealant
TYP
0.10
(2.54)
MAX
0.590-0.620
(15.03 - 15.79)
MIN
TYP
0.005
(0.127)
0.175
(4.45)
MAX
0.225
(5.72)
MAX TYP
0.015 -0.060
(0.25 - 1.52)
TYP
0.125
(3.18)
MIN
TYP
90° - 100°
TYP
0.008-0.012
(0.20 - 0.30)
TYP
86°-94°
TYP
0.150
(3.81)
MIN
TYP
0.090-0.110
(2.29 - 2.79)
TYP
0.015-0.021
(0.38 - 0.53)
TYP
0.060-0.100
(1.52 - 2.54)
TYP
0.685
(17.40) (0.64)
-0.060
+0.025
(-1.523)
32-Lead EPROM Ceramic Dual-In-Line Package (Q)
Order Number FM27C010QXXX
Package Number J32AQ
1.64 – 1.66
(41.66 – 42.164)
32
17
0.062
(1.575)
RAD
TYP
0.490 – 0.550
(12.446 – 13.97)
1
16
Pin No. 1 IDENT
0.580
(14.73)
MIN
0.050
(1.270)
TYP
0.125 – 0.165
(3.175 – 4.191)
0.600 – 0.620
(15.240 – 15.748)
0.145 – 0.210
(3.683 – 5.334)
86°- 94°
TYP
0.015
(0.381)
90°–105°
0.008 - 0.015
(0.203 – 0.381)
0.120 – 0.150
(3.048 – 3.81)
0.040 - 0.090
(1.016 – 2.286)
0.018 0.003
(0.457 0.078)
0.100 0.010
(2.540 0.254)
0.035 – 0.07
(0.889 – 1.778)
32-Lead Molded Dual-In-Line Package (N)
Order Number FM27C010NXXX
Package Number
9
www.fairchildsemi.com
FM27C010
Physical Dimensions inches (millimeters) unless otherwise noted
0.485-0.495
[12.32-12.57]
-H-
Base
Plane
0.106-0.112
[2.69-2.84]
B
S
D-E
S
0.007[0.18]
0.449-0.453
[11.40-11.51]
0.023-0.029
[0.58-0.74]
0.015
[0.38]
Min Typ
-A-
B
0.045
[1.143]
D-E
S
0.007[0.18]
S
°
60
B
S
0.002[0.05]
0.000-0.010
[0.00-0.25]
Polished Optional
0.490-0530
[12.45-13.46]
0.400
[10.16]
-D-
(
)
1
30
4
0.541-0.545
[13.74-13-84]
S
C
D-E, F-G
S
0.015[0.38]
5
29
0.549-0.553
[13.94-14.05]
-G-
-B-
0.585-0.595
[14.86-15.11]
0.013-0.021
[0.33-0.53]
TYP
-F-
See detail A
-J-
C
D-E, F-G
S
0.007[0.18]
M
13
21
0.078-0.095
[1.98-2.41]
0.123-0.140
[3.12-3.56]
0.050
14
A
20
-E-
-C-
0.004[0.10]
0.002[0.05]
0.007[0.18]
S
0.005
[0.13]
Max
0.0100
[0.254]
A
F-G
S
S
0.020
[0.51]
A
F-G
S
0.007[0.18]
S
0.118-0.129
[3.00-3.28]
0.045
[1.14]
0.030-0.040
[0.76-1.02]
B
A
D-E, F-G
0.025
[0.64]
S
0.010[0.25]
L
R
Detail A
Typical
Rotated 90°
Min
B
0.042-0.048
[1.07-1.22]
45°X
0.025
[0.64]
0.021-0.027
[0.53-0.69]
Min
B
0.065-0.071
[1.65-1.80]
0.053-0.059
[1.65-1.80]
0.031-0.037
[0.79-0.94]
0.006-0.012
[0.15-0.30]
0.027-0.033
[0.69-0.84]
0.026-0.032
[0.66-0.81]
0.019-0.025
[0.48-0.64]
Typ
S
Section B-B
Typical
H
D-E, F-G
S
0.007[0.18]
32-Lead PLCC Package
Order Number FM27C010VXXX
Package Number VA32A
Life Support Policy
Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written
approval of the President of Fairchild Semiconductor Corporation. As used herein:
1. Life support devices or systems are devices or systems which,
(a)areintendedforsurgicalimplantintothebody,or(b)support
or sustain life, and whose failure to perform, when properly
used in accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a significant
injury to the user.
2. A critical component is any component of a life support device
or system whose failure to perform can be reasonably ex-
pected to cause the failure of the life support device or system,
or to affect its safety or effectiveness.
Fairchild Semiconductor
Americas
Fairchild Semiconductor
Europe
Fairchild Semiconductor
Hong Kong
Fairchild Semiconductor
Japan Ltd.
Customer Response Center
Tel. 1-888-522-5372
Fax:
Tel:
Tel:
Tel:
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8/F, Room 808, Empire Centre
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
10
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FM27C010
Fairchild P/N FM27C010 - 1M-Bit (128K x 8) High Performance CMOS EPfRilOe:M////roarer/root/data13/imaging/BIT...04/08032000/FAIR/08022000/FM27C010.html
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[Information as of 1-Aug-2000]
PDF
FM27C010
1M-Bit (128K x 8) High Performance CMOS EPROM
Generic P/N 27C010
Contents
General Description
Features
Datasheet
Availability, Models, Samples & Pricing
General Description
The FM27C010 is a high performance, 1,048,576-bit Electrically Programmable UV Erasable Read
Memory. It is organized as 128K-words of 8 bits each. Its pin-compatibility with byte-wide JEDEC
EPROMs enables upgrades through 8 Mbit EPROMs. The "Don't Care" feature during read operatio
allows memory expansions from 1M to 8M bits with no printed circuit board changes.
The FM27C010 can directly replace lower density 28-pin EPROMs by adding an A16 address line a
jumper. During the normal read operation /PGM and V are in a "Don't Care" state which allows h
PP
order addresses, such as A17, A18, and A19 to be connected without affecting the normal read oper
This allows memory upgrades to 8M bits without hardware changes. The FM27C010 is also offered
32-pin plastic DIP with the same upgrade path.
The FM27C010 provides microprocessor-based systems extensive storage capacity for large portion
operating system and application software. Its 70 ns access time provides no-wait-state operation wi
high-performance CPUs. The FM27C010 offers a single chip solution for the code storage requirem
100% firmware-based equipment. Frequently-used software routines are quickly executed from EPR
storage, greatly enhancing system utility.
The FM27C010 is manufactured using Fairchild's advanced CMOS AMG™ EPROM technology.
The FM27C010 is one member of a high density EPROM Family which range in densities up to 4 M
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Fairchild P/N FM27C010 - 1M-Bit (128K x 8) High Performance CMOS EPfRilOe:M////roarer/root/data13/imaging/BIT...04/08032000/FAIR/08022000/FM27C010.html
Features
High performance CMOS
70 ns access time
Fast turn-off for microprocessor compatibility
Simplified upgrade path
V
and /PGM are "Don't Care" during normal read operation
PP
Manufacturer's identification code
Fast programming
JEDEC standard pin configuration
32-pin PDIP package
32-pin PLCC package
32-pin CERDIP package
Datasheet
Receive datasheet via E-mail
or download now
; use Adobe Acrobat to view...
FM27C010 1M-Bit (128K x 8) High Performance CMOS EPROM (109 Kbytes; 29-JU
Availability, Models, Samples & Pricing
Budgetary
Pricing
Package
Models
Std
Pack
Size
Package
Markin
Part Number Grade
Status
#
$US
ea
Type
SPICE IBIS Quantity
pins
$Y&Z&
FM27C010Q45 Comm Cerdip 32 Obsolete
N/A N/A
N/A N/A FM27C
4
1-24 $4.14
25-99 $3.10 N/A FM27C
100-500 $2.48
1-24 $4.14
25-99 $3.10 N/A FM27C
100-500 $2.48
$Y&Z&
Full
FM27C010Q120 Comm Cerdip 32
Production
N/A N/A
N/A N/A
N/A N/A
12
$Y&Z&
Full
FM27C010Q90 Comm Cerdip 32
Production
9
1-24 $4.27
25-99 $3.20 N/A FM27C
100-500 $2.56
$Y&Z&
Full
FM27C010QE150 Comm Cerdip 32
Production
15
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Fairchild P/N FM27C010 - 1M-Bit (128K x 8) High Performance CMOS EPfRilOe:M////roarer/root/data13/imaging/BIT...04/08032000/FAIR/08022000/FM27C010.html
1-24 $4.27
25-99 $3.20 N/A FM27C
$Y&Z&
Full
Production
FM27C010QE120 Comm Cerdip 32
FM27C010Q150 Comm Cerdip 32
N/A N/A
N/A N/A
N/A N/A
N/A N/A
N/A N/A
N/A N/A
N/A N/A
N/A N/A
100-500 $2.56
1-24 $4.14
25-99 $3.10 N/A FM27C
100-500 $2.48 15
$Y&Z
N/A N/A FM27
12
$Y&Z&
Full
Production
FM27C010T45
Comm TSOP 32 Obsolete
4
$Y&Z
N/A N/A FM27
45
FM27C010T45L Comm TSOP 32 Obsolete
FM27C010N90 Comm MDIP 32 Obsolete
FM27C010NE150 Comm MDIP 32 Obsolete
FM27C010N120 Comm MDIP 32 Obsolete
FM27C010NE120 Comm MDIP 32 Obsolete
$Y&Z&
N/A N/A FM27C
9
$Y&Z&
N/A N/A FM27C
15
$Y&Z&
N/A N/A FM27C
12
$Y&Z&
N/A N/A FM27C
12
$Y&Z&
N/A N/A FM27C
15
FM27C010N150 Comm MDIP 32 Obsolete
Full
N/A N/A
N/A N/A
N/A N/A
FM27C010DWF Comm
wafer
N/A N/A
Production
1-24 $3.60
$Y&Z&
Full
Production
FM27C010V90 Comm PLCC 32
FM27C010V150 Comm PLCC 32
FM27C010V120 Comm PLCC 32
25-99 $2.70 N/A FM27C
100-500 $2.16
9
1-24 $3.60
$Y&Z&
Full
Production
N/A N/A
N/A N/A
25-99 $2.70 N/A FM27C
100-500 $2.16
15
1-24 $3.60
$Y&Z&
Full
Production
25-99 $2.70 N/A FM27C
100-500 $2.16
12
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