FM34W02LEMT8 [FAIRCHILD]
EEPROM, 256X8, Serial, CMOS, PDSO8, PLASTIC, TSSOP-8;
| 型号： | FM34W02LEMT8 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | EEPROM, 256X8, Serial, CMOS, PDSO8, PLASTIC, TSSOP-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 双倍数据速率 光电二极管 内存集成电路 |
| 文件： | 总12页 (文件大小：92K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY INFORMATION
June 2000
FM34W02
2K-Bit Standard 2-Wire Bus Interface Serial EEPROM
with Full Array Write Protect
Designed with Permanent Write-Protection for First 128 Bytes for Serial Presence
Detect Application on Memory Modules (PC100/PC133 Compliant)
General Description
Features
The FM34W02 is 2048 bits of CMOS non-volatile electrically
erasable memory. This device is specifically designed to support
Serial Presence Detect circuitry in memory modules. This com-
munications protocol uses CLOCK (SCL) and DATA I/O (SDA)
lines to synchronously clock data between the master (for ex-
ample a microprocessor) and the slave EEPROM device(s).
I PC100/PC133 Compliant
I Extended Operating Voltage: 2.7V-5.5V
I Software Write-Protection for first 128 bytes
I Hardware Write-Protection for entire memory array
I 200 µA active current typical
The contents of the non-volatile memory allows the CPU to
determine the capacity of the module and the electrical character-
istics of the memory devices it contains. This will enable "plug and
play" capability as the module is read and PC main memory
resources utilized through the memory controller.
– 1.0 µA standby current typical (L)
– 0.1 µA standby current typical (LZ)
I IIC compatible interface
– Provides bidirectional data transfer protocol
I Sixteen byte page write mode
– Minimizes total write time per byte
The first 128 bytes of the memory of the FM34W02 can be
permanentlyWriteProtectedbywritingtothe"WRITEPROTECT"
Register. Write Protect implementation details are described
underthesectiontitledAddressingtheWPRegister. Inaddition,
like the NM24Wxx product family, the entire memory array can be
write-protected through "WP" pin.
I Self timed write cycle
- Typical write cycle time of 6ms
I Endurance: 1,000,000 data changes
I Data retention greater than 40 years
TheFM34W02isavailableinaJEDECstandardTSSOPpackage
for low profile memory modules for systems requiring efficient
spaceutilizationsuchasinanotebookcomputer. Twooptionsare
available: L - Low Voltage and LZ - Low Power, allowing the part
to be used in systems where battery life is of primary importance.
I Packages available: 8-pin TSSOP and 8-pin SO
I Temperature Ranges: Commercial and Extended
Block Diagram
V
CC
V
SS
WP
H.V. GENERATION
TIMING &CONTROL
START CYCLE
START
STOP
SDA
LOGIC
CONTROL
LOGIC
SLAVE ADDRESS
REGISTER &
COMPARATOR
2
E
PROM
16
ARRAY
16 x 16 x 8
XDEC
SCL
LOAD
INC
A2
A1
A0
WORD
ADDRESS
COUNTER
0/1/2/3
4
16
4
R/W
YDEC
Device Address Bits
8
Write Protect
Register
CK
D
OUT
DATA REGISTER
D
IN
DS800041-1
1
© 2000 Fairchild Semiconductor International
FM34W02 Rev. A
www.fairchildsemi.com
Connection Diagram
SO (M8) and TSSOP (MT8) Package
A0
A1
A2
1
2
3
4
8
7
6
5
V
CC
WP
FM34W02
SCL
SDA
V
SS
DS800041-2
Top View
See Package Number
M08A and MTC08
Pin Names
A0,A1,A2
VSS
Device Address Inputs
Ground
SDA
Data I/O
Clock Input
SCL
WP
VCC
Write Protect
Power Supply
Ordering Information
FM 34 02
W
LZ
E
XX
Letter Description
Package
M8
8-Pin SO8
MT8
8-Pin TSSOP
Temp. Range
None
E
0 to 70°C
-40 to +85°C
Voltage Operating Range
Blank
L
4.5V to 5.5V
2.7V to 5.5V
LZ
2.7V to 5.5V and
<1µA Standby Current
Density
02
W
2K
Full Array Write Protect
IIC
Interface
34
FM
Fairchild Non-Volatile
Memory
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FM34W02 Rev. A
Product Specifications
Operating Conditions
Ambient Operating Temperature
Absolute Maximum Ratings
Ambient Storage Temperature
–65°C to +150°C
6.5V to –0.3V
FM34W02
FM34W02E
0°C to +70°C
-40°C to +85°C
All Input or Output Voltages
with Respect to Ground
Positive Power Supply
FM34W02
Lead Temperature
4.5V to 5.5V
2.7V to 5.5V
2.7V to 5.5V
(Soldering, 10 seconds)
+300°C
FM34W02L
FM34W02LZ
ESD Rating
2000V min.
Standard VCC (4.5V to 5.5V) DC Electrical Characteristics
Symbol
Parameter
Test Conditions
Limits
Typ
Units
Min
Max
(Note 1)
ICCA
ISB
ILI
Active Power Supply Current
Standby Current
fSCL = 400 kHz
0.2
10
1.0
mA
µA
µA
µA
V
VIN = GND or VCC
VIN = GND to VCC
VOUT = GND to VCC
50
Input Leakage Current
Output Leakage Current
Input Low Voltage
0.1
0.1
1
1
ILO
VIL
VIH
VOL
–0.3
VCC x 0.3
VCC + 0.5
0.4
Input High Voltage
VCC x 0.7
V
Output Low Voltage
IOL = 3 mA
V
Low VCC (2.7V to 5.5V) DC Electrical Characteristics
Symbol
Parameter
Test Conditions
Limits
Units
Min
Typ
Max
(Note 1)
ICCA
ISB
Active Power Supply Current fSCL = 400 kHz
0.2
1.0
mA
Standby Current
VIN = GND or VCC = 4.5V - 5.5V
10
1
0.1
50
10
1
µA
µA
µA
VIN = GND or VCC = 2.7V - 5.5V (L)
VIN = GND or VCC = 2.7V - 5.5V (LV)
ILI
ILO
Input Leakage Current
Output Leakage Current
Input Low Voltage
VIN = GND to VCC
VOUT = GND to VCC
0.1
0.1
1
1
µA
µA
V
VIL
VIH
VOL
–0.3
VCC x 0.3
VCC + 0.5
0.4
Input High Voltage
VCC x 0.7
V
Output Low Voltage
IOL = 3 mA
V
Capacitance TA = +25°C, f = 100/400 KHz, VCC = 5V (Note 2)
Symbol
CI/O
Test
Conditions
VI/O = 0V
Max Units
Input/Output Capacitance (SDA)
Input Capacitance (A0, A1, A2, SCL)
8
6
pF
pF
CIN
VIN = 0V
Note 1: Typical values are TA = 25°C and nominal supply voltage (5V).
Note 2: This parameter is periodically sampled and not 100% tested.
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FM34W02 Rev. A
AC Conditions of Test
Input Pulse Levels
VCC x 0.1 to VCC x 0.9
Input Rise and Fall Times
10 ns
Input & Output Timing Levels VCC x 0.5
Output Load
1 TTL Gate and CL = 100 pF
Read and Write Cycle Limits (Standard and Low VCC Range 2.7V - 5.5V)
Symbol
Parameter
100 KHz
400 KHz
Units
Min
Max
Min
Max
fSCL
TI
SCL Clock Frequency
100
100
3.5
400
KHz
ns
Noise Suppression Time Constant at
SCL, SDA Inputs (Minimum VIN
Pulse width)
50
tAA
SCL Low to SDA Data Out Valid
0.3
4.7
0.1
1.3
0.9
µs
µs
tBUF
Time the Bus Must Be Free before
a New Transmission Can Start
tHD:STA
tLOW
Start Condition Hold Time
Clock Low Period
4.0
4.7
4.0
4.7
0.6
1.5
0.6
0.6
µs
µs
µs
µs
tHIGH
Clock High Period
tSU:STA
Start Condition Setup Time
(for a Repeated Start Condition)
tHD:DAT
tSU:DAT
tR
Data in Hold Time
0
0
ns
ns
µs
ns
µs
ns
ms
Data in Setup Time
250
100
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
1
0.3
tF
300
300
tSU:STO
tDH
4.7
0.6
50
300
tWR
(Note 3)
Write Cycle Time - FM34W02
- FM34W02L, FM34W02LZ
10
15
10
15
Note 3: The write cycle time (tWR) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle, the
FM34W02 bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and the device does not respond to its slave address.
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FM34W02 Rev. A
Bus Timing
t
t
R
F
t
HIGH
t
t
LOW
LOW
SCL
t
SU:STO
t
t
t
SU:DAT
SU:STA
HD:DAT
t
HD:STA
SDA
IN
t
BUF
t
t
AA
DH
SDA
OUT
DS800041-5
Background Information (IIC Bus)
DEFINITIONS
As mentioned, the IIC bus allows synchronous bidirectional com-
munication between Transmitter/Receiver using the SCL (clock)
and SDA (Data I/O) lines. All communication must be started with
a valid START condition, concluded with a STOP condition and
acknowledged by the Receiver with an ACKNOWLEDGE condi-
tion.
BYTE
PAGE
8 bits of data
16 sequential addresses (one byte
each) that may be programmed
during a 'Page Write' programming
cycle
PAGE BLOCK
2,048 (2K) bits organized into 16
pages of addressable memory. (8
bits) x (16 bytes) x (16 pages) = 2,048
bits
In addition, since the IIC bus is designed to support other devices
such as RAM, EPROMs, etc., a device type identifier string must
follow the START condition. For EEPROMs, this 4-bit string is
1010. Also refer the Addressing the WP Register section.
MASTER
SLAVE
Any IIC device CONTROLLING the
transfer of data (such as a micropro-
cessor)
As shown below, although the EEPROMs on the IIC bus may be
configured in any manner required, the total memory addressed
can not exceed 16K (16,384 bits) on the Standard IIC. EEPROM
memory address programming is controlled by 2 methods:
Device being controlled (EEPROMs
are always considered Slaves)
• Hardware configuring the A0, A1, and A2 pins (Device
Address pins) with pull-up or pull-down to VCC or VSS. All
TRANSMITTER
RECEIVER
Device currently SENDING data on
the bus (may be either a Master or
Slave).
unused pins must be grounded (tied to V ).
SS
• Software addressing the required PAGE BLOCK within the
device memory array (as sent in the Slave Address string).
Device currently receiving data on the
bus (Master or Slave)
Addressing an EEPROM memory location involves sending a
command string with the following information:
[DEVICE TYPE]—[DEVICE ADDRESS]—[PAGE BLOCK
ADDRESS]—[BYTE ADDRESS]
Example of 16K of Memory on 2-Wire Bus
V
V
CC
CC
SDA
SCL
V
V
V
V
CC
CC
CC
CC
34C02L
24C02
24C04
24C08
A0 A1 A2
V
A0 A1 A2
V
A0 A1 A2
V
A0 A1 A2 V
SS
SS
SS
SS
To V
CC
or V
SS
To V
CC
or V
SS
To V
CC
or V
SS
To V
CC
or V
SS
DS800041-6
Note:
The SDA pull-up resistor is required due to the open-drain/open collector output of IIC bus devices.
The SCL pull-up resistor is recommended because of the normal SCL line inactive 'high' state.
It is recommended that the total line capacitance be less than 400pF.
Specific timing and addressing considerations are described in greater detail in the following sections.
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FM34W02 Rev. A
Device
Address Pins
Memory Size
Number of
A0
A1
A2
Page Blocks
FM34W02
ADR
ADR
ADR
2048 Bits
1
Start Condition
Pin Descriptions
All commands are preceded by the start condition, which is a
HIGHtoLOWtransitionofSDAwhenSCLisHIGH.TheFM34W02
continuously monitors the SDA and SCL lines for the start condi-
tion and will not respond to any command until this condition has
been met.
Serial Clock (SCL)
The SCL input is used to clock all data into and out of the device.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into and out of the
device. It is an open drain output and may be wire–ORed with any
number of open drain or open collector outputs.
Stop Condition
All communications are terminated by a stop condition, which is a
LOW to HIGH transition of SDA when SCL is HIGH. The stop
condition is also used by the FM34W02 to place the device in the
standby power mode.
Device Operation Inputs (A0, A1, A2)
Device address pins A0, A1, and A2 are connected to V or V
CC
SS
to configure the EEPROM chip address. Table A shows the active
pins across the FM34W02 device family.
ACKNOWLEDGE
Acknowledgeisasoftwareconventionusedtoindicatesuccessful
data transfers. The transmitting device, either master or slave, will
release the bus after transmitting eight bits.
Table 1.
Device
A0
A1
A2 Effects of Addresses
During the ninth clock cycle the receiver will pull the SDA line to
LOW to acknowledge that it received the eight bits of data. Refer
to Figure 3.
FM34W02 ADR ADR ADR
8 devices max.
Device Operation
The FM34W02 device will always respond with an acknowledge
after recognition of a start condition and its slave address. If both
thedeviceandawriteoperationhavebeenselected,theFM34W02
will respond with an acknowledge after the receipt of each
subsequent eight bit byte.
TheFM34W02supportsabidirectionalbusorientedprotocol. The
protocol defines any device that sends data onto the bus as a
transmitter and the receiving device as the receiver. The device
controlling the transfer is the master and the device that is
controlled is the slave. The master will always initiate data
transfers and provide the clock for both transmit and receive
operations. Therefore, theFM34W02willbeconsideredaslave in
all applications.
In the Read mode the FM34W02 slave will transmit eight bits of
data, release the SDA line and monitor the line for an acknowl-
edge. If an acknowledge is detected and no stop condition is
generated by the master, the slave will continue to transmit data.
If an acknowledge is not detected, the slave will terminate further
data transmissions and await the stop condition to return to the
standby power mode.
Clock and Data Conventions
Data states on the SDA line can change only during SCL LOW.
SDA state changes during SCL HIGH are reserved for indicating
start and stop conditions. Refer to Figures 1 and 2.
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FM34W02 Rev. A
Write Cycle Timing
SCL
SDA
8th BIT
WORD n
ACK
t
WR
STOP
START
CONDITION
CONDITION
DS800041-7
SCL
SDA
DATA
CHANGE
DATA STABLE
DS800041-8
Data Validity (Figure 1).
SCL
SDA
START
CONDITION
STOP
CONDITION
DS800041-9
Start and Stop Definition (Figure 2).
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM
TRANSMITTER
DATA OUTPUT
FROM
RECEIVER
START
ACKNOWLEDGE
DS800041-10
Acknowledge Responses from Receiver (Figure 3).
Device Addressing
Following a start condition the master must output the address of
the slave it is accessing. The most significant four bits of the slave
address are those of the device type identifier (see Figure 4). This
is fixed as 1010 for all EEPROM devices.
All IIC EEPROMs use an internal protocol that defines a PAGE
BLOCK size of 2K bits (for Byte addresses 00 through FF).
7
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FM34W02 Rev. A
andthepreviouslywrittendatawillbeoverwritten. Aswiththebyte
write operation, all inputs are disabled until completion of the
internal write cycle. Refer to Figure 6 for the address, acknowl-
edge, and data transfer sequence.
Device Addressing (Continued)
Device Type
Identifier
Device
Address
Acknowledge Polling
1
0
1
0
A2
A1
A0 R/W (LSB)
Once the stop condition is issued to indicate the end of the host’s
write operation the FM34W02 initiates the internal write cycle.
ACKpollingcanbeinitiatedimmediately. Thisinvolvesissuingthe
start condition followed by the slave address for a write operation.
If the FM34W02 is still busy with the write operation no ACK will
bereturned.IftheFM34W02hascompletedthewriteoperationan
ACK will be returned and the host can then proceed with the next
read or write operation.
34W02
DS800041-11
Slave Addresses (Figure 4).
Refer to the following table for Slave Address string details:
Device A0 A1 A2
Page
Blocks
Page Block
Addresses
Software Write Protect
FM34W02
A
A
A
1 (2K)
(None)
Software write protection on the FM34W02 protects the first 128
bytes of the EEPROM memory. Software write protection is
implemented through a seperate register called the WRITE PRO-
TECT (WP) Register and writing to this WP register permanently
WRITE protects the memory. This WP register is a "one-time-
only-write" register. Once this register is written, it cannot be
erased.AfterthefirstWRITEtothisregister,allfutureaccess'
to this register are ignored as if an invalid IIC cycle occured.
To write protect, the user must perform a byte write to the WP
register. This will permanently disable programming to the first
128 bytes of memory.
Write Operations
The last bit of the slave address defines whether a write or read
condition is requested by the master. A '1' indicates that a read
operation is to be executed, and a '0' initiates the write mode.
A simple review: After the FM34W02 recognizes the start condi-
tion, the devices interfaced to the IIC bus wait for a slave address
to be transmitted over the SDA line. If the transmitted slave
addressmatchesanaddressofoneofthedevices,thedesignated
slave pulls the SDA line LOW with an acknowledge signal and
awaits further transmissions.
Addressing the WP Register
Addressing the WP register is very similar to accessing any
memory array with the following difference:
Byte Write
For a write operation a second address field is required which is
a byte address that is comprised of eight bits and provides access
to any one of the 256 bytes in the selected page block of memory.
Upon receipt of the byte address the FM34W02 responds with an
acknowledge and waits for the next eight bits of data, again,
responding with an acknowledge. The master then terminates the
transferbygeneratingastopcondition,atwhichtimetheFM34W02
begins the internal write cycle to the nonvolatile memory. While
the internal write cycle is in progress the FM34W02 inputs are
disabled, and the device will not respond to any requests from the
master. Refer to Figure 5 for the address, acknowledge and data
transfer sequence.
Insteadoftheconventional"1010"IICdeviceaddress,the unused
IIC device address "0110" is used to access just the WP register.
Deviceaddress"1010"willbeusedforallthetypicalmemoryarray
access. With this difference in place, accessing the WP register is
same as a typical IIC byte write cycle as described under "Write
Operations" section. All timing information and waveform details
remain the same. The "Byte Address" and the "Data" fields of the
Byte write cycle serve as place holders and can be of any value
(Don't Care). Refer to Figure 7.
Hardware Write Protect
Programming of the memory will not take place if the WP pin of the
FM34W02 is connected to VCC, regardless of whether the soft-
ware write protect register has been implemented or not. The
FM34W02 will accept slave and word addresses; but if the
memoryaccessediswriteprotectedbytheWPpin, theFM34W02
will not generate an acknowledge after the first byte of data has
beenreceived,andthustheprogramcyclewillnotbestartedwhen
Page Write
The FM34W02 is capable of a sixteen byte page write operation.
It is initiated in the same manner as the byte write operation; but
instead of terminating the write cycle after the first data byte is
transferred, the master can transmit up to fifteen more bytes. After
the receipt of each byte, the FM34W02 will respond with an
acknowledge.
the stop condition is asserted. (Note: if the WP pin is set to VCC
,
it will prevent the software write protect register from being
written.)
After the receipt of each byte, the internal address counter
incrementstothenextaddressandthenextSDAdataisaccepted.
If the master should transmit more than sixteen bytes prior to
generating the stop condition, the address counter will 'roll over'
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FM34W02 Rev. A
Write Protect Scheme (Continued)
S
T
A
R
T
S
T
O
P
SLAVE
ADDRESS
WORD
ADDRESS
Bus Activity:
Master
DATA
SDA Line
A
C
K
A
C
K
A
C
K
DS800041-15
Byte Write (Figure 5).
S
T
A
R
T
S
T
O
P
SLAVE
ADDRESS
Bus Activity:
Master
BYTE ADDRESS (n)
DATA n
DATA n + 1
DATA n + 15
SDA Line
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
DS800041-16
Page Write (Figure 6).
S
S
T
O
P
T
A
R
T
SLAVE
ADDRESS
BYTE
ADDRESS
Bus Activity:
Master
DATA
SDA Line
A
C
K
A
C
K
A
C
K
DON'T CARE
DON'T CARE
Bus Activity:
DEVICE
ADDRESS
DS800041-17
WP Register Write (Figure 7).
be read. After the slave word address acknowledge, the master
immediately reissues the start condition and the slave address
with the R/W bit set to one. This will be followed by an acknowl-
edge from the FM34W02 and then by the eight bit word. The
master will not acknowledge the transfer but does generate the
stop condition, and therefore the FM34W02 discontinues trans-
mission. Refer to Figure 9 for the address, acknowledge and data
transfer sequence.
Read Operations
Read operations are initiated in the same manner as write
operations,withtheexceptionthattheR/Wbitoftheslaveaddress
is set to a one. There are three basic read operations: current
address read, random read, and sequential read.
CURRENT ADDRESS READ
Internally the FM34W02 contains an address counter that main-
tains the address of the last word accessed, incremented by one.
Therefore, if the last access (either a read or write) was to address
n, the next read operation would access data from address n + 1.
Upon receipt of the slave address with R/W set to one, the
FM34W02 issues an acknowledge and transmits the data byte.
The master will not acknowledge the transfer but does generate
a stop condition, and therefore the FM34W02 discontinues trans-
mission. Refer to Figure 8 for the sequence of address, acknowl-
edge and data transfer.
SEQUENTIAL READ
Sequential reads can be initiated as either a current address read
or random access read. The first word is transmitted in the same
manner as the other read modes; however, the master now
responds with an acknowledge, indicating it requires additional
data. The FM34W02 continues to output data for each acknowl-
edge received. The read operation is terminated by the master not
respondingwithanacknowledgeorbygeneratingastopcondition.
The data output is sequential, with the data from address n
followed by the data from n + 1. The address counter for read
operations increments all word address bits, allowing the entire
memory contents to be serially read during one operation. After
the entire memory has been read, the counter 'rolls over' and the
FM34W02 continues to output data for each acknowledge re-
ceived.RefertoFigure10 fortheaddress,acknowledge,anddata
transfer sequence.
RANDOM READ
Random read operations allow the master to access any memory
location in a random manner. Prior to issuing the slave address
with the R/W bit set to one, the master must first perform a
“dummy” write operation. The master issues the start condition,
slave address, R/W bit set to zero, and then the word address to
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FM34W02 Rev. A
Current Address Read (Figure 8)
S
T
A
R
T
S
T
O
P
SLAVE
ADDRESS
Bus Activity:
Master
SDA Line
A
C
K
DATA
DS800041-18
Random Read (Figure 9)
S
T
S
T
A
R
T
S
T
O
P
SLAVE
A
BYTE
ADDRESS
SLAVE
ADDRESS
Bus Activity:
Master
ADDRESS
R
T
SDA Line
A
C
K
A
C
K
A
C
K
DATA n
DS800041-19
Sequential Read (Figure 10)
S
T
O
P
A
C
K
A
C
K
A
C
K
Bus Activity:
SLAVE
Master
ADDRESS
SDA Line
A
C
DATA n
DATA n +1
DATA n + 2
DATA n + x
K
DS800041-20
Typical System Configuration (Figure 11)
V
CC
SDA
SCL
Master
Transmitter/
Receiver
Slave
Transmitter/
Receiver
Master
Transmitter/
Receiver
Master
Transmitter
Slave
Receiver
DS800041-21
Note:
Due to open drain configuration of SDA, a bus-level resistor is called for
(Typical value = 4.7Ω)
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FM34W02 Rev. A
Physical Dimensions inches (millimeters) unless otherwise noted
0.189 - 0.197
(4.800 - 5.004)
8
7
6
3
5
4
0.228 - 0.244
(5.791 - 6.198)
1
2
Lead #1
IDENT
0.150 - 0.157
(3.810 - 3.988)
0.053 - 0.069
(1.346 - 1.753)
0.010 - 0.020
(0.254 - 0.508)
0.004 - 0.010
(0.102 - 0.254)
x 45¡
8¡ Max, Typ.
All leads
Seating
Plane
0.004
(0.102)
All lead tips
0.0075 - 0.0098
(0.190 - 0.249)
Typ. All Leads
0.014
(0.356)
0.016 - 0.050
(0.406 - 1.270)
Typ. All Leads
0.050
(1.270)
Typ
0.014 - 0.020
Typ.
(0.356 - 0.508)
8-Pin Molded Small Outline Package (M8)
Order Number FM34W02LM8/LZM8
Package Number M08A
11
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FM34W02 Rev. A
Physical Dimensions inches (millimeters) unless otherwise noted
0.114 - 0.122
(2.90 - 3.10)
8
5
(7.72) Typ
(4.16) Typ
0.169 - 0.177
(4.30 - 4.50)
0.246 - 0.256
(6.25 - 6.5)
(1.78) Typ
(0.42) Typ
0.123 - 0.128
(3.13 - 3.30)
(0.65) Typ
Land pattern recommendation
1
4
Pin #1 IDENT
0.0433
Max
(1.1)
0.0035 - 0.0079
See detail A
0.002 - 0.0118
(0.05 - 0.15)
0.0256 (0.65)
Typ.
Gage
plane
0.0075 - 0.0098
(0.19 - 0.30)
0¡-8¡
DETAIL A
Typ. Scale: 40X
0.0075 - 0.0098
(0.19 - 0.25)
0.020 - 0.028
(0.50 - 0.70)
Seating
plane
Notes: Unless otherwise specified
1. Reference JEDEC registration MO153. Variation AA. Dated 7/93
8-Pin Molded TSSOP, JEDEC (MT8)
Order Number FM34W02LMT8/LZMT8
Package Number MTC08
Life Support Policy
Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written
approval of the President of Fairchild Semiconductor Corporation. As used herein:
1. Life support devices or systems are devices or systems which,
(a)areintendedforsurgicalimplantintothebody,or(b)support
or sustain life, and whose failure to perform, when properly
used in accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a significant
injury to the user.
2. A critical component is any component of a life support device
or system whose failure to perform can be reasonably ex-
pected to cause the failure of the life support device or system,
or to affect its safety or effectiveness.
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Fairchild Semiconductor
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
12
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FM34W02 Rev. A
相关型号：
FM34W02UE
2K-Bit Standard 2-Wire Bus Interface Serial EEPROM with Full Array Write Protect
FAIRCHILD
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