FM93C86ATLMT8 [FAIRCHILD]
EEPROM, 1KX16, Serial, CMOS, PDSO8;
| 型号： | FM93C86ATLMT8 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | EEPROM, 1KX16, Serial, CMOS, PDSO8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 光电二极管 |
| 文件： | 总11页 (文件大小：93K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
January 2000
FM93C86A
16K-Bit Serial EEPROM
(MICROWIRE™ Bus Interface)
General Description
Features
The FM93C86A is 16,384 bits of CMOS nonvolatile EEPROM
(Electrically Erasable Programmable Read Only Memory) with
MICROWIRE serial interface. FM93C86A can be configured for
either 1024 x 16 bit or 2048 x 8 bit array using an organization
(ORG) input pin. This device is fabricated using Fairchild
Semiconductor's floating gate CMOS process for high reliability,
high endurance and low power consumption. This device is
available in 8-pin DIP and SO packages.
I 2.7V to 5.5V operation in all modes
I Typical active current of 200µA
10µA standby current typical
1µA standby current typical (L)
0.1µA standby current typical (LZ)
I Device status indication during programming mode
I No erase required before write
I Reliable CMOS floating gate technology
I MICROWIRE™ compatible serial I/O
I Self-timed programming cycle
The MICROWIRE serial interface offered by this EEPROM en-
ables simple interface to a wide variety of microcontrollers and
microprocessors. There are 7 instructions that operate the
FM93C86A: Read, Erase/Write Enable, Erase, Write, Erase/
Write Disable, Write All and Erase All.
I 40 years data retention
I Endurance: 1,000,000 data changes
I Packages available: 8-pin SO, 8-pin DIP
I Schmitt Trigger inputs and VCC lockout to prevent data
corruption
Block Diagram
CS
V
CC
Instruction
Decoder
SK
Control Logic,
And Clock
Generators
Instruction
Register
DI
High Voltage
Generator
And
Address
Register
ORG
Program
Timer
V
PP
EEPROM Array
16384 Bits
(1024x16) or (2048x8)
Decoder
1 of 1024
(or 2048)
Read/Write Amps
Data In/Out Register
16 (or 8) Bits
GND
Data Out Buffer
DO
DS800031-12
1
© 1999 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FM93C86A Rev. A
Connection Diagram
Dual-In-Line Package (N)
and 8-Pin SO Package (M8)
CS
SK
DI
1
2
3
4
8
7
6
5
VCC
NC
NM93C86A
ORG
VSS
DO
DS800031-14
Top View
See Package Number
N08E and M08A
Pin Names
Pin
Description
CS
SK
Chip Select
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
DI
DO
VSS
ORG
NC
Memory Organization Select
No Connect
VCC
Positive Power Supply
Ordering Information
FM
93
C
XX
A
LZ
E
XX
Letter Description
Package
N
M8
8-Pin DIP
8-Pin SO8
Temp. Range
None
0 to 70°C
V
E
-40 to +125°C
-40 to +85°C
Voltage Operating Range
Blank
L
4.5V to 5.5V
2.7V to 5.5V
LZ
2.7V to 5.5V and
<1µA Standby Current
A
x8 or x16 Configuration
16K
Density
86
C
CMOS
Interface
93
FM
MICROWIRE
Fairchild Non-Volatile
Memory
2
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FM93C86A Rev. A
Absolute Maximum Ratings (Note 1)
Operating Range
Ambient Storage Temperature
-65°C to +150°C
Ambient Operating Temperature
FM93C86A
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
All Input or Output Voltage
with Respect to Ground
FM93C86AE
FM93C86AV
VCC + 1 to -0.3V
Lead Temperature
Power Supply (VCC) Range
4.5V to 5.5V
(Soldering, 10 seconds)
+300°C
ESD Rating
2000V
DC and AC Electrical Characteristics 4.5V ≤ VCC ≤ 5.5V
Symbol
Parameter
Part Number
Conditions
Min
Max
Units
ICCA
Operating Current
CS = VIH, SK=1 MHz
1
mA
ICCS
IIL
Standby Current
Input Leakage
CS = 0V ORG = VCC or NC
VIN = 0V to VCC (Note 2)
50
1
µA
µA
-1
IILO
Input Leakage ORG Pin
ORG tied to VCC
ORG tied to VSS
(Note 3)
-1
-2.5
1
2.5
µA
IOL
VIL
Output Leakage
VIN = 0V to VCC
-1
-0.1
2
1
0.8
µA
V
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
SK Clock Frequency
SK High Time
VIH
VCC +1
0.4
V
VOL1
VOH1
VOL2
VOH2
fSK
IOL = 2.1 mA
IOH = -400 µA
IOL = 10 µA
IOL = -10 µA
(Note 4)
V
2.4
V
0.2
1
V
VCC - 0.2
0
V
MHz
ns
tSKH
FM93C86A
FM93C86AE/V
250
300
tSKL
tSKS
SK Low Time
250
50
ns
ns
SK Setup Time
SK must be at VIL for
tSKS before CS goes
high
tCS
Minimum CS Low Time
(Note 5)
250
ns
tCSS
tDH
CS Set-up Time
DO Hold Time
50
70
ns
ns
tDIS
DI Set-up Time
FM93C86A
FM93C86AE/V
100
200
ns
tCSH
tDIH
tPD
tSV
CS Hold Time
DI Hold Time
0
ns
ns
20
Output Delay
500
500
ns
ns
CS to Status Valid
tDF
CS to DO in Hi-Z
Write Cycle Time
100
10
ns
tWP
ms
3
www.fairchildsemi.com
FM93C86A Rev. A
Absolute Maximum Ratings (Note 1)
Operating Range
Ambient Operating Temperature
Ambient Storage Temperature
–65°C to +150°C
FM93C86AL/LZ
FM93C86ALE/LZE
FM93C86ALV/LZV
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
All Input or Output Voltage
with Respect to Ground
+6.5V to -0.3V
Lead Temperature (Soldering, 10 sec.)
ESD Rating
+300°C
Power Supply (VCC
)
2.7V to 5.5V
2000V
DC and AC Electrical Characteristics VCC = 2.7V to 5.5V unless otherwise specified
Symbol
Parameter
Part Number
Conditions
Min.
Max.
Units
ICCA
ICCS
Operating Current
CS = VIH, SK = 250KHz
CS = VIL
1
mA
Standby Current
L
LZ
10
1
µA
µA
IIL
Input Leakage
VIN = 0V to VCC (Note 2)
1
µA
µA
IILO
Input Leakage
ORG Pin
ORG tied to VCC
ORG tied to VSS (Note 3)
-1
-2.5
1
2.5
IOL
Output Leakage
VIN = 0V to VCC
1
µA
VIL
VIH
Input Low Voltage
Input High Voltage
-0.1
0.8 VCC
0.15 VCC
VCC +1
V
VOL
VOH
Output Low Voltage
Output High Voltage
IOL = 10 µA
IOH = -10 µA
0.1 VCC
V
V
0.9 VCC
fSK
SK Clock Frequency
SK High Time
(Note 4)
0
1
250
KHz
µs
tSKH
tSKL
tSKS
SK Low Time
1
µs
SK Setup Time
SK must be at VIL for
tSKS before CS goes high
0.2
µs
tCS
Minimum CS
Low Time
(Note 5)
1
µs
tCSS
tDH
CS Setup Time
DO Hold Time
DI Setup Time
CS Hold Time
DI Hold Time
0.2
70
0.4
0
µs
ns
µs
ns
µs
µs
µs
µs
ms
tDIS
tCSH
tDIH
tPD
0.4
Output Delay
2
1
tSV
CS to Status Valid
CS to DO in Hi-Z
Write Cycle Time
tDF
CS = VIL
0.4
15
tWP
Note 1: Stress above those listed under “Absolute Maximum Ratings” may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or any
other conditions above those indicated in the operational sections of the specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Capacitance TA = 25°C, f = 1 MHz
Symbol
Test
Typ Max Units
Note 2: Typical leakage values are in the 20 nA range.
Note 3: The ORG pin may draw > 1 µA when in the x8 mode ude to an internal pull-up transistor.
COUT
CIN
Output Capacitance
Input Capacitance
5
5
pF
pF
Note 4: The shortest allowable SK clock period = 1/fSK (as shown under the fSK fSK parameter).
Maximum SK clock speed (minimum SK period) is determined by the interaction of several AC
parameters stated in the datasheet. Within this SK period, both tSKH and tSKL limits must be observed.
Therefore, it is not allowable to set 1/fSK = tSKHminimum + tSKLminimum for shorter SK cycle time operation.
Note 5: CS (Chip Select) must be brought low (to VIL) for an interval of tCS in order to reset all
internal device registers (device reset) prior to beginning another opcode cycle. (This is shown in
the opcode diagrams in the following pages.)
AC Test Conditions
VCC Range
VIL/VIH
Input Levels
.03V/1.8V
VIL/VIH
Timing Level
VOL/VOH
Timing Level
0.8V/1.5V
IOL/IOH
2.7V ≤ VCC ≤ 5.5V
(Extended Voltage Levels)
1.0V
10µA
4.5V ≤ VCC ≤ 5.5V
0.4V/2.4V
1.0V/2.0V
0.4V/2.4V
2.1mA/-0.4mA
(TTL Levels)
Output Load: 1 TTL Gate (CL = 100 pF)
4
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FM93C86A Rev. A
Serial Clock (SK):
MICROWIRE I/O Pin Description
This pin is the clock input (rising edge active) for clocking in all
opcodesanddataontheDIpinandclockingoutalldataontheDO
pin.However,thispinhasnoeffectontheasynchronousprogram-
ming cycle (see the CS pin section) as the BUSY/READY status
is a function of the CS pin only.
Chip Select (CS):
This pin enables and disables the MICROWIRE device and
performs 2 general functions:
1. When in the low state, the MICROWIRE device is disabled
and the output tri-stated (high impedance). If this pin is
brought high (rising edge active), all internal registers are
reset and the device is enabled, allowing MICROWIRE
communication via DI/DO pins. To restate, the CS pin must
be held high during all device communication and opcode
functions. If the CS pin is brought low, all functions will be
disabled and reset when CS is brought high again. The
exception to this is when a programming cycle is initiated.
Again, all activity on the CS, DI and DO pins is ignored until
CS is brought high.
Data-In (DI):
All serial communication into the device is performed using this
input pin (rising edge active). In order to avoid false Start Bits, or
related issues, it is advised to keep the DI pin in the low state
unless actually clocking in data bits (Start Bit, Opcode, Address or
incoming data bits to be programmed). Please note that the first
'1' clocked into the device (after CS is brought high) is seen as a
Start Bit and the beginning of a serial command string, so caution
must be observed when bringing CS high.
2. When programming is in progress, the Data-Out pin will
display the programming status as either BUSY (DO low) or
READY (DO high) when CS is brought high. (Again, the
output will be tri-stated when CS is low.) To restate, during
programming, the CS pin may be brought high and low any
number of times to view the programming status without
affect the programming operation. Once programming is
completed (Output in READY state), the output is 'cleared'
(returned to normal tri-state condition) by clocking in a Start
Bit. After the Start Bit is clocked in, the output will return to a
tri-stated condition. When clocked in, this Start Bit can be the
first bit in a command string, or CS can be brought low again
to reset all internal circuits.
Data-Out (DO):
All serial communication out of the device, Read Data ( during
normal reads) as well as READY/BUSY status indication ( during
programming ) are performed using this output pin. Note that,
during READ operations, the EEPROM device starts to drive the
DO output pin "active" after the last address bit (A0) is clocked in.
Hence in applications where 3-wire configuration is required (
whereDIandDOpinsaretiedtogether)cautionmustbeobserved
for correct operation. Please refer AN-758 for further information.
Organization (ORG):
This pin controls the device architecture (8-bit data word vs. 16-bit
data word). If the ORG pin is brought to VCC, the device is
configured with a 16-bit data word and if the ORG pin is brought
to VSS (Ground), the device is configured with an 8-bit data word.
If the ORG pin is left floating, the device will default to a 16-bit data
word.
Unlike the lower density members of the Microwire product
family (FM93C06, FM93C46, FM93C56, FM93C66)
programming is not initiated by bringing CS low but initiated
as soon as the last bit of information (address bit or data bit
depending on the instruction type) is clocked in. Refer the
section on Programming for further detail.
Instruction Set for the FM93C86A
ORG
Memory
Pin
Logic
Configuration
# of Address Bits
0
1
2048 x 8
11 Bits
10 Bits
1024 x 16
5
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FM93C86A Rev. A
1024 by 16-Bit Organization (FM93C86A when ORG = VCC or NC)
Instruction SB Op Code Address
Data
Function
2 Bits
10
10 Bits
16 Bits
READ
EWEN
EWDS
ERASE
WRITE
ERAL
1
1
1
1
1
1
1
A9–A0
Read data stored in selected registers.
Enables programming modes.
00
11XXXXXXXX
00XXXXXXXX
A9–A0
00
Disables all programming modes.
Erases selected register.
11
01
A9–A0
D15–D0
D15–D0
Writes data pattern D15–D0 into selected register.
Erases all registers.
00
10XXXXXXXX
01XXXXXXXX
WRAL
00
Writes data pattern D15–D0 into all registers.
X = Don't care.
2048 by 8-Bit Organization (FM93C86A when ORG = GND)
Instruction SB Op Code Address
Data
Function
2 Bits
10
11 Bits
8 Bits
READ
EWEN
EWDS
ERASE
WRITE
ERAL
1
1
1
1
1
1
1
A10–A0
Read data stored in selected registers.
Enables programming modes.
00
11XXXXXXXXX
00XXXXXXXXX
A10–A0
00
Disables all programming modes.
Erases selected register.
11
01
A10–A0
D7–D0
D7–D0
Writes data pattern D7–D0 into selected register.
Erases all registers.
00
10XXXXXXXXX
01XXXXXXXXX
WRAL
00
Writes data pattern D7–D0 into all registers.
X = Don't care.
BUSYstatusofthedevice.DO=logical“0”indicatesthatprogram-
ming is still in progress and no other instruction can be executed.
DO = logical “1” indicates that the device is READY for another
instruction. If CS is forced “low” the DO pin will return to the high
impedance state. After the programming cycle has been com-
pleted and DO = logical “1”, the DO pin can be reset back to the
high impedance state by clocking a logical “1” into the DI pin. (This
is also performed with the start bit on all op codes, thus clocking
an instruction has the same effect.)
Functional Description
Programming
The programming cycle is automatically started after entering the
LAST bit of the programming instruction string (unlike other
Microwire family members which use the falling edge of CS to
initiate programming). This feature, counting the number of in-
struction bits, decreases the likelihood of inadvertent program-
ming and allows the programming to be cancelled before sending
out the last bit in the string (by bringing CS low).
Read (READ)
The READ instruction outputs serial data on the DO pin. After a
READ instruction is received, the instruction and address are
decoded, followed by data transfer from the selected memory
register into a serial-out shift register. A dummy bit (logical 0)
precedes the serial data output string. Output data changes are
initiatedbyalowtohightransitionofSKclockafterthelastaddress
bit (A0) is clocked in.
Programming Instruction Last Bit in String
WRITE
WRAL
ERASE
ERAL
D0
D0
A0
A0
Erase/Write Enable (EWEN)
Note that, in the ERASE/ERAL instructions, the A0 bit is the last
bit in the string and clocking in that bit will initiate programming. In
order to maintain compatibility, CS may be brought low after
clocking in the last bit, but it is not necessary.
When VCC is applied to the part, it “powers up” in the Erase/Write
Disable (EWDS) state. Therefore, all programming modes must
be preceded by an Erase/Write Enable (EWEN) instruction. Once
an Erase/Write Enable instruction is executed, programming
remains enabled until an Erase/Write Disable (EWDS) instruction
is executed or VCC is removed from the part.
In all programming modes the READY/BUSY status of the device
can be determined by polling the DO pin. After clocking in the last
bit of the instruction sequence and with the CS held “high”, the DO
pin will exit the high impedance state and indicate the READY/
6
www.fairchildsemi.com
FM93C86A Rev. A
instruction will be aborted. The self-timed programming cycle is
initiated on the rising edge of the SK clock as the last data bit (D0)
is clocked in. At this point, CS, SK and DI become don’t care
states. No separate ERASE cycle is required before a WRITE
instruction.
Functional Description (Continued)
Erase/Write Disable (EWDS)
To protect against accidental data overwrites, the Erase/Write
Disable (EWDS) instruction disables all programming modes and
should follow all programming operations. Execution of a READ
instruction is independent of both the EWEN and EWDS instruc-
tions.
As in the ERASE instruction, after starting a WRITE cycle, the DO
pin indicates the READY/BUSY status of the chip if CS is held
“high”. DO = logical “0” indicates that programming is still in
progress. DO = logical “1” indicates that the register, at the
address specified in the instruction, has been written and that the
part is ready for another instruction.
Erase (ERASE)
The ERASE instruction will program all bits in the specified
register to the logical “1” state. The self-timed programming cycle
is initiated on the rising edge of the SK clock as the last address
bit(A0)isclockedin.AtthispointCS,SKandDIbecomedon’tcare
states. After starting an Erase cycle the DO pin indicates the
READY/BUSY status of the chip if CS is held “high”. DO = logical
“0” indicates that programming is still in progress. DO = logical “1”
indicates that the register, at the address specified in the instruc-
tion, has been erased.
Erase All (ERAL)
The ERAL instruction will simultaneously program all registers in
the memory array to the logical “1” state.
Write All (WRAL)
The WRAL instruction will simultaneously program all registers
with the data pattern specified in the instruction.
Write (WRITE)
The WRITE instruction is followed by 16 bits of data (or 8 bits of
data when using the FM93C86A in the x8 organization) to be
written into the specified address. Note that if the CS is brought
“low” before clocking in all of the data bits, then the WRITE
Timing Diagrams for the FM93C86A
Synchronous Data Timing
V
IH
CS
SK
V
t
IL
CSS
t
t
t
CSH
SKH
SKL
t
SKS
V
IH
V
IL
t
t
DIH
DIS
V
IH
DI
V
IL
t
PD
t
DF
t
DH
V
OH
DO (READ)
V
OL
t
SV
t
t
DF
DH
V
OH
DO (PROGRAM)
STATUS VALID
V
OL
DS800031-3
7
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FM93C86A Rev. A
Timing Diagrams for the FM93C86A (Continued)
Key for Timing Diagrams
Organization of Address and Data Fields for the FM93C86A
ORG
VCC or NC
VSS
Organization
1024 x 16
AN
A9
DN
D15
D7
2048 x 8
A10
READ
CS
SK
DI
t
CS
. . .
1
1
0
A
N
A
0
. . .
DO
0
D
D
0
N
DS800031-4
DS800031-5
DS800031-6
EWEN
DO = HI-Z
t
CS
CS
SK
DI
. . .
X
X
1
0
0
1
1
ORG = V , 4 X’S
CC
ORG = V , 5 X’S
SS
EWDS
DO = HI-Z
tCS
CS
SK
DI
. . .
X
X
1
0
0
0
0
ORG = V , 4 X’S
CC
ORG = V , 5 X’S
SS
ERASE
tCS
CS
SK
Standby
DI
. . .
A0
AN
1
1
1
HI-Z
HI-Z
Busy
Ready
DO
tWP
DS800031-7
8
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FM93C86A Rev. A
Timing Diagrams for the FM93C86A (Continued)
WRITE
tCS
CS
SK
. . .
. . .
1
0
1
AN
A0 DN
D0
DI
Busy
Ready
DO
tWP
DS800031-8
ERAL
tCS
CS
STANDBY
SK
DI
. . .
1
0
0
1
0
X
X
ORG = VCC, 4 X's
ORG = VSS, 5 X's
READY
DO
BUSY
READY STATUS SIGNAL RESETS
TO HI-Z AFTER CLOCKING IN
ONE SK CYCLE WITH DI = 1
tWP
DS800031-9
WRAL
tCS
CS
SK
DI
STANDBY
. . .
. . .
D0
1
0
0
0
1
X
X
DN
ORG = VCC, 4 X's
ORG = VSS, 5 X's
READY
BUSY
DO
READY STATUS SIGNAL RESETS
TO HI-Z AFTER CLOCKING IN
ONE SK CYCLE WITH DI = 1
tWP
DS800031-10
9
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FM93C86A Rev. A
Physical Dimensions inches (millimeters) unless otherwise noted
0.189 - 0.197
(4.800 - 5.004)
8
7
6
5
0.228 - 0.244
(5.791 - 6.198)
1
2
3
4
Lead #1
IDENT
0.150 - 0.157
(3.810 - 3.988)
0.053 - 0.069
(1.346 - 1.753)
0.010 - 0.020
(0.254 - 0.508)
0.004 - 0.010
(0.102 - 0.254)
x 45°
8° Max, Typ.
All leads
Seating
Plane
0.04
0.0075 - 0.0098
(0.190 - 0.249)
Typ. All Leads
(0.102)
All lead tips
0.014
(0.356)
0.016 - 0.050
(0.406 - 1.270)
Typ. All Leads
0.050
(1.270)
Typ
0.014 - 0.020
(0.356 - 0.508)
Typ.
Molded Small Outline Package (M8)
Package Number M08A
10
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FM93C86A Rev. A
Physical Dimensions inches (millimeters) unless otherwise noted
0.373 - 0.400
(9.474 - 10.16)
0.090
(2.286)
8
7
0.032 0.005
(0.813 0.127)
RAD
8
7
6
5
4
0.092
(2.337)
DIA
0.250 - 0.005
(6.35 0.127)
Pin #1
IDENT
+
Pin #1 IDENT
1
Option 1
1
2
3
Option 2
0.280
MIN
0.040
(1.016)
Typ.
(7.112)
0.030
0.145 - 0.200
(3.683 - 5.080)
0.039
(0.991)
MAX
(0.762)
0.300 - 0.320
(7.62 - 8.128)
20° 1°
0.130 0.005
(3.302 0.127)
0.125 - 0.140
95° 5°
(3.175 - 3.556)
0.065
(1.651)
0.125
(3.175)
DIA
0.020
90° 4°
Typ
0.009 - 0.015
(0.229 - 0.381)
(0.508)
Min
0.018 0.003
(0.457 0.076)
NOM
+0.040
-0.015
0.325
0.100 0.010
+1.016
-0.381
8.255
(2.540 0.254)
0.045 0.015
(1.143 0.381)
0.060
(1.524)
0.050
(1.270)
Molded Dual-in-Line Package (N)
Package Number N08E
Life Support Policy
Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written
approval of the President of Fairchild Semiconductor Corporation. As used herein:
1. Life support devices or systems are devices or systems which,
(a)areintendedforsurgicalimplantintothebody,or(b)support
or sustain life, and whose failure to perform, when properly
used in accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a significant
injury to the user.
2. A critical component is any component of a life support device
or system whose failure to perform can be reasonably ex-
pected to cause the failure of the life support device or system,
or to affect its safety or effectiveness.
Fairchild Semiconductor
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Fairchild Semiconductor
Japan Ltd.
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11
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