FM93CS56TLZEMT8

更新时间:2024-10-30 02:50:23
品牌:FAIRCHILD
描述:EEPROM, 128X16, Serial, CMOS, PDSO8, PLASTIC, TSSOP-8

FM93CS56TLZEMT8 概述

EEPROM, 128X16, Serial, CMOS, PDSO8, PLASTIC, TSSOP-8 EEPROM

FM93CS56TLZEMT8 规格参数

生命周期:Obsolete零件包装代码:SOIC
包装说明:TSSOP,针数:8
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.51风险等级:5.76
JESD-30 代码:R-PDSO-G8长度:4.4 mm
内存密度:2048 bit内存集成电路类型:EEPROM
内存宽度:16功能数量:1
端子数量:8字数:128 words
字数代码:128工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:128X16封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH并行/串行:SERIAL
认证状态:Not Qualified座面最大高度:1.2 mm
串行总线类型:MICROWIRE最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):2.7 V标称供电电压 (Vsup):3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
宽度:3 mm

FM93CS56TLZEMT8 数据手册

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December 1999  
FM93C56  
2K-Bit Serial CMOS EEPROM  
(MICROWIRE™ Bus Interface)  
General Description  
Features  
The FM93C56 device is 2048 bits of CMOS non-volatile electri-  
cally erasable memory organized as 128x16 bit array. They are  
fabricated using Fairchild Semiconductor's floating-gate CMOS  
process for high reliability, high endurance and low power con-  
sumption. These memory devices are available in an 8-pin SOIC  
or 8-pin TSSOP package for small space considerations.  
I Device status during programming mode  
I Typical active current of 200µA  
10µA standby current typical  
1µA standby current typical (L)  
0.1µA standby current typical (LZ)  
I No erase required before write  
I Reliable CMOS floating gate technology  
I 2.7V to 5.5V operation in all modes  
I MICROWIRE compatible serial l/O  
I Self-timed programming cycle  
I 40 years data retention  
FM93C56 is compatible with MICROWIRE serial interface, which  
offers simple interface to standard microcontrollers and micropro-  
cessors. There are 7 instructions which control this device: Read,  
WriteEnable, Erase, EraseAll, Write, WriteAll, andWriteDisable.  
The ready/busy status is available on the DO pin to indicate the  
completion of a programming cycle.  
I Endurance: 1,000,000 data changes  
I Packages available: 8-pin SO, 8-pin DIP, 8-pin TSSOP  
I Schmitt Trigger inputs and VCC lockout to prevent data  
corruption  
Block Diagram  
VCC  
CS  
SK  
INSTRUCTION  
DECODER  
CONTROL LOGIC,  
AND CLOCK  
GENERATORS  
INSTRUCTION  
REGISTER  
DI  
HIGH VOLTAGE  
GENERATOR  
AND  
ADDRESS  
REGISTER  
PROGRAM  
TIMER  
VPP  
DECODER  
1 OF 128  
EEPROM ARRAY  
16  
READ/WRITE AMPS  
16  
VSS  
DATA IN/OUT REGISTER  
16 BITS  
DO  
DATA OUT BUFFER  
DS800026-1  
1
© 1999 Fairchild Semiconductor Corporation  
FM93C56  
www.fairchildsemi.com  
Connection Diagrams  
Dual-In-Line Package (N),  
8-Pin SO (M8) and 8-Pin TSSOP (MT8)  
Rotated Die (93C56T)  
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
CS  
SK  
DI  
NC  
VCC  
NC  
NC  
GND  
DO  
DI  
V
CC  
CS  
NC  
DO  
GND  
SK  
DS800026-2  
DS800026-12  
Top View  
See Package Number  
N08E, M08A and MTC08  
Pin Names  
CS  
Chip Select  
SK  
Serial Data Clock  
Serial Data Input  
DI  
DO  
GND  
VCC  
Serial Data Output  
Ground  
Power Supply  
Ordering Information  
FM  
93  
C
XX  
T
LZ  
E
XX  
Letter Description  
Package  
N
8-Pin DIP  
M8  
MT8  
8-Pin SO8  
8-Pin TSSOP  
Temp. Range  
None  
0 to 70°C  
V
E
-40 to +125°C  
-40 to +85°C  
Voltage Operating Range  
Blank  
L
4.5V to 5.5V  
2.7V to 5.5V  
LZ  
2.7V to 5.5V and  
<1µA Standby Current  
Blank  
T
Normal Pin Out  
Rotated Die Pin Out  
Density  
56  
2K  
C
CMOS  
CS  
Data protect and sequential  
read  
Interface  
93  
MICROWIRE  
FM  
Fairchild Non-Volatile  
Memory  
2
www.fairchildsemi.com  
FM93C56  
Absolute Maximum Ratings (Note 1)  
Operating Range  
Ambient Storage Temperature  
–65°C to +150°C  
Ambient Operating Temperature  
FM93C56  
0°C to +70°C  
-40°C to +85°C  
-40°C to +125°C  
All Input or Output Voltage  
with Respect to Ground  
+6.5V to -0.3V  
FM93C56E  
FM93C56V  
Lead Temperature (Soldering, 10 sec.)  
ESD Rating  
+300°C  
Power Supply (VCC  
)
4.5V to 5.5V  
2000V  
DC and AC Electrical Characteristics 4.5V VCC 5.5V  
Symbol  
Parameter  
Part Number  
Conditions  
Min.  
Max.  
Units  
ICCA  
ICCS  
Operating Current  
Standby Current  
CS = VIH, SK = 1MHz  
CS = VIL  
1
50  
1
mA  
µA  
µA  
IIL  
IOL  
Input Leakage  
Output Leakage  
VIN = 0V to VCC  
(Note 2)  
VIL  
VIH  
Input Low Voltage  
Input High Voltage  
-0.1  
2
0.8  
VCC +1  
V
VOL1  
VOH1  
Output Low Voltage  
Output High Voltage  
IOL = 2.1mA  
IOH = -400 µA  
0.4  
0.2  
1
V
V
2.4  
VOL2  
VOH2  
Output Low Voltage  
Output High Voltage  
IOL = 10 µA  
IOH = -10 µA  
V
V
VCC -0.2  
0
fSK  
SK Clock Frequency  
SK High Time  
(Note 3)  
MHz  
ns  
tSKH  
FM93C56  
FM93C56E/V  
250  
300  
tSKL  
tSKS  
SK Low Time  
250  
50  
ns  
ns  
SK Setup Time  
SK must be at VIL for  
tSKS before CS goes  
high  
tCS  
Minimum CS  
Low Time  
(Note 4)  
250  
ns  
tCSS  
tDH  
CS Setup Time  
DO Hold Time  
DI Setup Time  
50  
70  
ns  
ns  
ns  
tDIS  
FM93C56  
FM93C56E/V  
100  
200  
tCSH  
tDIH  
tPD  
CS Hold Time  
0
ns  
ns  
ns  
ns  
ns  
ms  
DI Hold Time  
20  
Output Delay  
500  
500  
100  
10  
tSV  
CS to Status Valid  
CS to DO in Hi-Z  
Write Cycle Time  
tDF  
CS = VIL  
tWP  
3
www.fairchildsemi.com  
FM93C56  
Absolute Maximum Ratings (Note 1)  
Operating Range  
Ambient Storage Temperature  
–65°C to +150°C  
Ambient Operating Temperature  
FM93C56L/LZ  
0°C to +70°C  
-40°C to +85°C  
-40°C to +125°C  
All Input or Output Voltage  
with Respect to Ground  
+6.5V to -0.3V  
FM93C56LE/LZE  
FM93C56LV/LZV  
Lead Temperature (Soldering, 10 sec.)  
ESD Rating  
+300°C  
Power Supply (VCC  
)
2.7V to 5.5V  
2000V  
DC and AC Electrical Characteristics VCC = 2.7V to 5.5V unless otherwise specified  
Symbol  
Parameter  
Part Number  
Conditions  
Min.  
Max.  
Units  
ICCA  
ICCS  
Operating Current  
CS = VIH, SK = 250KHz  
CS = VIL  
1
mA  
Standby Current  
L
LZ  
10  
1
µA  
µA  
IIL  
IOL  
Input Leakage  
Output Leakage  
VIN = 0V to VCC  
(Note 2)  
1
µA  
VIL  
VIH  
Input Low Voltage  
Input High Voltage  
-0.1  
0.8 VCC  
0.15 VCC  
VCC +1  
V
VOL  
VOH  
Output Low Voltage  
Output High Voltage  
IOL = 10 µA  
IOH = -10 µA  
0.1 VCC  
V
V
0.9 VCC  
fSK  
SK Clock Frequency  
SK High Time  
(Note 3)  
0
1
250  
KHz  
µs  
tSKH  
tSKL  
tSKS  
SK Low Time  
1
µs  
SK Setup Time  
SK must be at VIL for  
tSKS before CS goes  
high  
0.2  
µs  
tCS  
Minimum CS  
Low Time  
(Note 4)  
1
µs  
tCSS  
tDH  
CS Setup Time  
DO Hold Time  
DI Setup Time  
CS Hold Time  
DI Hold Time  
0.2  
70  
0.4  
0
µs  
ns  
µs  
ns  
µs  
µs  
µs  
µs  
ms  
tDIS  
tCSH  
tDIH  
tPD  
0.4  
Output Delay  
2
1
tSV  
CS to Status Valid  
CS to DO in Hi-Z  
Write Cycle Time  
tDF  
CS = VIL  
0.4  
15  
tWP  
Note 1: Stress above those listed under “Absolute Maximum Ratings” may cause permanent  
damage to the device. This is a stress rating only and functional operation of the device at these or any  
other conditions above those indicated in the operational sections of the specification is not implied.  
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.  
Capacitance TA = 25°C, f = 1 MHz (Note 5)  
Symbol  
Test  
Typ Max Units  
Note 2: Typical leakage values are in the 20nA range.  
Note 3: The shortest allowable SK clock period = 1/fSK (as shown under the fSK parameter).  
Maximum SK clock speed (minimum SK period) is determined by the interaction of several AC  
parametersstatedinthedatasheet.WithinthisSKperiod,bothtSKH andtSKL limitsmustbeobserved.  
Therefore,itisnotallowabletoset1/fSK =tSKHminimum +tSKLminimum forshorterSKcycletimeoperation.  
COUT  
CIN  
Output Capacitance  
Input Capacitance  
5
5
pF  
pF  
Note 4: CS (Chip Select) must be brought low (to VIL) for an interval of tCS in order to reset all  
internaldeviceregisters(devicereset)priortobeginninganotheropcodecycle. (Thisisshowninthe  
opcode diagram on the following page.)  
Note 5: This parameter is periodically sampled and not 100% tested.  
AC Test Conditions  
VCC Range  
VIL/VIH  
Input Levels  
.03V/1.8V  
VIL/VIH  
Timing Level  
VOL/VOH  
Timing Level  
0.8V/1.5V  
IOL/IOH  
2.7V VCC 5.5V  
(Extended Voltage Levels)  
1.0V  
10µA  
4.5V VCC 5.5V  
0.4V/2.4V  
1.0V/2.0V  
0.4V/2.4V  
2.1mA/-0.4mA  
(TTL Levels)  
Output Load: 1 TTL Gate (CL = 100 pF)  
4
www.fairchildsemi.com  
FM93C56  
Write (WRITE):  
Functional Description  
TheWRITEinstructionisfollowedbytheaddressand16bitsofdata  
to be written into the specified address. After the last bit of data is  
put in the data-in (DI) pin, CS must be brought low before the next  
rising edge of the SK clock. This falling edge of the CS initiates the  
self-timed programming cycle. The D0 pin indicates the READY/  
The FM93C56device has7 instructionsas describedbelow. Note  
that the MSB of any instruction is a “1” and is viewed as a start bit  
in the interface sequence. The next 10 bits carry the op code and  
the 8-bit address for register selection.  
Read (READ):  
BUSYstatusofthechipifCSisbroughthighafteraminimumoft  
.
CS  
D0 = logical 1 indicates that the register at the address specified in  
theinstructionhasbeenwrittenwiththedatapatternspecifiedinthe  
instruction and the part is ready for another instruction.  
The READ instruction outputs serial data on the D0 pin. After a  
READ instruction is received, the instruction and address are  
decoded, followed by data transfer from the selected memory  
register into a 16-bit serial-out shift register. A dummy bit (logical  
0)precedesthe16-bitdataoutputstring. Outputdatachangesare  
initiated by a low to high transition of the SK clock.  
Erase All (ERAL):  
The ERAL instruction will simultaneously program all registers in  
thememoryarrayandseteachbittothelogical1state.TheErase  
All cycle is identical to the ERASE cycle except for the different op-  
code. As in the ERASE mode, the DO pin indicates the READY/  
BUSY status of the chip if CS is brought high after the tCS interval.  
Write Enable (WEN):  
When VCC is applied to the part, it 'powers-up' in the Write Disable  
(WDS) state. Therefore, all programming modes must be pre-  
ceded by a Write Enable (WEN) instruction. Once a Write Enable  
instructionisexecuted,programmingremainsenableduntilaWrite  
Disable (WDS) instruction is executed or VCC is removed from the  
part.  
Write All (WRALL):  
The WRALL instruction will simultaneously program all registers  
with the data pattern specified in the instruction. As in the WRITE  
mode, the DO pin indicates the READY/BUSY status of the chip  
Erase (ERASE):  
if CS is brought high after the t interval.  
CS  
The ERASE instruction will program all bits in the specified  
register to the logical “1” state. CS is brought low following the  
loading of the last address bit. This falling edge of the CS pin  
initiates the self-timed programming cycle.  
Write Disable (WDS):  
To protect against accidental data disturb, the WDS instruction  
disables all programming modes and should follow all program-  
ming operations. Execution of a READ instruction is independent  
of both the WEN and WDS instructions.  
The DO pin indicates the READY/BUSY status of the chip if CS is  
broughthighafteraminimumtimeoftCS. DO=logical0indicates  
that the register, at the address specified in the instruction, has  
been erased, and the part is ready for another instruction.  
Note: The Fairchild CMOS EEPROMs do not require an "ERASE" or "ERASE ALL"  
operationpriortothe"WRITE"and"WRITEALL"instructions. The"ERASE"and"ERASE  
ALL"instructionsareincludedtomaintaincompatibilitywithearliertechnologyEEPROMs.  
Instruction Set for the FM93C56  
Instruction  
READ  
SB  
1
Op. Code  
Address  
A7-A0  
Data  
Comments  
Reads data stored in memory, at specified address.  
Write enable must precede all programming modes.  
Erase selected register.  
10  
00  
11  
01  
00  
00  
00  
WEN  
1
11xxxxxx  
A7-A0  
ERASE  
WRITE  
ERAL  
1
1
A7-A0  
D15-D0  
D15-D0  
Writes selected register.  
1
10xxxxxx  
01xxxxxx  
00xxxxxx  
Erases all registers.  
WRALL  
WDS  
1
Writes all registers.  
1
Disables all programming instructions.  
Note:  
Note:  
A7 is "don't care" bit, but must be included in the address string.  
x = Don't care.  
5
www.fairchildsemi.com  
FM93C56  
Timing Diagrams  
Synchronous Data Timing  
V
IH  
CS  
V
t
IL  
CSS  
t
t
t
CSH  
SKH  
SKL  
t
SKS  
V
IH  
SK  
V
IL  
t
t
DIH  
DIS  
V
IH  
DI  
V
IL  
t
t
DF  
t
PD  
DH  
V
OH  
DO (READ)  
V
OL  
t
SV  
t
t
DF  
DH  
V
OH  
DO (PROGRAM)  
STATUS VALID  
V
OL  
DS800026-4  
READ  
CS  
SK  
DI  
t
CS  
. . .  
1
1
0
A7  
A0  
. . .  
DO  
0
D15  
D0  
DS800026-5  
WEN  
CS  
SK  
DI  
t
CS  
. . .  
1
0
0
1
1
X
X
DS800026-6  
WDS  
CS  
SK  
DI  
tCS  
. . .  
1
0
0
0
0
X
X
DS800026-7  
6
www.fairchildsemi.com  
FM93C56  
Timing Diagrams (Continued)  
WRITE  
CS  
SK  
t
CS  
. . .  
1
0
1
A7  
A0  
D15  
D0  
DI  
DO  
BUSY  
READY  
t
WP  
DS800026-8  
WRALL  
CS  
SK  
DI  
t
CS  
. . .  
1
0
0
0
1
DON'T CARE (6 BITS) D15  
D0  
DO  
BUSY  
READY  
t
WP  
DS800026-9  
ERASE  
t
CS  
CS  
SK  
STANDBY  
. . .  
DI  
1
1
1
A7  
A6  
A5  
A0  
HI-Z  
HI-Z  
DO  
BUSY  
READY  
t
WP  
DS800026-10  
ERAL  
t
CS  
CS  
STANDBY  
SK  
DI  
1
0
0
1
0
DON'T CARE BITS (6 BITS)  
HI-Z  
HI-Z  
DO  
BUSY  
READY  
t
WP  
DS800026-11  
7
www.fairchildsemi.com  
FM93C56  
Physical Dimensions inches (millimeters) unless otherwise noted  
0.189 - 0.197  
(4.800 - 5.004)  
8
7
6
5
0.228 - 0.244  
(5.791 - 6.198)  
1
2
3
4
Lead #1  
IDENT  
0.150 - 0.157  
(3.810 - 3.988)  
0.053 - 0.069  
(1.346 - 1.753)  
0.010 - 0.020  
(0.254 - 0.508)  
0.004 - 0.010  
(0.102 - 0.254)  
x 45°  
8° Max, Typ.  
All leads  
Seating  
Plane  
0.04  
0.0075 - 0.0098  
(0.190 - 0.249)  
Typ. All Leads  
(0.102)  
All lead tips  
0.014  
(0.356)  
0.016 - 0.050  
(0.406 - 1.270)  
Typ. All Leads  
0.050  
(1.270)  
Typ  
0.014 - 0.020  
(0.356 - 0.508)  
Typ.  
Molded Small Out-Line Package (M8)  
Package Number M08A  
0.114 - 0.122  
(2.90 - 3.10)  
8
5
(7.72) Typ  
(4.16) Typ  
0.169 - 0.177  
(4.30 - 4.50)  
0.246 - 0.256  
(6.25 - 6.5)  
(1.78) Typ  
(0.42) Typ  
0.123 - 0.128  
(3.13 - 3.30)  
(0.65) Typ  
Land pattern recommendation  
1
4
Pin #1 IDENT  
0.0433  
Max  
(1.1)  
0.0035 - 0.0079  
See detail A  
0.002 - 0.006  
(0.05 - 0.15)  
0.0256 (0.65)  
Typ.  
Gage  
plane  
0.0075 - 0.0098  
(0.19 - 0.30)  
0°-8°  
DETAIL A  
Typ. Scale: 40X  
0.0075 - 0.0098  
(0.19 - 0.25)  
0.020 - 0.028  
(0.50 - 0.70)  
Seating  
plane  
8-Pin Molded TSSOP, JEDEC (MT8)  
Package Number MTC08  
8
www.fairchildsemi.com  
FM93C56  
Physical Dimensions inches (millimeters) unless otherwise noted  
0.373 - 0.400  
(9.474 - 10.16)  
0.090  
(2.286)  
8
7
0.032 0.005  
(0.813 0.127)  
RAD  
8
7
6
5
4
0.092  
(2.337)  
DIA  
0.250 - 0.005  
(6.35 0.127)  
Pin #1  
IDENT  
+
Pin #1 IDENT  
1
Option 1  
1
2
3
Option 2  
0.280  
MIN  
0.040  
(1.016)  
Typ.  
(7.112)  
0.030  
0.145 - 0.200  
(3.683 - 5.080)  
0.039  
(0.991)  
MAX  
(0.762)  
0.300 - 0.320  
(7.62 - 8.128)  
20° 1°  
0.130 0.005  
(3.302 0.127)  
0.125 - 0.140  
95° 5°  
(3.175 - 3.556)  
0.065  
(1.651)  
0.125  
(3.175)  
DIA  
0.020  
90° 4°  
Typ  
0.009 - 0.015  
(0.229 - 0.381)  
(0.508)  
Min  
0.018 0.003  
(0.457 0.076)  
NOM  
+0.040  
-0.015  
0.325  
0.100 0.010  
+1.016  
-0.381  
8.255  
(2.540 0.254)  
0.045 0.015  
(1.143 0.381)  
0.060  
(1.524)  
0.050  
(1.270)  
Molded Dual-In-Line Package (N)  
Package Number N08E  
Life Support Policy  
Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written  
approval of the President of Fairchild Semiconductor Corporation. As used herein:  
1. Life support devices or systems are devices or systems which,  
(a)areintendedforsurgicalimplantintothebody,or(b)support  
or sustain life, and whose failure to perform, when properly  
used in accordance with instructions for use provided in the  
labeling, can be reasonably expected to result in a significant  
injury to the user.  
2. A critical component is any component of a life support device  
or system whose failure to perform can be reasonably ex-  
pected to cause the failure of the life support device or system,  
or to affect its safety or effectiveness.  
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+33 (0) 1-6930-3696  
+39 (0) 2-249111-1  
2-18-6, Yushima, Bunkyo-ku  
Tokyo, 113-0034 Japan  
Tel: 81-3-3818-8840  
Fax: 81-3-3818-8841  
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.  
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FM93C56  

FM93CS56TLZEMT8 相关器件

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