FMS6246 [FAIRCHILD]
Six Channel, 6th Order SD/PS Video Filter Driver; 六通道，六阶SD / PS视频滤波驱动器
| 型号： | FMS6246 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Six Channel, 6th Order SD/PS Video Filter Driver |
| 文件： | 总10页 (文件大小：93K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
July 2005
FMS6246
Six Channel, 6th Order SD/PS Video Filter Driver
Features
Description
■ Three selectable sixth-order 8/15MHz (SD/PS) filters
■ Three fixed sixth-order 8MHz (SD) filters
■ Transparent input clamping
The FMS6246 Low Cost Video Filter (LCVF) is intended to
replace passive LC filters and drivers with a low-cost integrated
device. Six 6th order Butterworth filters provide improved image
quality compared to typical passive solutions. The combination
of low power Standard Definition (SD) and Progressive Scan
(PS) filters greatly simplify DVD video output circuitry. Three
channels offer fixed SD filters while the other three are select-
able between SD and PS filters.
■ Single video load drive (2Vpp, 150Ω, AV = 6dB)
■ AC or DC-coupled inputs
■ AC or DC-coupled outputs
■ DC-coupled outputs eliminate AC-coupling capacitors
■ Low Power
The FMS6246 offers a fixed gain of 6dB. A metal option is avail-
able that provides a fixed gain of 9dB, offering even more flexi-
bility.
■ 5V only
■ Robust (12kV HBM) output ESD protection
■ Lead (Pb) Free packages- TSSOP-20
The FMS6246 may be directly driven by a DC-coupled DAC out-
put or an AC-coupled signal. Internal diode clamps and bias cir-
cuitry may be used if AC-coupled inputs are required (see
applications section for details).
Applications
■ Cable and Satellite set top boxes
The outputs can drive AC or DC-coupled single (150Ω) video
loads. DC-coupling the outputs removes the need for output
coupling capacitors. The input DC levels will be offset approxi-
mately +280mV at the output.
■ DVD players
■ HDTV
■ Personal Video Recorders (PVR)
■ Video On Demand (VOD)
Block Diagram
Transparent Clamp
6dB
SD IN1
SD IN2
SD IN3
SD OUT1
Transparent Clamp
Transparent Clamp
6dB
SD OUT2
6dB
SD OUT3
th
8MHz, 6 order
Transparent Clamp
Transparent Clamp
Transparent Clamp
6dB
SD/PS IN1
SD/PS IN2
SD/PS OUT1
6dB
SD/PS OUT2
6dB
SD/PS IN3
F
SD/PS OUT3
Selectable
8/15 MHz
th
SD / PS
cSEL
6
order
©2004 Fairchild Semiconductor Corporation
1
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FMS6246 Rev. 1A
Pin Assignments
Pin Configuration
Pin#
Pin
SD IN1
SD IN2
SD IN3
N/C
Type
Input
Input
Input
Input
Input
Input
Description
1
2
3
4
5
6
SD video input, channel 1
SD video input, channel 2
SD video input, channel 3
No Connect
Vcc
+5V supply
SD IN1
SD IN2
SD IN3
N/C
SD OUT1
SD OUT2
SD OUT3
Gnd
1
2
20
19
18
17
16
15
14
13
12
11
FcSEL
Selects filter corner frequency for pins 7, 8,
and 9. “0” = SD, “1” = HD
7
SD/PS IN1
SD/PS IN2
SD/PS IN3
N/C
Input
Input
Input
Input
Input
Selectable SD or PS video input, channel 1
Selectable SD or PS video input, channel 2
Selectable SD or PS video input, channel 3
No Connect
3
8
9
4
FAIRCHILD
FMS6246
10
11
12
13
14
15
16
17
18
19
20
Vcc
Gnd
5
N/C
No Connect
N/C
6
FcSEL
SD/PS OUT3 Output Filtered SD or PS video output, channel 3
SD/PS OUT2 Output Filtered SD or PS video output, channel 2
SD/PS OUT1 Output Filtered SD or PS video output, channel 1
20L TSSOP
SD/PS IN1
SD/PS OUT1
SD/PS OUT2
SD/PS OUT3
N/C
7
SD/PS IN2
SD/PS IN3
N/C
8
N/C
Gnd
Input
Input
Input
No Connect
Must be tied to Ground
Must be tied to Ground
9
Gnd
10
SD OUT3
SD OUT2
SD OUT1
Output Filtered SD video output, channel 3
Output Filtered SD video output, channel 2
Output Filtered SD video output, channel 1
2
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FMS6246 Rev. 1A
Absolute Maximum Ratings
Parameter
DC Supply Voltage
Min.
-0.3
Max.
6
Unit
V
Analog and Digital I/O
-0.3
Vcc + 0.3
50
V
Output Current, Any One Channel (Do Not Exceed)
mA
Reliability Information
Parameter
Junction Temperature
Min.
Typ.
Max.
150
Unit
°C
°C
Storage Temperature Range
-65
150
Lead Temperature (Soldering, 10s)
300
°C
Thermal Resistance (ThetaJA), JEDEC Standard Multi-Layer Test
Boards, Still Air
74
°C/W
Recommended Operating Conditions
Parameter
Operating Temperature Range
Supply Voltage Range
Min.
0
Typ.
Max.
70
Unit
°C
4.75
5.0
5.25
V
Factory Programming Options
Part Name
Part Number
Gain Option
FMS6246
FMS6246MTC20
FMS6246MTC209
6dB
9dB
FMS6246-9
3
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FMS6246 Rev. 1A
DC Electrical Characteristics
T = 25°C, V = 5V, R = 37.5Ω, inputs AC coupled with 0.1uF, all outputs AC coupled with 220uF into
c
cc
source
150Ω loads, referenced to 400kHz; unless otherwise noted.
Symbol
Parameter
Supply Current1
Conditions
Min.
Typ.
60
Max
Units
mA
Vpp
V
ICC
Vin
Vil
no load
80
Video Input Voltage Range
Digital Input Low1
Digital Input High1
Referenced to GND, if DC-coupled
1.4
FcSEL
FcSEL
0
0.8
Vih
2.4
V
V
cc
Standard Definition Electrical Characteristics
T = 25°C, V = 1V , V = 5V, R = 37.5Ω, all inputs AC coupled with 0.1uF, all outputs AC coupled
c
in
pp cc
source
with 220uF into 150Ω loads, referenced to 400kHz; unless otherwise noted.
Symbol
AVSD
f1dBSD
fcSD
Parameter
Channel Gain1
-1dB Bandwidth1
-3dB Bandwidth1
Attenuation(stopband reject)1 All SD Channels at f = 27MHz
Conditions
Min.
5.6
Typ.
6.0
7.15
8.0
50
Max
Units
dB
All SD Channels
6.4
All SD Channels
All SD Channels
5.2
MHz
MHz
dB
6.5
fSBSD
DG
43
Differential Gain
All SD Channels
0.7
1.0
0.35
-54
72
%
DP
Differential Phase
Output Distortion
Crosstalk (ch-to-ch)
Signal-to-Noise Ratio2
Propagation Delay
All SD Channels
°
THD
VOUT = 1.4Vpp, 3.58MHz
at 1MHz
%
XTALKSD
SNR
dB
NTC-7 weighting, 100kHz to 4.2MHz
Delay from input to output, 4.5MHz
dB
tpdSD
90
ns
Progressive Scan Electrical Characteristics
T = 25°C, V = 1V , V = 5V, R = 37.5Ω, all inputs AC coupled with 0.1uF, all outputs AC coupled
c
in
pp cc
source
with 220uF into 150Ω loads, referenced to 400kHz; unless otherwise noted.
Symbol
AVPS
Parameter
Channel Gain1
-1dB Bandwidth1
-3dB Bandwidth1
Attenuation(stopband reject)1 All PS Channels at f = 54MHz
Conditions
Min.
5.6
12
Typ.
6.0
14
Max
Units
dB
All PS Channels
6.4
f1dBSPS
fcPS
All PS Channels
All PS Channels
MHz
MHz
dB
13
16
fSBPS
37
45
THD
Output Distortion (All PS
channels)
VOUT = 1.4Vpp, 7MHz
0.35
%
XTALKPS
SNR
Crosstalk (ch-to-ch)
Signal-to-Noise Ratio2
Propagation Delay
at 1MHz
-53
66
47
dB
dB
ns
unweighted; 100kHz to 15MHz
Delay from input to output
tpdPS
Notes:
1. 100% tested at 25°C
2. SNR = 20 * log (714mV / rms noise)
4
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FMS6246 Rev. 1A
coupling capacitor. A conceptual illustration of the input clamp
circuit is shown below:
Applications Information
Functional Description
The FMS6246 Low Cost Video Filter (LCVF) provides 6dB gain
(9dB optional, contact factory for further information) from input
to output. In addition, the input will be slightly offset to optimize
the output driver performance. The offset is held to the minimum
required value to decrease the standing DC current into the
load. Typical voltage levels are shown in the diagram below.
0.65V
Y
OUT
Y
Driver
IN
800kΩ
1.0 -> 1.02V
0.65 -> 0.67V
0.3 -> 0.32V
Figure 2. Input Clamp Circuit
I/O Configurations
0.0 -> 0.02V
Vin
For DC-coupled DAC drive with DC-coupled outputs, use this
configuration:
Driven by:
2.28V
1.58V
DC-Coupled DAC Outputs or
AC-Coupled and Clamped
Y, R, G, B, CV
0V - 1.4V
75
DVD or
STB
SoC
LCVF
Clamp
Inactive
0.88V
0.28V
Vout
DAC
Output
There will be a 280mV offset from the DC input level to
the DC output level.
Vout = 2 * Vin + 280mV
0.85V
0.5V
Figure 3. DC-coupled Inputs and Outputs
Alternatively, if the DAC’s average DC output level causes the
signal to exceed the range of 0V to 1.4V, it can be AC-coupled
as follows:
0.15V
Vin
0V - 1.4V
1.98V
0.1u
75
Driven by:
DC-Coupled DAC Outputs
AC-Coupled and Biased
U, V, Pb, Pr, C
DVD or
STB
SoC
DAC
Output
LCVF
Clamp
Active
1.28V
0.58V
Vout
Figure 1. Typical Voltage Levels
The FMS6246 provides an internal diode clamp to support AC-
coupled input signals. If the input signal does not go below
ground, the input clamp will not operate. This allows DAC out-
puts to directly drive the FMS6246 without an AC coupling
capacitor. The worst-case sync tip compression due to the
clamp will not exceed 7mV. The input level set by the clamp
combined with the internal DC offset will keep the output within
its acceptable range. When the input is AC-coupled, the diode
clamp will set the sync tip (or lowest voltage) just below ground.
Figure 4. AC-coupled Inputs, DC-coupled Outputs
When the FMS6246 is driven by an unknown external source or
a SCART switch with its own clamping circuitry the inputs
should be AC-coupled as follows:
0V - 1.4V
For symmetric signals like C, U, V, Cb, Cr, Pb and Pr, the aver-
age DC bias is fairly constant and the inputs can be AC-coupled
with the addition of a pull-up resistor to set the DC input voltage.
DAC outputs can also drive these same signals without the AC
0.1u
75
LCVF
Clamp
Active
External Video
source must
be AC-coupled.
75
Figure 5. SCART Configuration with DC-coupled
Outputs
5
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FMS6246 Rev. 1A
The same method can be used for biased signals with the addi-
tion of a pull-up resistor to make sure the clamp never operates.
The internal pull-down resistance is 800kΩ 20% so the exter-
nal resistance should be 7.5MΩ to set the DC level to 500mV. If
a pull-up resistance less than 7.5MΩ is desired, an external
pull-down can be added such that the DC input level is set to
500mV.
Power Dissipation
The FMS6246 output drive configuration must be considered
when calculating overall power dissipation. Care must be taken
not to exceed the maximum die junction temperature. The fol-
lowing example can be used to calculate the FMS6246’s power
dissipation and internal temperature rise.
Tj = TA + Pd • ΘJA
where Pd = PCH1 + PCH2 + PCHx
and PCHx = Vs • ICH - (VO2/RL)
where
External Video
source must
be AC-coupled.
0.1u
75
LCVF
Bias
Input
7.5M
VO = 2Vin + 0.280V
ICH = (ICC / 6) + (VO/RL)
Vin = RMS value of input signal
ICC = 60mA
500mV +/-350mV
75
Figure 6. Biased SCART with DC-coupled Outputs
Vs = 5V
The same circuits can be used with AC-coupled outputs if
desired.
RL = channel load resistance
Board layout can also affect thermal characteristics. Refer to the
Layout Considerations Section for more information.
0V - 1.4V
75
220u
DVD or
STB
SoC
LCVF
Clamp
Inactive
Layout Considerations
General layout and supply bypassing play major roles in high
frequency performance and thermal characteristics. Fairchild
offers a demonstration board, FMS6246DEMO, to use as a
guide for layout and to aid in device testing and characterization.
The FMS6246DEMO is a 4-layer board with a full power and
ground plane. Following this layout configuration will provide the
optimum performance and thermal characteristics. For optimum
results, follow the steps below as a basis for high frequency lay-
out:
DAC
Output
Figure 7. DC-coupled inputs, AC-coupled Outputs
0V - 1.4V
•
•
•
•
Include 10µF and 0.1µF ceramic bypass capacitors
0.1u
75
220u
DVD or
STB
SoC
DAC
Output
LCVF
Clamp
Active
Place the 10µF capacitor within 0.75 inches of the power pin
Place the 0.1µF capacitor within 0.1 inches of the power pin
For multi-layer boards, use a large ground plane to help dissi-
pate heat
•
•
For 2 layer boards, use a ground plane that extends beyond
the device by at least 0.5”
Figure 8. AC-coupled inputs and outputs
Minimize all trace lengths to reduce series inductances
External video
source must
be AC-coupled.
0.1u
75
220u
LCVF
Clamp
Active
7.5M
500mV +/-350mV
75
Figure 9. Biased SCART with AC-Coupled Outputs
NOTE: The video tilt or line time distortion will be dominated by
the AC-coupling capacitor. The value may need to be increased
beyond 220uF in order to obtain satisfactory operation in some
applications.
6
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FMS6246 Rev. 1A
Typical Application Diagram
The following circuit may be used for direct DC-coupled drive by DACs with an output voltage range of 0V to 1.4V. AC-coupled or DC-
coupled outputs may be used with AC-coupled outputs offering slightly lower power dissipation.
+5V
DVD Player or STB
0.1
uF
10
uF
75Ω
75Ω
75Ω
220uF
220uF
220uF
75Ω Video Cables
Y1
C
1
2
20
Y1
OUT
SD IN1
SD IN2
SD IN3
Vcc
SD OUT1
SD OUT2
SD OUT3
75Ω
75Ω
75Ω
19
C
OUT
CV
3
5
7
8
9
18
CV
OUT
16,17
14
FAIRCHILD
FMS6246
Video
SoC
GND
SD/PS OUT1
SD/PS OUT2
20L TSSOP
75Ω
75Ω
75Ω
220uF
220uF
220uF
75Ω Video Cables
Y2/G
Pb/B
Pr/R
G/Y2
SD/PS IN1
SD/PS IN2
SD/PS IN3
OUT
OUT
75Ω
75Ω
75Ω
13
B/Pb
12
R/Pr
OUT
SD/PS OUT3
cSEL
F
6
AC-Coupling Caps
are Optional.
DAC Load Resistors
Figure 10. Typical application diagram
7
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FMS6246 Rev. 1A
Mechanical Dimensions
20-Lead Thin Shrink Outline Package (TSSOP)
7
6
– B –
e
N
5
(b)
2X E/2
TSSOP-20
8
SYMBOL
A
MIN
NOM
MAX
1.10
0.15
0.95
0.75
–
1.0 DIA
E1 E
c
c1
–
–
–
0.90
0.60
–
–
–
0.22
–
–
A1
A2
L
R
R1
b
0.05
0.85
0.50
0.09
0.09
0.19
0.19
0.09
0.09
0°
1.0
b1
1
2
3
ddd C B A
SECTION AA
2X
6
e /2
9
N/2 TIPS
1.0
–
0.30
0.25
0.20
0.16
8°
b1
c
ccc
D
c1
01
L1
aaa
bbb
ccc
ddd
e
A2
A
8
3
7
– A –
–
aaa C
1.0 REF
0.10
0.10
0.05
0.20
0.65 BSC
12° REF
12° REF
6.50
4.40
6.4 BSC
0.65 BSC
20
– C –
b
NX
A1
(02)
(0.20)
M
bbb C B A
R1
02
03
D
– H –
R
GAGE
PLANE
6.50
4.30
6.60
4.50
E1
E
e
10
(03)
A
A
0.25
01
L
N
(L1)
NOTES:
1
2
3
4
5
All dimensions are in millimeters (angle in degrees).
Dimensioning and tolerancing per ASME Y14.5–1994.
Dimensions "D" does not include mold flash, protusions or gate burrs. Mold flash protusions or gate burrs shall not exceed 0.15 per side .
Dimension "E1" does not include interlead flash or protusion. Interlead flash or protusion shall not exceed 0.25 per side.
Dimension "b" does not include dambar protusion. Allowable dambar protusion shall be 0.08mm total in excess of the "b" dimension at maximum
material condition. Dambar connot be located on the lower radius of the foot. Minimum space between protusion and adjacent lead is 0.07mm
for 0.5mm pitch packages.
6
7
8
9
Terminal numbers are shown for reference only.
Datums – A – and – B – to be determined at datum plane – H – .
Dimensions "D" and "E1" to be determined at datum plane – H – .
This dimensions applies only to variations with an even number of leads per side. For variation with an odd number of leads per side, the "center"
lead must be coincident with the package centerline, Datum A.
10 Cross sections A – A to be determined at 0.10 to 0.25mm from the leadtip.
8
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FMS6246 Rev. 1A
Ordering Information
Gain
Pack
Qty
Model
Part Number
Option Lead Free Package Container
FMS6246 FMS6246MTC20
FMS6246 FMS6246MTC20X
6dB
6dB
Yes
Yes
TSSOP-20
TSSOP-20
Rail
94
Reel
2500
Temperature range for all parts: 0°C to 70°C.
Contact Fairchild for additional gain options. Refer to Factory Programming Options Table for more information.
9
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FMS6246 Rev. 1A
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
ACEx™
POP™
Power247™
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FAST
FASTr™
FPS™
FRFET™
GlobalOptoisolator™
GTO™
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ActiveArray™
Bottomless™
CoolFET™
CROSSVOLT™
DOME™
EcoSPARK™
E2CMOSTM
EnSignaTM
FACT™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
®
PowerTrench
®
QFET
QS™
SyncFET™
®
QT Optoelectronics™ TinyLogic
Quiet Series™
RapidConfigure™
RapidConnect™
TINYOPTO™
TruTranslation™
MSXPro™
OCX™
HiSeC™
I2C™
UHC™
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Across the board. Around the world.™
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FAIRCHILD SEMICONDUCTOR RESERVESTHE RIGHTTO MAKE CHANGES WITHOUTFURTHER NOTICETOANY
PRODUCTS HEREINTO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOTASSUMEANYLIABILITY
ARISING OUTOFTHEAPPLICATION OR USE OFANYPRODUCTOR CIRCUITDESCRIBED HEREIN; NEITHER DOES IT
CONVEYANYLICENSE UNDER ITS PATENTRIGHTS, NORTHE RIGHTS OF OTHERS.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUTTHE EXPRESS WRITTENAPPROVALOF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or
In Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Obsolete
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. I7
10
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FMS6246 Rev. 1A
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