FMS7401LEN14 [FAIRCHILD]
Digital Power Controller; 数字电源控制器
| 型号： | FMS7401LEN14 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Digital Power Controller |
| 文件： | 总80页 (文件大小：1461K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
www.fairchildsemi.com
FMS7401/7401L
Digital Power Controller
• 5-Ch 8-bit Analog-to-Digital Converter
General Description
– 20 µS conversion time
The FMS7401/7401L is a family of Digital Power Control-
lers designed for applications requiring ease of digital based
control over analog based implementations. The FMS7401/
7401L family is an ideal solution to implement ballast
control, motor control and battery management functions.
This family integrates a wide variety of analog blocks with
an 8-bit microcontroller core to offer a complementary
feature set with high performance, low power and small
size in a single chip.
– Sample and Hold
– Internal Voltage Reference (1.21V)
– Gated Auto-sampling Mode
• Auto-zero Amplifier (gain 16)
• Uncommitted Amplifier
• Internal Current Source Generator (1mA)
• On-chip Oscillator
– No external components
– 1µs instruction cycle time
• On-chip Power-on Reset
• Programmable read and write disable functions
• Memory Mapped I/O
• Programmable Comparator (63 Levels)
• Brown-out Reset
• Software selectable I/O option
• Push-pull outputs with tri-state option
• Weak pull-up or high impedance inputs
• Fully static CMOS
The FMS7401/7401L family is fabricated using CMOS
technology and is fully static. This offers significant power
savings. This family is available in both 8-pin and 14-pin
PDIP packages. SOIC and TSSOP packages are available
upon request.
The FMS7401L is intended for applications using a supply
voltage in the 2.7V to 3.6V range, while the FMS7401 is
suited for applications that use a supply voltage in the 10V to
13.5V range.
– Power Saving Halt Mode
– FMS7401L (< 1.3µA @ 3.3V)
– Power Saving Idle Mode
– FMS7401L (< 180µA @ 3.3V)
• Single supply operation
– 10V – 13.5V (FMS7401)*
– 2.7V – 3.6V (FMS7401L)
• 40 years data retention
• 100,000 data changes
• 8-/14-pin PDIP, SOIC, and TSSOP packages
• In-circuit programming
Features
• 8-bit Microcontroller Core
• 1K bytes on-board code EEPROM
• 64 bytes data EEPROM
• 64 bytes SRAM
• Watchdog Reset
• Multi-input Wakeup on all general purpose I/O pins
• Fast 12-bit PWM timer with dead time control and half-
bridge output drive
– Fast Page-write Programming Mode
– Input Capture Mode
Data Memory (bytes)
Program
Device
Supply Voltage
2.7V – 3.6V
2.7V – 3.6V
10V – 13.5V
Memory (bytes)
SRAM
64
Data EEPROM
I/O
6
Pin Count
FMS7401L
FMS7401L
FMS7401*
1K
1K
1K
64
64
64
8
64
8
14
14
64
8
* Contact your local Fairchild Sales Representative for FMS7401 availability.
REV. 1.0.2 6/23/04
FMS7401/7401L
Block Diagram
Vcc
Vdd
GND RESET
FMS7401
only
G7/AIN4/
AOUT
3.3V
Regulator
Uncommitted
Amplifier
_
G6/-AIN
AOUT
Vcc
+
VREF
Analog
Mux
ACH5
ACH2
Power-on Reset
and Brown-out Reset
Internal
Oscillator
G3/AIN1
G2/AIN2
8-bit
ADC
ACH3
Y
S/H
Timer 0
and Watchdog
G0/T1HS1
G5/T1HS2
G1/AIN3/
ADSTROBE
ACH4
ACH1
PWM
TIMER 1
and
Dead Time
Control
8-bit
64bytes
Data EEPROM
Memory
Autozero
Amplifier
Microcontroller
Core
_
+
SR_GND
G4/AIN0
x16
64 bytes
SRAM
Unit Gain
Programmable
Comparator
1024 bytes
Code EEPROM
Memory
I/O
PORTS
+
_
AGND
AOUT
Digital
Filter
Progr.
Reference
Figure 1. FMS7401/7401L Block and Connection Diagram
Pin Configurations
G4/AIN0
GND
1
2
3
4
8
1
2
3
4
8
VCC
G5/T1HS2
VCC
G0/T1HS1
G3/AIN1
G1/AIN3
G2/AIN2
G5/T1HS2
G0/T1HS1
G3/AIN1
7
6
5
7
6
5
G2/AIN2
G1/AIN3
G4/AIN0
GND
FMS7401L 8-Pin PDIP/SOIC
FMS7401L 8-Pin TSSOP
1
2
3
4
5
6
7
14
13
12
11
10
9
G4/AIN0
VCC
VDD
SR_GND
GND
G5/T1HS2
RESET
G6/-AIN
G7/AOUT
G2/AIN2
G1/AIN3
G0/T1HS1
G3/AIN1
AGND
8
FMS7401/7401L 14-Pin PDIP/SOIC/TSSOP
2
REV. 1.0.2 6/23/04
PRODUCT SPECIFICATION
FMS7401/7401L
FMS7401/7401L Pin Definitions
Pin Number
8-Pin
14-Pin
PDIP
SOIC
TSSOP
PDIP
SOIC
TSSOP
Pin Name
Pin Function Description
General purpose I/O port (bit 4 of the I/O configuration registers).
AIN0 analog input of the ADC (autozero amplifier’s positive terminal).
Programmable Comparator non-inverting input, if COMPSEL=0.
Digital ground pin.
1
3
1
G4/AIN0
2
3
4
5
3
6
GND
G2/AIN2
General purpose I/O port (bit 2 of the I/O configuration registers).
AIN2 analog input of the ADC.
Programmable Comparator non-inverting input, if COMPSEL=1.
General purpose I/O port (bit 1 of the I/O configuration registers).
AIN3 analog input of the ADC.
4
5
6
7
7
9
G1/AIN3/
ADSTROBE
External digital clock input.
PWM Timer 1’s ADSTROBE output.
G3/AIN1
General purpose I/O port (bit 3 of the I/O configuration registers).
AIN1 analog input of the ADC.
Internal current source generator pin.
6
7
8
1
10
12
G0/
T1HS1
General purpose I/O port (bit 0 of the I/O configuration registers).
PWM Timer 1’s T1HS1 output.
G5/
T1HS2
General purpose I/O port (bit 5 of the I/O configuration registers).
PWM Timer 1’s T1HS2 output.
8
–
2
–
14
2
VCC
Supply voltage input for the FMS7401L. In the FMS7401, Vcc is the regulated output.
SR_GND
AIN0 analog input of the ADC (autozero amplifier’s negative terminal). SR_GND is
internally connected to GND in the 8-pin FMS7401L.
–
–
–
–
4
5
G6/-AIN
General purpose I/O port (bit 6 of the I/O configuration registers).
Uncommitted amplifier negative analog input.
General purpose I/O port (bit 7 of the I/O configuration registers).
AIN4 analog input of the ADC.
G7/AIN4/
AOUT
Uncommitted amplifier analog output.
–
–
8
AGND
Analog ground for the FMS7401. In the FMS7401L, AGND is internally connected to
GND. Externally, AGND should be left unconnected or connected to GND.
–
–
–
–
11
13
RESET
VDD
Active low external reset input.
High voltage supply input for the FMS7401. In the FMS7401L, VCC is internally
connected to VDD. Externally, VDD should either be left unconnected or connected to
VCC.
REV. 1.0.2 6/23/04
3
FMS7401/7401L
PRODUCT SPECIFICATION
Table of Contents
FMS7401/7401L. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
FMS7401/7401L Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1 Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.1 FMS7401L Power-on Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.2 FMS7401L External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.3 FMS7401L Brown-out Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2 Clock Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3 Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1 Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1.1 PLL Steps for Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2 Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2.1 PLL Steps for Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4 ADC Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1 ADC Circuit Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1.1 ADCNTRL1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1.2 ADCNTRL2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.2 ADC Conversion Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.2.1 Analog Input Voltage and its 8-bit Digital Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.2.2 ADC Gated Auto-sampling Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.2.3 ADC Conversion Clock Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.3 Autozero Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.4 Uncommitted Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.5 Current Source Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5 Programmable Comparator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.1 Programmable Comparator’s Voltage Threshold Levels (VLOOP=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.2 Hardware Voltage and Current Loop Control (VLOOP=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.3 Digital Delay Filter with PWMOFF Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6 PWM Timer 1 Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.1 PWM Timer 1 Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.1.1 PSCALE Register and Timer 1 Clock Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.1.2 PWM Cycle Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.1.3 Timer 1 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.2 Pulse Width Modulation (PWM) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.3 Input Capture Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7 Timer 0 Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7.1 Idle Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7.2 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8 I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.1 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9 Multi-input Wakeup Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
9.1 MIW Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
4
REV. 1.0.2 6/23/04
PRODUCT SPECIFICATION
FMS7401/7401L
10 8-Bit Microcontroller Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
10.1 Core Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
10.1.1 Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
10.1.2 X-Pointer (X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
10.1.3 Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
10.1.4 Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
10.1.5 Status Register (SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
10.1.6 Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
10.2 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
11 Device Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
11.1 Initialization Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
11.2 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
12 In-circuit Programming Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
12.1 Programming Mode Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
12.2 Programming Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
12.2.1 Byte Write Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
12.2.2 Page Write Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
12.2.3 Byte Read Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
12.2.4 Program Memory Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
13 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
13.1 FMS7401L (2.7V to 3.6V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
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5
FMS7401/7401L
PRODUCT SPECIFICATION
List of Figures
Figure 1. FMS7401/7401L Block and Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
Figure 2. BOR and POR Circuit Relationship Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Figure 3. Internal Clock Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Figure 4. External Clock Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Figure 5. Recommended Halt/Idle Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Figure 6. ADC Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Figure 7. Current Generator Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Figure 8. Programmable Comparator Block Diagram (VLOOP = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Figure 9. Programmable Comparator Block Diagram (VLOOP = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Figure 10. Digital Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Figure 11. Timer 1’s PWM Mode Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Figure 12. Example PWM Output Signals a) and b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Figure 13. Timer 1’s Input Capture Mode Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Figure 14. PORTGD Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Figure 15. Output Port Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Figure 16. Multi-input Wakeup (MIW) Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Figure 17. Core Program Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Figure 18. Basic Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Figure 19. Programming Mode Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Figure 20. Programming Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Figure 21. Serial Data Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Figure 22. Page Mode Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Figure 23. Internal Oscillator Frequency (FOSC) vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Figure 24. Icc Active vs. Temperature (no PLL or data EEPROM writes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Figure 25. Icc Active vs. Temperature (no PLL, with data EEPROM writes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Figure 26. Icc Active vs. Temperature (with PLL, no data EEPROM writes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Figure 27. Halt Current vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Figure 28. Idle Current vs. Temperature (no PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Figure 29. Idle Current vs. Temperature (with PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Figure 30. VOL vs. IOL @ 25°C (G1–G4, G6, G7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Figure 31. VOL vs. IOL @ 25°C (G0, G5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Figure 32. VOH vs. IOH @ 25°C (G1–G4, G6, G7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Figure 33. VOH vs. IOH @ 25°C (G0, G5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Figure 34. BOR Level vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Figure 35. Programmable Comparator Voltage Level vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Figure 36. VREF vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Figure 37. Current Source (ISRC) vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
Figure 38. Gain 16 Error vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
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PRODUCT SPECIFICATION
FMS7401/7401L
List of Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Default Register States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
CMODE Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
PLL Frequency Selection (FPLL/FOSC = 2MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
HALT Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
ADCNTRL1 Register Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Analog Input Channel Selection (ACHSEL[3:0]) Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
ADCNTRL2 Register Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Programmable Comparator (COMP) Control Register Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Programmable Comparator Lower Voltage Reference VTHL (Levels 1 – 31) . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Table 10. Programmable Comparator Upper Voltage Reference VTHU (Levels 32 – 63) . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Table 11. Digital Delay (DDELAY) Register Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Table 12. Prescale (PSCALE) Register Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Table 13. PLL Divide Factor Selection Bits and the FT1CLK Resolution (FOSC=2 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Table 14. Timer 1 Prescale Selection (PS) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Table 15. Dead Time (DTIME) Register Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Table 16. Timer 1 Control (T1CNTRL) Register Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Table 17. Timer 1 Mode Configuration Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Table 18. Timer 0 Control (T0CNTRL) Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Table 19. Watchdog Service Register (WDSVR) Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Table 20. I/O Register Bit Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Table 21. I/O Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Table 22. Multi-input Wakeup (MIW) Register Bit Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Table 23. Interrupt Priority Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Table 24. Instruction Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Table 25. Instruction Cycles and Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Table 26. Initialization Register 1 Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Table 27. Initialization Register 3 Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Table 28. Initialization Register 4 Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Table 29. T1HS1 (G0) and T1HS2 (G5) Default Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Table 30. Memory Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Table 31. Memory Mapped Registers and their Register Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Table 32. Programming Interface Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Table 33. 32-Bit Command and Response Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
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7
FMS7401/7401L
PRODUCT SPECIFICATION
1 Reset Circuit
The reset circuit in the FMS7401/7401L contains four input conditions that trigger a main system reset. When the main system
reset is triggered, a sequence of events occur defaulting all memory mapped registers (including the initialization registers) and
I/Os to their initial states (see Table 1). During the system reset sequence, the instruction core execution is halted allowing time
for the internal oscillator and other analog circuits to stabilize. Once the system reset sequence completes, the device will begin
with its normal operation executing the instruction program residing in the code EEPROM memory. The time required for the
system reset sequence to complete (TRESET) is dependent on the individual trigger condition and is defined in the Electrical
Characteristics section of the datasheet. The four reset trigger conditions are as follows:
• Power-on Reset (POR)
• External Reset1
• Brown-out Reset (BOR)
• Watchdog Reset2
Table 1. Default Register States
Peripheral/Register
G1, G2, G3, G4, G6, G7
External Reset
High-impedance input (tri-state input)
Defined by Init Reg. 4 (see Table 28)
No change Unspecified
POR
G0, G5
SRAM Memory
Stack Pointer
0xF
0x80
0xFFF
0x1F
0x00
0xF
0x80
0xFFF
0x1F
0x00
Status Register
T1CMPA, T1CMPB and T1RA Registers
DTIME Register
All other memory mapped register not listed above.3
1.1 FMS7401L Power-on Reset Circuit
The Power-on Reset (POR) circuit maintains the device in a reset state until Vcc reaches a voltage level high enough to guaran-
tee proper device operation. The POR circuit is sensitive to the different Vcc ramp rates and must be within SVcc as specified in
the Electrical Characteristics section of the datasheet.
The POR circuit does not generate a system reset when Vcc is falling. This feature is performed by the Brown-out Reset (BOR)
circuit and must be enabled by the BOREN bit of the Initialization Register 1.4 In the case where Vcc does not drop to 0V
before the next power-up sequence, it is necessary to enable the BOR circuit and/or reset the device externally through the
RESET pin.1
1.2 FMS7401L External Reset1
The device may be externally reset through the RESET input pin if the POR/BOR circuits cannot be used to properly reset the
device in the application. The RESET input pin contains an internal pull-up resistor making it an active low signal. Therefore,
to issue a device system reset the RESET input should be held low for at least 10µS before being released (i.e. returned to a
high state). While the RESET input is held low, the internal oscillator and other analog circuits are kept in a low power state
reducing the current consumption of the device (a state resembling Halt Mode). In addition, the I/O pins are all initialized to an
input tri-state configuration unless defaulted otherwise.5 At the rising edge of the RESET input signal, the main system reset
sequence is triggered releasing the internal oscillator and other analog circuits so that they may be initialized and begin their
normal operation.
1.3 FMS7401L Brown-out Reset Circuit
The Brown-out Reset (BOR) circuit is one of the on-chip analog comparator peripherals and must be enabled through the
BOREN bit of the Initialization Registers 1.4 The BOR circuit is used to hold the device in a reset state when Vcc drops below
a fixed threshold defined in the Electrical Characteristics section of the datasheet. While in reset, the device is held in its initial
condition until Vcc rises above the fixed/power-on threshold. Shortly after Vcc rises above the fixed/power-on threshold, the
internal system reset sequence is started. Once the system reset sequence completes, the device will begin with its normal
operation executing the instruction program residing in the code EEPROM memory.
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REV. 1.0.2 6/23/04
PRODUCT SPECIFICATION
FMS7401/7401L
The BOR circuit should be used in situations when Vcc rises and falls slowly and in situations when Vcc does not fall to 0V
before rising back to the device’s normal operating range. The BOR circuit can be thought of as a supplement function to the
POR circuit if Vcc does not fall below 0.7V.
Figure 2. BOR and POR Circuit Relationship Diagram
1. Available only on the 14-pin package option.
2. Refer to the Timer 0 Circuit section of the datasheet for details regarding the Watchdog Reset.
3. Refer to Table 30 of the Device Memory section of the datasheet for the detailed memory map.
4. Refer to the Device Memory section of the datasheet for details regarding the Initialization Register 1.
5. Refer to Table 28 and Table 29 of the Device Memory section of the datasheet for details.
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9
FMS7401/7401L
PRODUCT SPECIFICATION
2 Clock Circuit
The FMS7401/7401L may be clocked using its internal oscillator circuit or using an external digital clock signal. The desired
clock source is selectable by the CMODE bit of the Initialization Register 1.1 During the reset sequence, the CMODE bit is
updated and the desired clock source (also called the device reference clock or FRCLK1) takes control of the device. All devices
are defaulted from the factory to use the internal oscillator as their main system instruction clock source. After power-up, the
internal oscillator runs continuously unless entering Halt Mode or using an external clock source.
Table 2. CMODE Bit Definition
CMODE
FRCLK1 Clock Source
0
1
Internal Oscillator (@ FOSC)
External digital clock (G1/AIN3)
The internal oscillator signal is factory trimmed to yield the FOSC frequency as specified in the Electrical Characteristics section
of the datasheet. If the external digital clock is selected, the input signal must have a 50/50 duty cycle, can range from DC to
the FOSC, and must be available upon power-up. When the device is driven using an external clock source, the clock input to the
device should be provided through the AIN3/G1 input.
Once the source of FRCLK1 is selected, the clock is then used as the reference clock for the PLL, the clock to the digital filter in
the Programmable Comparator circuit, and is divided-by-2 to be used as the main system instruction clock (FICLK) of the device
(see Figure 3 and Figure 4).
2.1 PLL
The FMS7401/7401L has an internal digital clock multiplier (PLL) that steps-up the FRCLK1 frequency by a multiplication fac-
tor of 32. The multiplied PLL output is then divided by a factor of 1, 2, 4, and 8 in order to generate its programmable output
frequencies that may be used as the main system instruction clock or by the PWM Timer 1 circuit. The PLL provides the ability
to run the PWM Timer 1 circuit at a frequency as high as 64MHz while the rest of the device operates at a much slower fre-
quency keeping the total current consumption low.
The reference clock of the PLL is defined by the FRCLK2 signal (as shown in Figure 3 and Figure 4) and sourced by the FRCLK1
signal. In order to yield the proper output frequencies offered by the PLL, FRCLK2 must operate at the FPLL frequency as speci-
fied in the Electrical Characteristics section of the datasheet. In the case that FRCLK1 is operating at the upper FOSC frequency,2
the REFBY2 bit in the ADCNTRL2 register3 must be set in order to divide the FRCLK1 by 2 to yield the appropriate FPLL fre-
quency of the FRCLK2 signal. Once the REFBY2 bit is set, the FRCLK2 signal that drives the PLL and digital filter in the Pro-
grammable Comparator circuit operates at a FRCLK1/2 frequency. If an external digital clock is sourcing FRCLK1, the input signal
must be supplied at the specified FOSC frequency in order to meet the specified FPLL frequency of the FRCLK2 signal.
Table 3. PLL Frequency Selection (FPLL/FOSC = 2MHz)
FICLK
FICLK
FS[1:0]
FRCLK2
2 MHz
2 MHz
2 MHz
2 MHz
(FMODE = 0)
(FMODE = 1)
FPWMCLK
8 MHz
0
0
1
1
0
1
0
1
1 MHz
1 MHz
1 MHz
1 MHz
8 MHz
8 MHz
8 MHz
8 MHz
16 MHz
32 MHz
64 MHz
The PLL outputs may be used to clock both the PWM Timer 1 circuit and the main system clock. However, the PLL must first
be enabled by setting the PLLEN bit of the PSCALE register.4 Once set, the PLL is turned on and begins the locking phase.
Before using any of the PLL outputs, software must wait the TPLL_LOCK to ensure that the PLL is locked into its appropriate fre-
quency and in phase. The PLLEN bit may not be changed while the PWM Timer 1 circuit is in run mode.5 Any write attempts
to this bit during this condition will not change its value.
The PWM Timer 1 circuit may be clocked either by the PLL’s FPWMCLK output or by the main system clock (FICLK). The FSEL
bit of the PSCALE register4 selects between the PLL’s FPWMCLK output (if FSEL=1) or FICLK (if FSEL=0). The FSEL bit may
not be set if the PLL is not enabled (PLLEN=0) or changed while the PWM Timer 1 circuit is in run mode.5Any write attempts
to this bit during these conditions will not change its value.
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REV. 1.0.2 6/23/04
PRODUCT SPECIFICATION
FMS7401/7401L
The FS[1:0] bits of the PSCALE register4 select the divide factor for the FPWMCLK output (see Table 3). The FS bits may be
changed by software at any time; however, if the PWM Timer 1 circuit is in run mode the FS[1:0] value will not change the
FPWMCLK output frequency until after the PWM cycle ends (once the TMR1 counter overflows). The last FS[1:0] value at the
PWM cycle end time will dictate the divide factor of the FPWMCLK output for the next PWM cycle. When reading the FS[1:0],
the value reported will be the last value written by software (it may not necessarily reflect the divide factor for the current
PWM cycle).
The main system instruction clock (FICLK) source may be provided by the internal oscillator (FOSC) or the PLL’s F(FS=0) output
with the same divide factor as the FS[1:0] = 00 selection.6 The FMODE bit of the PSCALE register4 selects between the F(FS=0)
(if FMODE=1) or FRCLK1 divided-by-2 signal. With the FMODE bit enabled, it is possible to execute instructions at a speed
eight times faster than the standard. The FMODE bit may not be set if the PLL is not enabled.5 Any attempts to write to
FMODE while PLLEN=0 will force FMODE=0 ignoring any set instruction. Once the PLL has been enabled, software may
change FICLK’s source on-the-fly during normal instruction execution in order to speed-up a particular action.
In order to synchronously disable the PLL clocking structure, software must clear FSEL and FMODE before clearing the
PLLEN bit in order to disable the PLL successfully e.g. using separate instructions like “RBIT PLLEN, PSCALE.” There are
also special conditions for Halt/Idle power saving modes that must also be considered. Please refer to the Power Saving Modes
section of the datasheet for details.
Figure 3. Internal Clock Scheme
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FMS7401/7401L
PRODUCT SPECIFICATION
Figure 4. External Clock Scheme
1. Refer to the Device Memory section of the datasheet for details regarding the Initialization Registers 1.
2. The upper FOSC frequency (4MHz) is not a standard feature offered on the FMS7401/7401L devices but is available upon request.
3. The ADCNTRL2 register is defined in the ADC Circuit section of the datasheet.
4. The PSCALE register is defined in the PWM Timer 1 Circuit section of the datasheet.
5. Software must always configure the device’s entire clocking structure (see Figure 3 and Figure 4) while the PWM Timer 1 circuit is off (T1C0=0) and configured in
PWM mode (T1C3=0).
6. The PLL’s F(FS=0) output is not affected by the FS[1:0] bit value of the PSCALE register and merely shares the FS[1:0]=00 divide factor.
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PRODUCT SPECIFICATION
FMS7401/7401L
3 Power Saving Modes
The FMS7401/7401L has both Halt and Idle power saving modes. Each mode is controlled by software and offers the advan-
tage of reducing the total current consumption of the device in an application. For all current consumption details, please refer
to the Electrical Characteristics section of the datasheet. In order to maintain proper Vcc voltage regulation of the FMS7401,
the internal regulator remains enabled—making the current consumption much higher than the FMS7401L for both Halt and
Idle Modes.1
3.1 Halt Mode
Halt Mode is a power saving feature that almost completely shuts down the device for current conservation. The device is
placed into Halt Mode by setting the Halt enable bit (EHALT) of the HALT register using either the “LD M, #” or the “SBIT #,
M” instructions in the software. EHALT is a write only bit and is automatically cleared upon exiting Halt Mode. When enter-
ing Halt Mode, the internal oscillator and all other on-chip systems including the Programmable Comparator (COMP) and
Brown-out Reset (BOR) circuits are shut down. For the FMS7401, to maintain proper Vcc voltage regulation, the internal reg-
ulator circuit remains enabled while in Halt Mode.
The device can exit Halt Mode only by the Multi-input Wakeup (MIW) circuit.2 Therefore, prior to entering Halt Mode, soft-
ware must first configure the MIW circuit. After a wakeup from Halt Mode, a THALT_REC3 start-up delay is initiated to allow the
internal oscillator and other analog circuits to stabilize before normal device execution resumes. Immediately after exiting Halt
Mode, software must clear the Power Mode Clear (PMC) register by using only the “LD M, #” instruction (see Figure 5).
Table 4. HALT Register Definition
HALT Register (addr. 0xB7)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
EIDLE
EHALT
Figure 5. Recommended Halt/Idle Flow
Normal Mode
Normal Mode
HALT, #02H
Idle Mode
LD HALT, #01H
Halt Mode
LD
Timer 0
Overflow
Multi-Input
Wakeup
Multi-Input
Wakeup
LD PMC, #00H
LD PMC, #00H
Resume Normal
Mode
Resume Normal
Mode
3.1.1 PLL Steps for Halt Mode
When using Halt Mode and the PLL in an application, software must take the appropriate steps in order to keep the integrity of
the clock structure before entering and after exiting Halt since the PLL must be disabled. While in Halt Mode, all other device
circuits except for the MIW are disabled. Once the PLL is disabled, all output frequencies are turned off. If the PLL is re-
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FMS7401/7401L
PRODUCT SPECIFICATION
enabled, it must complete the lock phase before software may enable the use of the outputs to clock any of the device circuits.
Therefore, upon exiting Halt Mode software must wait the TPLL_LOCK3 to ensure that the PLL is locked into its appropriate
frequency and in phase.
1. Initially, the PLLEN bit of the PSCALE register must be set in order to enable the PLL circuit.
2. If the PLL outputs are to be used to clock any of the device circuits, FMODE and/or FSEL of the PSCALE register must
be set after the appropriate TPLL_LOCK wait time.4
3. Prior to entering Halt Mode, software must clear both FMODE and FSEL (the PWM Timer 1 must be disabled in order to
clear either bit) keeping the PLLEN bit 1.
4. Using a separate instruction (e.g. RBIT PLLEN, PSCALE) disable the PLL by clearing the PLLEN bit.
5. Software may then instruct the device to enter Halt Mode.
6. If all disabled circuits must be re-enabled after exiting from Halt Mode, repeat all initial steps enabling all
circuits in the appropriate order as well as waiting TPLL_LOCK
.
3.2 Idle Mode
In addition to the Halt Mode power saving feature, the device also supports an Idle Mode operation. The device is placed into
Idle Mode by setting the Idle enable bit (EIDLE) of the HALT register through software using either the “LD M, #” or the
“SBIT #, M” instructions. EIDLE is a write only bit and is automatically cleared upon exiting Idle Mode. The Idle Mode
operation is similar to Halt Mode except the internal oscillator, PLL, and Timer 0 circuits remain active while the other on-chip
systems including the Programmable Comparator (COMP) and Brown-out Reset (BOR) circuits are shut down. For the
FMS7401, to maintain proper Vcc voltage regulation, the internal regulator circuit remains enabled while in Idle Mode.
The device exits Idle Mode automatically by the Timer 0 Idle overflow every 8192 cycles and by the Multi-input Wakeup
(MIW) circuit.2 Software must first configure the MIW prior to entering Idle Mode in order to wake the device from Idle with-
out waiting for the overflow to occur. Once a wake from Idle Mode is triggered, the normal device execution resumes by the
next clock cycle. Immediately after exiting Idle Mode, software must clear the Power Mode Clear (PMC) register by using only
the “LD M, #” instruction (see Figure 5).
3.2.1 PLL Steps for Idle Mode
When using Idle Mode, the PLL does not need to be disabled prior to entering Idle as it does with Halt Mode. The PLL may
remain enabled the entire time the device is in Idle; however, the device will consume additional current. If current consump-
tion is important, consider using Halt instead of Idle Mode or at least disabling the PLL while in Idle.
By keeping the PLL enabled while in Idle Mode, the PLL’s outputs remain ready for use at any moment. With the PLL’s out-
puts available, software has the option to source the main system clock (FICLK) by the PLL’s F(FS=0) output when the FMODE
bit of the PSCALE register is set.4 In addition, if the PLL’s FPWMCLK output is clocking the PWM Timer 1 circuit,5 the timer
may remain operational while in Idle Mode. However, the total current consumption will increase, hence the recommendation
to disable the PWM Timer 1 before entering Idle Mode. In contrast, if FICLK is clocking the PWM Timer 1, the timer circuit
execution (like the main system controller) is stopped during Idle. Whether the PWM Timer 1 is operational or not during Idle
Mode, the instruction execution is stopped therefore all pending flags, etc. cannot be serviced.
If the PLL is to be disabled prior to entering Idle Mode, software must take the appropriate steps in order to keep the integrity
of the clock structure. Once the PLL is disabled, all output frequencies are turned off. If the PLL is re-enabled, it must com-
plete the lock phase before software may enable the use of the outputs to clock any of the device circuits. Therefore, upon exit-
ing Idle Mode software must wait the TPLL_LOCK to ensure that the PLL is locked into its appropriate frequency and in phase.
14
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PRODUCT SPECIFICATION
FMS7401/7401L
1. Initially, the PLLEN bit of the PSCALE register must be set in order to enable the PLL circuit.
2. If the PLL outputs are to be used to clock any of the device circuits, FMODE and/or FSEL of the PSCALE register must
be set after the appropriate TPLL_LOCK wait time.
3. Prior to entering Idle Mode, software must clear both FMODE and FSEL (the timer must be disabled in order to clear
either bit) keeping the PLLEN bit 1.
4. Using a separate instruction (e.g. RBIT PLLEN, PSCALE) disable the PLL by clearing the PLLEN bit.
5. Software may then instruct the device to enter Idle Mode.
6. If all disabled circuits must be re-enabled after exiting from Idle Mode, repeat all initial steps enabling all circuits in the
appropriate order as well as waiting TPLL_LOCK
.
1. Contact your local Fairchild Sales Representative for FMS7401 availability.
2. The MIW and Timer 0 Circuits are described later in the datasheet.
3. Refer to the Electrical Characteristics section of the datasheet for details.
4. Refer to the Clock Circuit’s PLL section of the datasheet for details.
5. The FSEL bit in the PSCALE register must be set.
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FMS7401/7401L
PRODUCT SPECIFICATION
4 ADC Circuit
The Analog-to-Digital Converter (ADC) Circuit extends the features of the FMS7401/7401L by offering a 5-channel 8-bit
ADC. The ADC may be programmed to convert voltages on any of the eight inputs of the analog mux, where five are multi-
function input channels (ACH1-ACH5) and three are used for system calibration. The integrated ADC function offers a single
cost-effective solution for applications requiring voltage, current and temperature sensing. The multifunction input channels
may be configured to perform standard conversions on any of the analog input pins (G4/AIN0, G3/AIN1, G2/AIN2, G3/AIN3
or G7/AIN4). Three of the multifunction input channels may be programmed to perform ADC conversions through the internal
Autozero Amplifier, Uncommitted Amplifier, and Current Source Generator for special control system and battery manage-
ment applications (see Figure 6).
The ADC Circuit’s eight analog inputs are software selectable where their analog input voltage is converted with respect to the
internal ADC reference voltage (VAREF). VAREF may be programmed to use the internal bandgap reference voltage (VREF) or
Vcc as its source. By default, the ADC circuit’s VAREF is configured to use the internal VREF as its source.1
The ADC performs conversions of 8-bit resolution with accuracy as defined in the Electrical Characteristics section of the
datasheet. For a standard ADC conversion, the ADC circuit converts the analog input voltage in a total of 13 conversion clock
cycles, and a total of 20 conversion clock cycles when performing an autozero ADC conversion. To yield a better ADC conver-
sion accuracy, the ADC circuit may configure the ADC clock (FADCLK) to a slower frequency, lengthening the total conversion
time while improving its accuracy. As part of the total conversion time, the ADC circuit completes a sample and hold phase to
measure fast changing analog signals before converting the voltage. An ADC conversion can be initiated by a software com-
mand or automatically (using the gated auto-sampling mode) by the active (on) edge transition of the ADSTROBE PWM
Timer 1 output.2 If enabled, the ADC circuit offers the use of its microcontroller hardware interrupt (ADCI) triggered after
each completed ADC conversion so that the microcontroller core is freed to perform other tasks.
4.1 ADC Circuit Configuration
Software must access the three memory mapped ADC registers to configure and control the ADC circuit.3 The ADC Control 1
(ADCNTRL1) register is used to select the analog input channel and ADC reference voltage (VAREF) for the conversion. In
addition, it is used to initiate a conversion through software, monitor the ADC pending flag, and enable the ADC circuit’s
microcontroller hardware interrupt (ADCI). The ADC Control 2 (ADCNTRL2) register is used to enable the internal Autozero
Amplifier, Uncommitted Amplifier, Current Source Generator, and/or ADC Auto-sampling Mode. The ADCNTRL2 register is
also used to divide the ADC FADCLK clock to improve the conversion accuracy. Lastly, the ADC Data (ADATA) register is used
by software to read the final converted 8-bit digital value. ADATA is a read only register and is updated automatically at the end
of each ADC conversion.
16
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PRODUCT SPECIFICATION
FMS7401/7401L
Figure 6. ADC Block Diagram4
Vcc
ACHSEL[3:0]
ENIS
Sel
G3/AIN1
G2/AIN2
G1/AIN3
ACH2
ACH3
ACH4
ACH1
ACH5
AGND
+VREF
Vcc/3
ADSTROBE
SAR
S/H
Y
ACH5
LOGIC
8
AGND
+VREF
Analog Voltage
Generator
8
+VAREF
Autozero
Amplifier
FRCLK2
Vcc
SR_GND
G4/AIN0
DELTIME
2R
_
R
x16
+
4
GAIN
Programmable
Delay
PWMOFF
R
+
-
R
+VREF
Vcc
A
COMPSEL
+VREF
+VAREF
Voltage Level
Generator
Y
BSel
G7/AIN4/AOUT
VLOOP
0.23R
6
_
+
G6/-AIN
COMPLEV
REFSEL
+VREF
R
B
ACH5
Y
ASel
ENAMP
4.1.1 ADCNTRL1 Register
The ADCNTRL1 is an 8-bit memory map register used to configure and control the ADC circuits. Software has both read and write
access to all bits of the register.
Bit 7 of the ADCNTRL1 register is the ADC pending (APND) flag and is triggered after the 8-bit converted digital value is latched to
theADATA register towards the end of theADC conversion cycle. TheAPND bit may be used by software to monitor when to access
ADATA or to issue microcontroller hardware interrupts (if enabled). In order for software to monitorAPND, it must be cleared before
the next converted value is latched in ADATA where the APND flag is set to 1.
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FMS7401/7401L
PRODUCT SPECIFICATION
Bit 6 of the ADCNTRL1 register is the ADC’s microcontroller hardware interrupt enabled (AINTEN) bit. If set, hardware
interrupts (ADCI) are enabled and triggered by the APND pending flag.5 As long as the ADC pending flag is set, the hardware
interrupt will continue to execute software’s ADC interrupt service routine until the pending flag is cleared.6
Bit 5 of the ADCNTRL1 register is the ADC Conversion Start/Busy (ASTART) bit. Software must set the ASTART bit to ini-
tiate an ADC conversion when the ENDAS bit of the ADCNTRL2 register is set to 0. The ASTART bit will remain high as long
as an ADC conversion is in progress (whether software or the ADSTROBE signal triggered the conversion). If software
attempts to clear the ASTART bit while a conversion is in progress, the write command is ignored and the ASTART bit remains
high until the conversion cycle completes. Software should monitor ASTART to determine when the conversion has completed
instead of the APND bit. The APND bit may be triggered before the ASTART is automatically cleared. The ADC conversion
completion delay may occur when the FICLK clock is slower than an ADC conversion clock cycle.
Bit 4 of the ADCNTRL1 register is the ADC Voltage Reference Selection (REFSEL) bit. If REFSEL=0, the ADC Reference
Voltage (VAREF) becomes sourced by the internal bandgap voltage reference (VREF). If REFSEL=1, the ADC Reference Voltage
(VAREF) becomes sourced by Vcc. If the ADC circuit is performing a conversion, software must avoid writing to the REFSEL
bit.
Bits 3-0 of the ADCNTRL1 register are the Analog Channel Selection (ACHSEL[3:0]) bits selecting one of the eight analog
input channels to convert its voltage (see Table 6). Software may write to the ACHSEL bits at any time; however, the actual
ACHSEL selection signals will not change while an ADC conversion is in progress. If a read command is issued while a con-
version is in progress, the current value of the ACHSEL bits may not necessarily reflect the actual state of the ACHSEL selec-
tion signals. The last value of the ACHSEL bits written by software at the time of the ADC conversion trigger, dictates the state
of the ACHSEL selection signals for the triggered ADC conversion cycle.
The SBIT or RBIT instructions may be used to either set or clear one of the ADCNTRL1 register bits, like the AINTEN bit.
The SBIT and RBIT instructions both take two instruction clock cycles to complete their execution. In the first cycle, all regis-
ter bits are automatically read to obtain their most current value. In the second cycle, the bit to be set/cleared is given its new
value and all bits are then re-written to the register. Using the SBIT/RBIT instruction to set/clear an enable bit with a pending
flag in the same register may cause a potential hazard. Software may inadvertently clear a recently triggered pending flag if the
trigger happened during the second phase of the SBIT/RBIT instruction execution. To avoid this condition, the LD instruction
must be used to set or clear the interrupt enable bit. The ADC circuit is designed such that software may not trigger a pending
flag by writing a 1 to the APND bit, it may only be cleared. The action of writing a 1 to the APND register bit holds its current
bit value. The action of writing a 0 to the APND register bit clears the bit value. Therefore, the “LD T1CNTRL, #0E0H”
instruction will set the ASTART and AINTEN bits without clearing APND.
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PRODUCT SPECIFICATION
FMS7401/7401L
Table 5. ADCNTRL1 Register Bit Definitions
ADCNTRL1 Register (addr. 0x9F)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
APND
AINTEN
ASTART
REFSEL
ACHSEL[3:0]
Bit
Description
APND
(0) ADC’s pending flag is cleared.
(1) ADC’s pending flag is triggered.
(0) Disables ADC hardware interrupts.
(1) Enables ADC hardware interrupts.
(0) ADC conversion is not in progress.
AINTEN
ASTART
REFSEL
ACHSEL[3:0]
(1) Start an ADC conversion / ADC conversion in progress.
(0) ADC Reference (VAREF) = Internal VREF
(1) ADC Reference (VAREF) = Vcc
Analog Input Channel Selection Bits. Refer to Table 6 for details.
Table 6. Analog Input Channel Selection (ACHSEL[3:0]) Bit Definitions
ACHSEL[3]
ACHSEL[2]
ACHSEL[1]
ACHSEL[0]
Analog Channel
I/O Equiv.
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
1
0
0
1
1
0
0
1
0
0
1
0
1
0
1
0
0
ACH1
ACH2
ACH3
ACH4
ACH5
AGND
+VREF
Vcc/3
G4/AIN0
G3/AIN1
G2/AIN2
G1/AIN3
G7/AIN4/AOUT
-
-
-
4.1.2 ADCNTRL2 Register
The ADCNTRL2 is an 8-bit memory map register used to configure the analog circuits. Six of the eight register bits are used to
configure circuits directly related to the ADC circuit while the others are not related.
Bit 7 (REFBY2) of the ADCNTRL2 register is the reference clock (FRCLK1) divide-by-2 enable bit. The REFBY2 bit config-
ures the reference clock of the PLL and Programmable Comparator circuit to be sourced either by FRCLK1 or FRCLK1/2 clock.
Refer to the Clock Circuit section of the datasheet for additional details.
Bit 6 (COMPSEL) of the ADCNTRL2 register is the Programmable Comparator’s non-inverting input selection bit. If
COMPSEL=0, the non-inverting input of the Programmable Comparator is the G4/AIN0 device pin. If COMPSEL=1, the
non-inverting input of the Programmable Comparator is the G2/AIN2 device pin. Before enabling the Programmable
Comparator circuit, the selected analog input port pin must be configured as a tri-state input bypassing the I/O circuitry.9
Refer to the Programmable Comparator Circuit section of the datasheet for addition details.
Bit 5 of the ADCNTRL2 register is the Uncommitted Amplifier Enable (ENAMP) bit. If ENAMP=0, the Uncommitted Ampli-
fier circuit is disabled and its pin connections (G6/-AIN and G7/AOUT) may be used as normal I/O ports. The G7/AIN4 pin may
still be used as a standard ADC conversion input through the analog ACH5 channel. If ENAMP=1, the Uncommitted Amplifier
circuit is enabled and its pin connections must be configured as tri-state inputs where G6/-AIN is the inverting input and G7/
AOUT is the amplifier output.9 If the ADC circuit is performing a conversion on the analog ACH5 input when driven by the
Uncommitted Amplifier, software must avoid clearing the ENAMP bit. Refer to the following Uncommitted Amplifier section
for additional details.
Bit 4 (ENDAS) of the ADCNTRL2 register enables the ADC conversion’s gated auto-sampling operating mode. If ENDAS=1,
the ADC circuit configures the FADCLK clock for synchronization with the PWM Timer 1’s ADSTROBE output signal. The
ADC circuit will then accept triggers by the active (on) edge transition of the ADSTROBE signal. All other ADC configuration
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19
FMS7401/7401L
PRODUCT SPECIFICATION
options must be prepared prior to setting the ENDAS bit. Refer to the following ADC Gated Auto-sampling Mode section for
additional details. The ADSTROBE signal is generated by the PWM Timer 1 circuit and is configured using its T1CMPB and
T1RA registers. Refer to the PWM Timer 1 Circuit section of the datasheet for details regarding its operation. If ENDAS=0,
the ADC circuit is configured to accept only ADC start commands issued by software when setting the ASTART bit of the
ADCNTRL1 register to 1. Refer to the following ADC Conversion Modes section for additional details.
Bits 3 and 2 (ASPEED[1:0]) of the ADCNTRL2 register selects the divide factor (1, 2, 4, or 8) to slow the FADCLK clock
extending the ADC conversion cycle time. In most cases, the FADCLK clock division is performed to improve the ADC
conversion accuracy. Refer to the following ADC Conversion Clock Configuration section for addition details.
Bit 1 of the ADCNTRL2 register is the Current Source Generator Enable (ENIS) bit. If ENIS=0, the Current Source Generator
circuit is disabled and its G3/AIN1 pin may be used as a normal I/O port or as a standard ADC conversion input through the
analog ACH2 channel. If ENIS=1, the Current Source Generator circuit is enabled and its pin connection must be configured as
a tri-state input bypassing the I/O circuitry.9 If the ADC circuit is performing a conversion on the analog ACH2 input when
driven by the Current Source Generator, software must avoid clearing the ENIS bit. Refer to the following Current Source
Generator section for additional details.
Bit 0 (GAIN) of the ADCNTRL2 register is the autozero amplifier enable bit. If GAIN=0, the autozero amplifier with its gain
16 circuitry is disabled where its G4/AIN0 pin connections may be used as a normal I/O port. The G4/AIN0 pin may still be
used as a standard ADC conversion input through the analog ACH1 channel. If GAIN =1, the autozero amplifier with its gain
16 circuitry is enabled and its G4/AIN0 pin connection must be configured as a tri-state input where G4/AIN0 is the non-
inverting and SR_GND is the inverting input of the amplifier.9 Software may write to the GAIN bit at any time; however, the
actual GAIN enable signal will not change while an ADC conversion is in progress. If a read command is issued while a con-
version is in progress, the current value of the GAIN bit may not necessarily reflect the actual state of the GAIN enable signal.
The last value of the GAIN bit written by software at the time of the ADC conversion trigger, dictates the state of the GAIN
enable signal for the triggered ADC conversion cycle. Refer to the following Autozero Amplifier section for additional details.
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PRODUCT SPECIFICATION
FMS7401/7401L
Table 7. ADCNTRL2 Register Bit Definitions
ADCNTRL2 Register (addr. 0xA0)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
REFBY2
COMPSEL
ENAMP
ENDAS
ASPEED[1:0]
ENIS
GAIN
Bit
Description
REFBY2
Used to divide the reference clock for the PLL and digital filter of the Programmable Comparator circuit. Refer to the Clock
Circuit section of the datasheet for details.
(0) FRCLK2=FRCLK1
(1) FRCLK2=FRCLK1/2
COMPSEL
ENAMP
(0) G4 is connected to the Programmable Comparator’s non-inverting input.
(1) G2 is connected to the Programmable Comparator’s non-inverting input.
(0) Disables the Uncommitted Amplifier (G6 and G7 are normal I/Os).
(1) Enables the Uncommitted Amplifier where G6/-AIN is the inverting input and G7/AOUT is the amplifier output. The
amplifier output (AOUT) is also the ACH5 input to the ADC’s analog mux.
ENDAS
(0) Enables the Standard ADC Conversion Mode where software must trigger an ADC conversion by setting the ASTART
bit of the ADCNTRL1 register.
(1) Enables the ADC Gated Auto-sampling Mode where PWM Timer 1’s ADSTROBE output to automatically triggers an
ADC conversion.
ASPEED[1:0]
(0) ADC conversion clock speed = FADCLK
(1) ADC conversion clock speed = FADCLK/2
(2) ADC conversion clock speed = FADCLK/4
(3) ADC conversion clock speed = FADCLK/8
ENIS
GAIN
(0) Disable Current Source Generator (G3 is a normal I/O).
(1) Enable Current Source Generator where G3/AIN1 sources the ISRC
.
(0) Disables the Autozero Amplifier (G4 is a normal I/O).
(1) Enables the Autozero Amplifier (with a gain of 16) where G4/AIN0 is its non-inverting input and SR_GND is it inverting
input.
4.2 ADC Conversion Modes
The ADC circuit may be configured to convert analog voltages with a conversion cycle time determined by the ADC clock
(FADCLK) and the ASPEED bits of the ADCNTRL2 register. Refer to the following ADC Conversion Clock Configuration
section for details. By default, the ADC circuit performs a conversion with every trigger initiated by software setting the
ASTART bit of the ADCNTRL1 register to 1. The ADC circuit may also be configured to perform a conversion automatically
(using the gated auto-sampling mode) with every active (on) edge of the PWM Timer 1 ADSTROBE output signal. Refer to the
following ADC Gated Auto-sampling Mode section for details.
Before any ADC conversion triggers are issued (by software or automatically) software must configure the voltage reference
(VAREF) and analog input channel appropriately. This is done by programming the REFSEL and ACHSEL bits of the
ADCNTRL1 register. If using the internal Autozero Amplifier, Uncommitted Amplifier, and Current Source Generator circuits
in the application, software must also configure and enable the desired circuits. Lastly, the FADCLK must be configured to
improve the ADC conversion accuracy.
When performing an ADC conversion where software triggers the conversion, the ASTART bit of the ADCNTRL1 register
remains high (1) symbolizing that a conversion is in progress. The ADC conversion is divided in two phases lasting a total of
13 conversion clock cycles. However, an autozero ADC conversion lasts a total of 20 conversion clock cycles. Refer to the fol-
lowing Autozero Amplifier section for details. In the first phase of a standard conversion, occupying the first four conversion
cycles, the ADC circuit performs a sample and hold operation to measure fast changing analog signals before converting the
input voltage. The second phase, occupying the last nine cycles, converts the analog input voltage to an 8-bit digital value and
stores it in the ADATA register for easy access by software. Once the converted value is stored in ADATA, the APND bit is trig-
gered and ASTART bit is cleared (symbolizing completion of the conversion cycle). Software cannot rely on the APND bit for
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FMS7401/7401L
PRODUCT SPECIFICATION
this information because the APND bit may be triggered before the ASTART is automatically cleared. The ADC conversion
completion delay may occur when the FICLK clock is slower than an ADC conversion clock cycle.
4.2.1 Analog Input Voltage and its 8-bit Digital Result
The relationship between the 8-bit digital value stored in the ADATA register and the analog input voltage is as follows:
VACH(x)
VAREF
--------------------
× 255
VADC
=
• VADC is the 8-bit digital result of an ADC conversion.
• VACH(x) is the analog voltage applied to the selected input channel.
4.2.2 ADC Gated Auto-sampling Mode
The ADC circuit may be configured in Gated Auto-sampling Mode by setting the ENDAS bit of the ADCNTRL2 register.
When in Auto-sampling Mode, all ADC conversions are automatically triggered by the active (on) edge transition of the PWM
Timer 1’s ADSTROBE output signal.2 If the period of the PWM ADSTROBE signal is less than the total ADC conversion
time, any triggers issued while a conversion is in progress (ASTART=1) are ignored. Once the trigger is detected, the ASTART
bit of the ADCNTRL1 register is set symbolizing that a conversion is in progress. The initial conversion phase, the sample and
hold or autozero (if GAIN=1), begins after a 1µS cycle delay.7 Once all eight digital bits are determined and stored in the
ADATA register, the APND flag is set to trigger a hardware interrupt (if enabled) flagging software that the ADATA register has
been updated with the ADC conversion results. Once all phases of the ADC conversion cycle completes, the ASTART bit is
then automatically cleared by the ADC circuit. Since software cannot change the ADC circuit configuration while an ADC con-
version is in progress, the ASTART bit must be monitored to determine when the conversion cycle completes. Software cannot
rely on the APND bit for this information because the APND bit may be triggered before the ASTART is automatically cleared.
The ADC conversion completion delay may occur when the FICLK clock is slower than an ADC conversion clock cycle.
4.2.3 ADC Conversion Clock Configuration
The ADC conversion clock (FADCLK) is sourced either by the device’s main system instruction clock (FICLK) or the PWM Timer
1’s clock (FT1CLK) depending on the ADC circuit’s operating mode. If the standard ADC conversion mode is selected, the ADC
circuit is automatically configured to source the FADCLK clock by the FICLK clock. If the ADC Conversion Auto-sampling Mode
is selected, the ADC circuit is automatically configured to source the FADCLK clock by the FT1CLK clock to synchronize the ADC
conversions with the active (on) edge of the PWM Timer 1 ADSTROBE output signal.2
When in standard ADC conversion mode, the ASPEED[1:0] bits of the ADCNTRL2 register may be used to slow the total con-
version time improving the ADC conversion accuracy. However, if the FICLK clock is sourced by the PLL’s F(FS=0) output (when
FMODE=1) the FADCLK will clock eight times faster than the proper conversion rate (1µS cycle time). The FADCLK clock must
then be divided by setting the ASPEED[1:0]=3 divide factor to yield a FADCLK/8 conversion clock cycle. Otherwise, software
may temporarily clear FMODE returning the conversion cycle to its proper frequency and free the ASPEED bits to be used to
improve the conversion accuracy. In addition, if the internal oscillator is trimmed to its upper FOSC frequency and it is sourcing
the FICLK clock, the ASPEED[1:0]=1 divided factor must be selected to yield a FADCLK/2 conversion clock cycle.8 A greater
divide factor may still be selected by setting the ASPEED[1:0]>1.
When in ADC Conversion Auto-sampling Mode, the ADC circuit automatically configures the FADCLK clock to be sourced by
the FT1CLK clock so that the ADC conversions may be synchronized with the active (on) edge of the ADSTROBE signal. How-
ever, the FT1CLK clock is first sent into a special divide circuit which evaluates its configuration to determine the divide factor
needed to yield the proper FADCLK conversion rate (1µS cycle time). The FMODE, FSEL, and FS bits of the PSCALE register
are evaluated so that the divide circuit applies the appropriate divide factor to the FT1CLK clock (the PS bits do not apply). The
ASPEED[1:0] bits of the ADCNTRL2 register may be used to slow the total conversion time improving the ADC conversion
22
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PRODUCT SPECIFICATION
FMS7401/7401L
accuracy. However, if the internal oscillator is trimmed to its upper FOSC frequency while FMODE and FSEL are zero, the
ASPEED[1:0]=1 divided factor must be selected to yield a FADCLK/2 conversion clock cycle.8 A greater divide factor may still
be selected by setting the ASPEED[1:0]>1.
4.3 Autozero Amplifier
The GAIN bit of the ADCNTRL2 register enables the Autozero Amplifier circuit. To perform a proper ADC conversion using
the autozero amplifier, software must configure its non-inverting input (G4/AIN0) as a tri-state input bypassing the I/O
circuitry. The autozero amplifier has a gain of 16, but is not defined as a true differential amplifier because the inverting
SR_GND input must be connected as close to ground as possible (e.g. to act as a Kelvin connection) to reduce noise and
improve the precision of the measurement.
To perform an ADC conversion through the autozero amplifier, the ACH1 input channel of the analog mux must be selected.
The autozero ADC conversion is divided in three phases lasting a total of 20 conversion clock cycles. In the first phase, occu-
pying the first six conversion cycles, it calculates the offset voltage of the amplifier. The second phase, occupying the next five
cycles, adds or subtracts the offset voltage to the amplified input voltage which now has a gain of 16. The final phase, occupy-
ing the last nine cycles, converts the autozero input voltage to an 8-bit digital value and stores it in the ADATA register for easy
access by software.
4.4 Uncommitted Amplifier
The Uncommitted Amplifier Enable (ENAMP) bit of the ADCNTRL2 register enables the Uncommitted Amplifier (AMP)
circuit whose inverting input is connected to the G6/-AIN and output to the G7/AOUT port pins. Before enabling the AMP
circuit, software must configure both the G6/-AIN and G7/AOUT pins as tri-state input ports bypassing all I/O circuitry. The
AMP circuit may be used in any control or battery management applications.
In control applications, the AMP circuit is used as the error amplifier in a hardware closed loop whose input connections are
part of the external compensation loop circuit. The output of the amplifier (AOUT) is internally fed to the Programmable
Comparator circuit to control the PWM T1HS1 and T1HS2 inputs of the control plant block. An ADC conversion may be
triggered to monitor AOUT by selecting the ACH5 input channel of the analog mux.
The AMP circuit may be configured as a general uncommitted amplifier whose non-inverting input is connected to VREF
.
Therefore, the AMP circuit may only amplify differences with respect to VREF. An ADC conversion may be triggered to con-
vert the voltage at AOUT by selecting the ACH5 input channel of the analog mux. In battery management applications, the AMP
circuit may be used to improve the resolution of the battery voltage measurement by adding a gain through the feedback loop.
Voltage variation at a typical point will be amplified with a gain for better resolution, for example, to sense the Negative Delta
V (NDV) to determine the end of change for a NiCD or NiMH battery.
4.5 Current Source Generator
The Current Source Enable (ENIS) bit of the ADCNTRL2 register enables the Current Source Generator (ISOURCE) circuit
connected to the G3/AIN1 pin. Before enabling the ISOURCE circuit, software must configure the G3/AIN1 port as a tri-state
input bypassing all I/O circuitry.9 Once the ENIS bit is set, the ISOURCE circuit begins to generate ISRC of current typically
used to interface to an opto-coupler output.1 Figure 7 provides an example of a typical ISOURCE application where the
voltage developed at the G3/AIN1 input can be converted by the ADC circuit if the ACH2 analog input channel is selected.
The ISOURCE and ADC circuit combination may also be used to measure Capacitive Sensors or the resistance of a thermistor
(NTC/PTC) to indirectly measure the temperature.
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23
FMS7401/7401L
PRODUCT SPECIFICATION
Figure 7. Current Generator Interface
Vcc
Control
Voltage
Analog
ADC
Mux
G3/AIN1
1. Refer to the Electrical Characteristics section of the datasheet for details.
2. Refer to the PWM Timer 1 Circuit section of the datasheet for details regarding the ADSTROBE signal configuration.
3. Refer to Table 30 of the Device Memory section of the datasheet for the detailed memory map.
4. On the FMS7401L 8-pin device, the SR_GND is internally bonded to the GND pin.
5. Hardware interrupts are not executed by the microcontroller core unless the Global Interrupt enable (G) flag of the Status register is set. Refer to the 8-Bit
Microcontroller Core section of the datasheet for details.
6. The ADC hardware interrupt will be executed in the defined priority order. Refer to the 8-Bit Microcontroller Core section of the datasheet for details.
7. Assuming the internal oscillator frequency is FOSC=2MHz as specified in the Electrical Characteristics section of the datasheet.
8. The upper FOSC frequency (4MHz) is not a standard feature offered on the FMS7401/7401L devices but is available upon request.
9. Refer to the I/O Ports section of the datasheet for details.
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PRODUCT SPECIFICATION
FMS7401/7401L
5 Programmable Comparator Circuit
The Programmable Comparator circuit is an analog comparator whose outputs may be monitored by software or fed into a dig-
ital delay filter used to disable the PWM Timer 1 circuit or its PWM cycle. The comparator’s non-inverting input is software
selectable by the COMPSEL bit of the ADCNTRL2 register.1 If COMPSEL=0, the non-inverting input of the Programmable
Comparator is the G4/AIN0 device pin. If COMPSEL=1, the non-inverting input of the Programmable Comparator is the G2/
AIN2 device pin. Before enabling the Programmable Comparator circuit, the selected analog input port pin must be configured
as a tri-state input bypassing the I/O circuitry.2 The inverting input of the comparator is controlled by the Voltage Loop
(VLOOP) enable bit of the comparator control (COMP) register. If VLOOP=0, the voltage loop is disabled and the inverting
input of the analog comparator is configured as one of the 63 programmable voltage levels (VTHL, VTHU). If VLOOP=1, the
analog comparator is set in a voltage loop configuration with the Uncommitted (Error) Amplifier output (AOUT) connected to
the comparator’s inverting input (see Figure 9).
The Programmable Comparator circuit may be configured and controlled by software through the two 8-bit Comparator
Control (COMP) and Digital Delay (DDELAY) registers. Both the Programmable Comparator and the digital delay filter
must be enabled by software by setting the Comparator Enable (COMPEN) and clearing the EPWM bits of the Digital Delay
(DDELAY) register. Upon a system reset, the Programmable Comparator is disabled and the digital delay filter is enabled.
The COMP circuit is automatically disabled during Halt Mode. After exiting the Halt Mode, software must wait at least 10
instruction clock cycles before reading the COUT bit to ensure that the internal circuit has stabilized.
Table 8. Programmable Comparator (COMP) Control Register Bit Definitions
COMP Register (addr. 0xA0)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CL[5:0]
VLOOP
COUT
Bit
Description
CL[5:0]
VLOOP
Programmable Comparator Voltage Reference Level bits. Refer to Table 9 and Table 10 for details.
(0) Configures the inverting input of the analog comparator as one of the 63 programmable voltage levels (VTHL, VTHU).
(1) Configures the analog comparator in a voltage loop configuration with the Uncommitted Amplifier output (AOUT
connected to the inverting input.
)
COUT
(0) G2/AIN2 or G4/AIN0 non-inverting input is less than inverting input configured by VLOOP.
(1) G2/AIN2 or G4/AIN0 non-inverting input is greater than inverting input configured by VLOOP.
5.1 Programmable Comparator’s Voltage Threshold Levels (VLOOP=0)
The Programmable Comparator circuit is configured to compare the G4/AIN0 or G2/AIN2 non-inverting input against the pro-
grammable voltage threshold levels on its inverting input (see Table 9 and Table 10). The comparator output (COUT) is 1 when
the G4/AIN0 or G2/AIN2 input pin rises above the selected voltage threshold. As long as the input stays above the selected
voltage threshold, the COUT signal will hold its state. The COUT signal will equal zero if the G4/AIN0 or G2/AIN2 input voltage
falls below the programmed threshold voltage or if the Programmable Comparator circuit is disabled. Software may change the
programmed threshold voltage on-the-fly as needed in the application. If the digital delay filter circuit is enabled (EPWM=0),
the COUT signal is monitored for its rising edge to generate the PWMOFF signal. Refer to Figure 8 and the following Digital
Delay Filter with PWMOFF Output section for addition details.
Bit 6 of the ADCNTRL2 register is the Programmable Comparator non-inverting input selection (COMPSEL) bit.1 If
COMPSEL=0, the non-inverting input of the Programmable Comparator is the G4/AIN0 device pin. If COMPSEL=1, the non-
inverting input of the Programmable Comparator is the G2/AIN2 device pin. Before enabling the Programmable Comparator
circuit, the selected analog input port pin must be configured as a tri-state input bypassing the I/O circuitry.2
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FMS7401/7401L
PRODUCT SPECIFICATION
Bits 7-2 (CL[5:0]) is the comparator voltage threshold level selection bits of the Comparator Control (COMP) register. The CL
bits may be programmed to select one of the voltage threshold levels as the inverting input of the analog comparator. Refer to
Table 9 and Table 10 for a detailed list of voltages.
Bit 1 of the Comparator Control (COMP) register is the Programmable Comparator circuit’s voltage loop (VLOOP) configura-
tion enable bit. If VLOOP=0, the Programmable Comparator circuit is configured to compare the analog G4/AIN0 or G2/AIN2
input (COMPSEL=0 or 1) to one of the 63 voltage threshold levels. If VLOOP=1, enables the voltage loop configuration where
the analog G4/AIN0 or G2/AIN2 input (COMPSEL=0 or 1) to the Uncommitted (Error) Amplifier output (AOUT).
Bit 7 of the Digital Delay (DDELAY) register is the Programmable Comparator circuit enable (COMPEN) bit. If COMPEN=0,
the Programmable Comparator circuit is disabled and the COUT signal is low. If COMPEN=1, the Programmable Comparator
circuit is enabled and the COUT signal generated by the comparison of the two inputs.
The comparator output (COUT) signal is latched by the main system instruction (FICLK) clock into bit 0 (COUT) of the Compar-
ator Control (COMP) register. Software may only read the COUT bit to monitor the comparator’s activity. The COUT bit
cannot cause a microcontroller hardware interrupt or perform any other action.
Figure 8. Programmable Comparator Block Diagram (VLOOP = 0)
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PRODUCT SPECIFICATION
FMS7401/7401L
Table 9. Programmable Comparator Lower Voltage Reference VTHL (Levels 1 – 31)
CL[0]
Voltage Reference
35mV
Level
1
CL[5]
0
CL[4]
0
CL[3]
0
CL[2]
0
CL[1]
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2
0
0
0
0
1
50mV
3
0
0
0
0
1
64mV
4
0
0
0
1
0
78mV
5
0
0
0
1
0
93mV
6
0
0
0
1
1
107mV
121mV
135mV
150mV
164mV
178mV
192mV
205mV
219mV
233mV
247mV
261mV
274mV
288mV
302mV
316mV
330mV
343mV
358mV
371mV
385mV
401mV
413mV
429mV
443mV
459mV
7
0
0
0
1
1
8
0
0
1
0
0
9
0
0
1
0
0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
1
0
1
0
0
1
0
1
0
0
1
1
0
0
0
1
1
0
0
0
1
1
1
0
0
1
1
1
0
1
0
0
0
0
1
0
0
0
0
1
0
0
1
0
1
0
0
1
0
1
0
1
0
0
1
0
1
0
0
1
0
1
1
0
1
0
1
1
0
1
1
0
0
0
1
1
0
0
0
1
1
0
1
0
1
1
0
1
0
1
1
1
0
0
1
1
1
0
0
1
1
1
1
0
1
1
1
1
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27
FMS7401/7401L
PRODUCT SPECIFICATION
Table 10. Programmable Comparator Upper Voltage Reference VTHU (Levels 32 – 63)
CL[0]
Voltage Reference
0.46V
0.51V
0.56V
0.61V
0.66V
0.71V
0.76V
0.81V
0.86V
0.91V
0.96V
1.01V
1.06V
1.11V
1.16V
1.21V
1.27V
1.32V
1.37V
1.43V
1.48V
1.53V
1.58V
1.63V
1.68V
1.73V
1.78V
1.83V
1.88V
1.94V
1.99V
2.04V
Level
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
CL[5]
1
CL[4]
0
CL[3]
0
CL[2]
0
CL[1]
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
0
0
0
1
0
0
0
1
1
0
0
0
1
1
0
0
1
0
1
0
0
1
0
1
0
0
1
1
1
0
0
1
1
1
0
1
0
0
1
0
1
0
0
1
0
1
0
1
1
0
1
0
1
1
0
1
1
0
1
0
1
1
0
1
0
1
1
1
1
0
1
1
1
1
1
0
0
0
1
1
0
0
0
1
1
0
0
1
1
1
0
0
1
1
1
0
1
0
1
1
0
1
0
1
1
0
1
1
1
1
0
1
1
1
1
1
0
0
1
1
1
0
0
1
1
1
0
1
1
1
1
0
1
1
1
1
1
0
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
5.2 Hardware Voltage and Current Loop Control (VLOOP=1)
The Programmable Comparator circuit is configured to compare the G4/AIN0 or G2/AIN2 non-inverting input against the out-
put of the Uncommitted (Error) Amplifier (AOUT) when configured in a voltage/current loop control mode. In the voltage/cur-
rent loop control, the inner (current) loop is performed by comparing the level on the G4/AIN0 or G2/AIN2 input against the
voltage present at the Uncommitted (Error) Amplifier (AOUT). The Uncommitted Amplifier performs the outer (voltage) loop
control by detecting the error signal and driving the current control loop to modify the PWM duty cycle (see Figure 9). The
FMS7401/7401L voltage/current loop configuration can be used in SMPS applications where the digital loop control does not
have the required accuracy and speed. Refer to the ADC Circuit section of the datasheet for the Uncommitted Amplifier config-
uration details.
When VLOOP=1, the comparator output (COUT) is 1 when the G4/AIN0 or G2/AIN2 input pin rises above AOUT. As long as the
input stays above AOUT, the COUT signal will hold its state. The COUT signal will equal zero if the G4/AIN0 or G2/AIN2 input
voltage falls below AOUT or if the Programmable Comparator circuit is disabled. If the digital delay filter circuit is enabled
(EPWM=0), the COUT signal is monitored for its rising edge to generate the PWMOFF signal. Refer to Figure 9 and the
following Digital Delay Filter with PWMOFF Output section for addition details.
28
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PRODUCT SPECIFICATION
FMS7401/7401L
Bit 6 of the ADCNTRL2 register is the Programmable Comparator non-inverting input selection (COMPSEL) bit.1 If
COMPSEL=0, the non-inverting input of the Programmable Comparator is the G4/AIN0 device pin. If COMPSEL=1, the non-
inverting input of the Programmable Comparator is the G2/AIN2 device pin. Before enabling the Programmable Comparator
circuit, the selected analog input port pin must be configured as a tri-state input bypassing the I/O circuitry.2
Bit 1 of the Comparator Control (COMP) register is the Programmable Comparator circuit’s voltage loop (VLOOP) configura-
tion enable bit. If VLOOP=0, the Programmable Comparator circuit is configured to compare the analog G4/AIN0 or G2/AIN2
input (COMPSEL=0 or 1) to one of the 63 voltage threshold levels. If VLOOP=1, enables the voltage loop configuration where
the analog G4/AIN0 or G2/AIN2 input (COMPSEL=0 or 1) to the Uncommitted (Error) Amplifier output (AOUT).
Bit 7 of the Digital Delay (DDELAY) register is the Programmable Comparator circuit enable (COMPEN) bit. If COMPEN=0,
the Programmable Comparator circuit is disabled and the COUT signal is low. If COMPEN=1, the Programmable Comparator
circuit is enabled and the COUT signal generated by the comparison of the two inputs.
Bit 0 (COUT) of the Comparator Control (COMP) register is the latched comparator output (COUT) signal. If the Programma-
ble Comparator circuit is enabled, the COUT signal is latched by the main system instruction (FICLK) clock into the COUT bit of
the COMP register. Software may only read the COUT bit to monitor the comparator’s activity. The COUT bit cannot cause
any microcontroller hardware interrupt or any other actions.
Figure 9. Programmable Comparator Block Diagram (VLOOP = 1)
DDELAY
Register
EPWM DD[3] DD[2] DD[1] DD[0]
5
3
2
1
0
COMPSEL
(ADCNTRL2[6])
PWMOFF (WKEN[6])
En
DIGITAL DELAY
CIRCUIT
FRCLK2
G2/AIN2
G4/AIN0
Comparator
+
_
COUT
COMP Register
Programmable
Reference
G7/AOUT
G6/-AIN
VLOOP
Uncommitted (Error)
Amplifier
_
0.23R
ACH5
+
R
VREF
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FMS7401/7401L
PRODUCT SPECIFICATION
5.3 Digital Delay Filter with PWMOFF Output
The Programmable Comparator’s output (COUT) is fed into the digital delay filter with a programmable delay time. The COUT
signal toggles from 0 to 1 when the external input (G4/AIN0 or G2/AIN2) voltage is higher than the programmed voltage
threshold or Uncommitted Amplifier output (AOUT), depending on the state of VLOOP. The COUT rising edge transition triggers
the programmable digital delay counter to begin incrementing. With each digital delay count, its value is compared against the
value stored in the DD[3:0] bits of the Digital Delay (DDELAY) control register. If COUT remains high when the digital delay
count equaling DD[3:0] completes, the PWMOFF signal transitions from 0 to 1. This rising edge transition of the PWMOFF
signal is then used to either disable the PWM Timer 1 circuit completely or the current PWM cycle forcing the PWM output
signals to their resting (off) state. The PWMOFF output signal may also be programmed as an input of the G6 port MIW
circuit. Interrupts may be triggered if the G6 port MIW circuit is enabled and configured to trigger its microcontroller hardware
interrupt (EDGEI). Refer to the Multi-input Wakeup Circuit section of the datasheet regarding for configuration details.
Bit 7 of the DDELAY register is the Programmable Comparator circuit enable (COMPEN) bit. If COMPEN=0, the Program-
mable Comparator circuit is disabled and the COUT signal is low. If COMPEN=1, the Programmable Comparator circuit is
enabled and the COUT signal is generated by the comparison of the two inputs.
Bit 6 (PWMINT) of the DDELAY register, if set to 1, selects the PWMOFF signal in place of its G6 input to the MIW circuit.
Software must then enable the MIW PWMOFF/G6 circuit by setting the WKEN[6] bit. The WKEDG[6] bit must also be
cleared to select the rising edge transitions on the PWMOFF signal as its WKPND[6] bit trigger. Software may monitor the
WKPND[6] flag or enable the MIW hardware interrupt (EDGEI) to help detect when the PWMOFF signal is triggered.3
Bit 5 (EPWM) of the DDELAY register is the digital delay filter and PWMOFF signal enable bit. The EPWM bit is active low
so that on power-up (after a system reset) the digital delay filter circuit is automatically enabled once the Programmable
Comparator circuit is enabled. If the Programmable Comparator and PWM Timer 1 circuits are enabled, since the filter is
defaulted enabled, the PWMOFF signal may disable the PWM Timer 1 upon a comparator transition. If the digital delay filter
and PWMOFF circuit is not needed, software must set the EPWM bit to 1 disabling the filter before enabling the Programma-
ble Comparator to prevent unwanted disables of the PWM Timer 1 circuit or its outputs.
Bit 4 (OFFMODE) of the DDELAY register determines how the PWMOFF signal affects the PWM Timer 1 circuit. If OFF-
MODE=0 and the Timer 1 circuit is configured in an enabled PWM Mode, Timer 1 is automatically disabled forcing the PWM
T1HS1 and T1HS2 output signals to their resting (off) states with the rising edge of the PWMOFF signal. The T1C0 bit of the
T1CNTRL2 register is cleared, reinitializing the 12-bit TMR1 counter to 0x000. Software must re-enable the Timer 1 circuit to
reactivate the PWM output signals. If OFFMODE=1 and Timer 1 is configured in PWM Mode, the T1HS1 and T1HS2 output
signals are forced to their resting (off) state until the current PWM cycle completes. Once the PWM cycle completes, the
PWMOFF signal releases the T1HS1 and T1HS2 output signals and they resume with their normal operation even if the COUT
signal remains active (1). The next PWMOFF trigger will not occur until the next rising edge of COUT
.
Bits 3-0 (DD[3:0]) of the DDELAY register determine how long to delay the trigger of the PWMOFF signal once the rising
edge of COUT has been detected. Once the digital delay counter is triggered, the delay count is compared against the value
stored in the DD[3:0] bits. Once the delay counter completes its DD[3:0] count, if COUT remains high, the PWMOFF signal is
triggered. The digital delay counters increment at the device reference clock rate (FRCLK2).4
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PRODUCT SPECIFICATION
FMS7401/7401L
Table 11. Digital Delay (DDELAY) Register Bit Definitions
DDELAY Register (addr. 0xA2)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
COMPEN
PWMINT
EPWM
OFFMODE
DD[3:0]
Bit
Description
COMPEN
PWMINT
EPWM
(0) Disable the Programmable Comparator circuit.
(1) Enable the Programmable Comparator circuit.
(0) The input of the G6 MIW circuit network is the G6/-AIN device pin.
(1) The input of the G6 MIW circuit network is the PWMOFF output signal (not the G6/-AIN device pin).
(0) Enables the Digital Delay Filter circuit. The PWMOFF output is triggered by COUT after the programmed delay (TDDELAY).
(1) Disables the Digital Delay Filter circuit and the PWMOFF output signal.
OFFMODE
DD[3:0]
(0) PWM outputs switched off and Timer 1 stops after a comparator detection with delay.
(1) PWM outputs switched off for the current PWM cycle only.
Digital delay after COUT triggers high, TDDELAY = DD • (1/FRCLK2
)
Figure 10. Digital Delay Timing
Comparator
Output
Digital
Delay
T
DDELAY
Start
Sample
PWMOFF
T1HS1
T1HS2
1. Refer to the ADC Circuit section of the datasheet for additional details.
2. Refer to the I/O Ports section of the datasheet for details.
3. Hardware interrupts are not executed by the microcontroller core unless the Global Interrupt enable (G) flag of the Status register is set. Refer to the 8-Bit
Microcontroller Core section of the datasheet for details.
4. Refer to the Clock Circuit section of the datasheet for details regarding the FRCLK2 clock.
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PRODUCT SPECIFICATION
6 PWM Timer 1 Circuit
The Pulse Width Modulation (PWM) Timer 1 circuit, a programmable 12-bit PWM timer with a 3-bit prescaler can be config-
ured to operate in both PWM and Input Capture Modes. In PWM Mode, the Timer 1 circuit may be configured to generate
pulses of a specified duty cycle and period on the T1HS1 (G0), T1HS2 (G5), and/or ADSTROBE (G1) timer output ports. On
the other hand, in Input Capture Mode, the Timer 1 circuit may be configured to capture and store the current timer value at the
time of a trigger defined by the rising or falling edge of the T1HS2 (G5) input port. In addition, the T1HS1 and ADSTROBE
PWM outputs may be generated as in the PWM Mode.
The Timer 1 circuit backbone is a 12-bit programmable up-counter (TMR1) that is accessible by software, with read-only
access, through the 4-bit TMR1HI and 8-bit TMR1LO memory mapped registers where TMR1={TMR1HI, TMR1LO}.1 Upon
a system reset or once entering a new Timer 1 mode of operation, the 12-bit TMR1 counter is initialized to 0x000. Once a
selected Timer 1 mode is enabled, the TMR1 counter will begin incrementing by the FT1CLK clock with the programmed divide
factor defined by a 3-bit prescaler. Once the TMR1 overflows, TMR1 is reinitialized to 0x000 and resumes incrementing until
software disables the mode. In PWM Mode, the TMR1 overflow value may be programmed by software where, in Input
Capture Mode, the TMR1 will overflow once the 0xFFF count completes. The Timer 1 circuit may be programmed to generate
microcontroller hardware interrupts with every TMR1 overflow and capture.
The Timer 1 FT1CLK clock may be programmed to operate from high to low frequencies with the use of the programmable
digital clock multiplier (PLL) and internal oscillator in order to provide the maximum flexibility for various PWM applica-
tions.
6.1 PWM Timer 1 Configuration Registers
Software must access the six memory mapped PWM Timer 1 registers to configure and control the Timer 1 circuit.1 The 8-bit
Prescale (PSCALE) register is used to configure the entire FMS7401/7401L clock structure including the Timer 1’s FT1CLK
.
The 12-bit Timer 1 Compare A (T1CMPA), Timer 1 Compare B (T1CMPB), and Timer 1 Reload (T1RA) registers are used to
define the PWM output signal’s duty cycle and period. The 5-bit Dead Time (DTIME) register is used to define the time delay
(TDT) between the PWM T1HS1 and T1HS2 edge transitions while in PWM Mode. The Timer 1 Control (T1CNTRL) register
is used to select Timer 1’s operating mode, enable its PWM output signals, and control its hardware interrupt (TMRI1).
6.1.1 PSCALE Register and Timer 1 Clock Configuration
Although the PSCALE register is part of the PWM Timer 1 circuit, its register bits configure the clock structure for the entire
FMS7401/7401L along with the Timer 1 clock (FT1CLK). Refer to the Clock Circuit section of the datasheet for details regard-
ing the device’s clock structure. The FT1CLK source may be supplied by either the programmable FPWMCLK PLL output or the
main instruction (FICLK) clock. Once the FT1CLK source is selected, it may not be changed while the Timer 1 circuit is in PWM
mode and running or in Input Capture Mode (run mode). Upon a system reset, the PSCALE register is automatically initialized
to 0x00.
Bit 7 of the PSCALE register is the PLL circuit enable (PLLEN) bit. Before using any of the PLL outputs, software must
enable the PLL circuit and wait the TPLL_LOCK to ensure that the PLL is locked into its appropriate frequency and in phase. The
PLLEN bit may not be changed while the Timer 1 circuit is in run mode. Any attempts to write to PLLEN under this condition
will be ignored and its value will remain unchanged.
Bits 6 and 5 (FS[1:0]) of the PSCALE register are the bits used to select between the different output frequencies available to
the PLL’s FPWMCLK output signal. FS selects between the four available PLL divide factors (divide-by-1/2/4/8) selecting an out-
put frequency of 8/16/32/64MHz (see Table 13). The FS bits may be changed by software at any time; however, if the Timer 1
circuit is in run mode, the FS value will not change the FPWMCLK output frequency until after the TMR1 counter overflows end-
ing the current PWM cycle. The last FS value at the TMR1 counter overflow will dictate the divide factor of the FPWMCLK out-
put for the next PWM cycle. When reading FS, the value reported will be the last value written by software and may not
necessarily reflect the divide factor for the current PWM cycle.
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Bit 4 of the PSCALE register is the frequency selection (FSEL) bit for the Timer 1 circuit. FSEL is used to select between the
slow or high frequency options, ultimately selecting the FT1CLK to be sourced either by the FICLK or FPWMCLK (see Table 13).
If FSEL=0, the slow frequency option is selected and the FICLK will then source the FT1CLK with either a 1/8MHz frequency
determined by the FMODE bit, as discussed later in the section. If FSEL=1, the high frequency option is selected and the
FPWMCLK will then source the FT1CLK at a frequency selected by the FS[1:0] bits. The FSEL bit may not be set if the PLL is not
enabled (PLLEN=0) or changed while the Timer 1 circuit is in run mode. Any attempts to write to FSEL under this condition
will be ignored and its value will remain unchanged.
Bit 3 (FMODE) of the PSCALE register is the frequency selection bit for the main instruction clock (FICLK). FMODE is used
to select between the slow or high frequency options, ultimately selecting the FICLK to be sourced either by the internal oscilla-
tor (or the external digital clock) operating at FOSC2 or the PLL’s F(FS=0) output signal.3 If FMODE=0, the slow frequency
option is selected and the internal oscillator will then source the FICLK at a FOSC/2 frequency. If FMODE=1, the high frequency
option is selected and the F(FS=0) will then source the FICLK with PLL’s divide-by-8 output frequency. With the FMODE bit
enabled, it is possible to execute instructions at a speed approximately eight times faster than the standard. The FMODE bit
may not be set if the PLL is not enabled (PLLEN=0). Any attempts to write to FMODE while PLLEN=0 will force FMODE=0
ignoring any set instructions. Once the PLL has been enabled, software may change FICLK’s clock source on-the-fly during
normal instruction execution in order to speed-up a particular action.
Bits 2-0 of the PSCALE register are the three prescaler (PS[2:0]) bits used to divide the FT1CLK to obtain a wider frequency
range on the PWM output signals (see Table 14). The PS bits are used by the Timer 1 circuit to increment the 12-bit TMR1 at a
frequency equal to FT1CLK divided-by 1 through 8. The PS bits (like FS) may be changed by software at any time; however, if
the Timer 1 circuit is in run mode, the PS value will not change the prescale division factor until after the TMR1 counter over-
flows ending the current PWM cycle. The last PS value at the TMR1 counter overflow will dictate the prescale divide factor of
the FT1CLK for the next PWM cycle. When reading PS, the value reported will be the last value written by software and may not
necessarily reflect the divide factor for the current PWM cycle.
Table 12. Prescale (PSCALE) Register Bit Definitions
PSCALE Register (addr. 0xA4)
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
PLLEN
FS[1:0]
FSEL
FMODE
PS[2:0]
Bit
Description
PLLEN
(0) Disables the PLL circuit.
(1) Enables the PLL circuit.
FS[1:0]
FSEL
PLL Divide Factor Selection Bits. Refer to Table 13 for details.
(0) Selects FICLK as Timer 1’s clock (FT1CLK) source.
(1) Selects FPWMCLK PLL output as Timer 1’s clock (FT1CLK) source.
FMODE
PS[2:0]
(0) Selects FCLK divided-by-2 output as the main system instruction clock (FICLK) source.
(1) Selects F(FS=0) PLL output as the main system instruction clock (FICLK) source.
Timer 1 Prescale Selection Bits. Refer to Table 13 for details.
Table 13. PLL Divide Factor Selection Bits and the FT1CLK Resolution (FOSC=2 MHz)
FT1CLK
(FSEL=0)
Max PWM Freq.
(8-bit resolution)
Max PWM Freq.
(12-bit resolution)
FSEL=0
FT1CLK
FSEL=0
FS[1:0]
FPWMCLK
8 MHz
FMODE=0
FMODE=1
8 MHz
(FSEL=1)
FMODE=0
3.906 kHz
3.906 kHz
3.906 kHz
3.906 kHz
FSEL=1
31.25 kHz
62.5 kHz
125 kHz
250 kHz
FMODE=0
244.14 Hz
244.14 Hz
244.14 Hz
244.14 Hz
FSEL=1
1.95 kHz
3.9 kHz
0
0
1
1
0
1
0
1
1 MHz
1 MHz
1 MHz
1 MHz
8 MHz
16 MHz
32 MHz
64 MHz
16 MHz
32 MHz
64 MHz
8 MHz
8 MHz
7.8 kHz
8 MHz
15.625 kHz
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PRODUCT SPECIFICATION
Table 14. Timer 1 Prescale Selection (PS) Bits
PS[2]
PS[1]
PS[0]
Timer 1 Clock
FT1CLK / 1
T1CLK / 2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
F
FT1CLK / 3
FT1CLK / 4
FT1CLK / 5
FT1CLK / 6
FT1CLK / 7
FT1CLK / 8
6.1.2 PWM Cycle Configuration Registers
The PWM Timer 1 circuit has three 12-bit (T1CMPA, T1CMPB, T1RA) and one 5-bit (DTIME) configuration registers used to
specify the duty cycle and period of the Timer 1 output signals. Upon a system reset, all four registers are initialized with ones
(0xFFF, 0x1F). All configuration registers must be programmed with their appropriate values prior to enabling the Timer 1
circuit. Except for the DTIME register, the T1CMPA, T1CMPB and T1RA registers may be changed by software at any time;
however, if the Timer 1 circuit is in run mode, the register values will not change the Timer 1 output signal’s attributes until
after the TMR1 counter overflows ending the current PWM cycle. The last register values at the TMR1 counter overflow will
dictate the output signal’s attributes for the next PWM cycle. When reading the registers, the value reported will be the last
value written by software and may not necessarily reflect the output signal’s attributes for the current PWM cycle.
The 12-bit T1RA is Timer 1’s reload/capture register (depending on the selected operating mode). All 12 bits are accessible by
software through the 4-bit T1RAHI and 8-bit T1RALO memory mapped registers where T1RA= {T1RAHI, T1RALO}.1 In
PWM Mode, T1RA configures the period of the T1HS1, T1HS2 and ADSTROBE outputs and determines after what TMR1
count it will overflow (reinitialize to 0x000) to begin the next PWM cycle. In Input Capture Mode, T1RA contains the captured
value of the TMR1 count at the time of the trigger defined by the rising or falling edge of the T1HS2 input.
The 12-bit T1CMPA is Timer 1’s Compare A register that dictates the length of the resting (off) state of the T1HS1 and T1HS2
output signals. All 12 bits are accessible by software through the 4-bit T1CMPAHI and 8-bit T1CMPALO memory mapped
registers where T1CMPA={T1CMPAHI, T1CMPALO}.1 In PWM Mode, the TMR1 counter is compared against T1CMPA
(TMR1=T1CMPA) to determine when the first transition of the T1HS1 and T1HS2 output signals should be triggered. In Input
Capture Mode, the T1CMPA value is still used to configure T1HS1 but has no affect on the T1HS2 signal since it is used as an
input of the Timer 1 circuit in this mode. Software must ensure that the total T1CMPA plus TDT time is not greater than or equal
to the total T1RA plus TDT times.
The 12-bit T1CMPB is Timer 1’s Compare B register that dictates the length of the resting (off) state of the ADSTROBE out-
put signal. All 12 bits are accessible by software through the 4-bit T1CMPBHI and 8-bit T1CMPBLO memory mapped regis-
ters where T1CMPB={T1CMPBHI, T1CMPBLO}.1 The TMR1 counter is compared against T1CMPB to determine when the
first transition of the ADSTROBE output signal should be triggered. If enabled, at the rising edge of ADSTROBE
(TMR1=T1CMPB) an Analog-to-Digital Converter (ADC) conversion may be initiated.4 Software must ensure that the total
T1CMPB plus TDT time is not greater than or equal to the total T1RA plus TDT times.
Bits 4-0 (DT[4:0]) of the DTIME register determines the amount of dead time (TDT) delay, if any, between the T1HS1 and
T1HS2 output signal transitions (see Table 13). In PWM Mode, once the TMR1 counter equals the T1CMPA value, the T1HS1
signal transitions ending its resting (off) state. The dead time delay counter is then initiated incrementing with each edge of the
FT1CLK up to the programmed DT[4:0] value.5 Once TDT has passed, the T1HS2 signal will then transition ending its resting
(off) state. As the TMR1 counter continues, once the TMR1 counter equals the T1RA value, the T1HS2 signal transitions end-
ing its active (on) state. The dead time delay counter is then reinitiated incrementing to the DT[4:0] value. Once TDT has
passed, the T1HS1 signal will then transition ending its active (on) state.
34
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Table 15. Dead Time (DTIME) Register Bit Definitions
DTIME Register (addr. 0xA5)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
DT[4:0]
DT[4:0]
0x00
Dead Time Delay (TDT
No Dead Time Delay
(1/FT1CLK) • DT
)
0x01 – 0x1F
6.1.3 Timer 1 Control Register
The Timer 1 Control (T1CNTRL) register is used to select Timer 1’s operating mode, enable its PWM output signals, and con-
trol its hardware interrupt (TMRI1). Upon a system reset, the T1CNTRL register is automatically initialized to 0x00. Refer to
Table 16 and Table 17 for additional details regarding the T1CNTRL register bits.
Bit 7 (T1C3) of the T1CNTRL register selects between the two Timer 1 operating modes. If T1C3=0, the Timer 1 circuit will
be configured in PWM mode. Once Timer 1 is configured in PWM Mode, the TMR1 counter must be started in order for the
circuit to be enabled and considered to be in run mode. If T1C3=1, the Timer 1 circuit will be configured in Input Capture
Mode. Once in Input Capture Mode, the Timer 1 circuit is immediately enabled and the TMR1 counter will automatically
begin incrementing from its initial state (0x000) until Timer 1’s operating mode is returned to a disabled PWM Mode (its
default). Therefore, software must issue a write command clearing T1C3 and T1C0 within the same instruction. If T1C3 is
cleared while T1C0 is set, the Timer 1 circuit will remain in Input Capture Mode until the TMR1 overflows and TDT completes
ending the current PWM cycle. Once the TMR1 overflows, the operating mode is switched to a disable PWM Mode even
though T1C0=1. Software must clear T1C0 before re-enabling the Timer 1 circuit in any of the two operating modes.
Bit 6 (T1C2) of the T1CNTRL register has two functions depending on Timer 1’s selected operating mode. In PWM Mode,
T1C2 is used to enable the T1HS2 (G5) output signal (if set). Otherwise, the T1C2 bit (if zero) disables the T1HS2 output sig-
nal. The T1HS2 signal on the G5 pin may be configured as an active high or low output depending on the configured PORTGD
configuration. If PORTGD[5]=0, the T1HS2 (G5) output is active high, otherwise it is active low. In Input Capture Mode,
T1C2 is used to select the edge to trigger a TMR1 T1HS2 input capture. If T1C2=0, every rising edge of the T1HS2 input will
trigger a TMR1 capture. If T1C2=1, every falling edge will trigger a capture. Software may change the value of T1C2 at any
time; however, if the circuit is in run mode, T1C2 will not change the circuit’s attribute until after the TMR1 counter overflows
and the TDT passes completing the current PWM cycle. The last T1C2 value after the TDT completes, will dictate the circuit’s
attribute for the next PWM cycle. When reading the T1C2, the value reported will be the last value written by software and
may not necessarily reflect the circuit’s attribute for the current PWM cycle.
Bit 5 (T1C1) of the T1CNTRL register enables or disable the T1HS1 (G0) output signal for either operating mode. If T1C1=1,
the T1HS1 output signal is enabled, otherwise it is disabled. The T1HS1 signal on the G0 pin may be configured as an active
high or low output depending on the configured PORTGD configuration. If PORTGD[0]=0, the T1HS1 (G0) output is active
high, otherwise it is active low. Software may change the value of T1C1 at any time; however, if the circuit is in run mode,
T1C1 will not change the circuit’s attribute until after the TMR1 counter overflows and the TDT passes completing the current
PWM cycle. The last T1C1 value after the TDT completes, will dictate the circuit’s attribute for the next PWM cycle. When
reading the T1C1, the value reported will be the last value written by software and may not necessarily reflect the circuit’s
attribute for the current PWM cycle.
The ADSTROBE signal is outputted through the device’s G1 pin when bit 0 (T1BOUT) of the T1CNTRL register is set
to 1. The ADSTROBE output is always generated by the Timer 1 circuit regardless of the state of T1BOUT. The ADSTROBE
signal on the G1 pin may be configured as an active high or low output depending on the configured PORTGD configuration. If
PORTGD[1]=0, the ADSTROBE (G1) output is active high, otherwise it is active low. Software may change the value of
T1BOUT at any time; however, if the circuit is in run mode, T1BOUT will not change the device’s I/O attribute until after the
TMR1 counter overflows and the TDT passes completing the current PWM cycle. The last T1BOUT value after the TDT com-
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FMS7401/7401L
PRODUCT SPECIFICATION
pletes, will dictate the device’s I/O attribute for the next PWM cycle. When reading the T1BOUT, the value reported will be the
last value written by software and may not necessarily reflect the device’s I/O attribute for the current PWM cycle.
Bit 4 (T1C0) of the T1CNTRL register has two functions depending on Timer 1’s selected operating mode. In PWM Mode,
when T1C0=1, the TMR1 circuit becomes enabled and begins to increment from its initial 0x000 state; otherwise, the TMR1
counter is stopped and reinitialized. Software may disable the Timer 1 circuit at any time; however, the TMR1 counter and
PWM outputs will not be disabled until the current PWM cycle completes. Software should monitor the T1C0 bit to determine
when the PWM cycle ends and Timer 1 circuit actually disabled. In Input Capture Mode, the T1C0 bit is one of the TMR1
overflow (a transition from 0xFFF to 0x000) pending flags used to trigger the Timer 1 Circuit’s hardware interrupt if the inter-
rupt is enabled. In order for software to properly monitor the TMR1 overflows, the T1C0 bit must be cleared before the next
TMR1 overflow.
Bit 3 (T1PND) of the T1CNTRL register has two functions depending on Timer 1’s selected operating mode. In either operat-
ing modes, the T1PND bit is one of the Timer 1 Circuit’s hardware interrupt pending flags if the interrupt is enabled. In PWM
Mode, the T1PND bit is triggered by a TMR1 overflow (a transition from the T1RA count to 0x000). However, in Input Cap-
ture Mode, the T1PND bit is triggered by the capture of the current TMR1 value by the rising or falling edge of the T1HS2
(G5) input port. In order for software to properly monitor the pending flag, the T1PND bit must be cleared before the next
TMR1 overflow or capture.
Bit 2 of the T1CNTRL register is the Timer 1’s microcontroller hardware interrupt enable (T1EN) bit. If set, hardware inter-
rupts are enabled and trigger by the T1PND and/or T1C0 pending flags depending on Timer 1’s operating mode.6 If in PWM
Mode, the hardware interrupt is triggered only by the T1PND bit. If in Input Capture Mode, the T1PND and T1C0 bits are log-
ically-ORed together. As long as a Timer 1 pending flag is set, the hardware interrupt will continue to execute software’s Timer
1 interrupt service routine until the pending flag is cleared.7
The SBIT or RBIT instructions may be used to either set or clear one of the T1CNTRL register bits, like the T1EN bit. The
SBIT and RBIT instructions both take two instruction clock cycles to complete their execution. In the first cycle, all register
bits are automatically read to obtain their most current value. In the second cycle, the bit to be set/cleared is given its new value
and all bits are then re-written to the register. Using the SBIT/RBIT instruction to set/clear an enable bit with a pending flag in
the same register may cause a potential hazard. Software may inadvertently clear a recently triggered pending flag if the trigger
happened during the second phase of the SBIT/RBIT instruction execution. To avoid this condition, the LD instruction must be
used to set or clear the interrupt enable bits. The Timer 1 circuit is designed such that software may not trigger a pending flag
by writing a 1 to the T1PND and T1C0 (if in Input Capture Mode) bits, they may only be cleared. The action of writing a 1 to a
T1PND and T1C0 register bits holds the current bit values. The action of writing a 0 to the T1PND and T1C0 register bits
clears the bit values. Therefore, if Timer 1 is configured for a rising edge triggered input capture mode with outputs enabled
and software is to enable interrupts without interrupting the pending flags, the “LD T1CNTRL, #0BDH” instruction should be
used. The T1EN bit will be set to 1 without clearing T1PND and/or T1C0.
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PRODUCT SPECIFICATION
FMS7401/7401L
Table 16. Timer 1 Control (T1CNTRL) Register Bit Definitions
T1CNTRL Register (addr. 0xAE)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
T1C3
T1C2
T1C1
T1C0
T1PND
T1EN
X
T1BOUT
Bit
Description
T1C3
T1C2
T1C1
T1C0
Timer 1 Mode Configuration Bit. Refer to Table 17 for details.
Timer 1 Mode Configuration Bit. Refer to Table 17 for details.
Timer 1 Mode Configuration Bit. Refer to Table 17 for details.
PWM Mode
(0) Stop the PWM Timer 1 circuit.
(1) Start the PWM Timer 1 circuit.
Input Capture Mode
(0) Timer 1’s TMR1 overflow pending flag is cleared.
(1) Timer 1’s TMR1 overflow pending flag is triggered.
T1PND
PWM Mode
(0) Timer 1’s TMR1 overflow pending flag is cleared.
(1) Timer 1’s TMR1 overflow pending flag is triggered.
Input Capture Mode
(0) Timer 1 capture pending flag is cleared.
(1) Timer 1 capture pending flag is triggered.
T1EN
(0) Disables Timer 1 hardware interrupts.
(1) Enables Timer 1 hardware interrupts.
T1BOUT
(0) Retain normal I/O function of the G1/AIN3 pin.
(1) Enables Timer 1’s ADSTROBE output to be sent to the G1 output port.
Table 17. Timer 1 Mode Configuration Bits
T1C3
T1C2
T1C1
Timer Mode Source
PWM mode no output toggle
Interrupt
Timer count on
0
0
0
0
1
0
1
0
1
0
0
1
1
0
0
TMR1 Overflow
TMR1 Overflow
TMR1 Overflow
TMR1 Overflow
Prescaler Input
Prescaler Input
Prescaler Input
Prescaler Input
Prescaler Input
PWM mode T1HS1 and T1HS2 toggle
PWM mode T1HS1 toggle
PWM mode T1HS2 toggle
Capture mode no T1HS1 toggle
TMR1 Overflow
T1HS2 rising-edge
1
1
1
0
1
1
1
0
1
Capture mode with T1HS1 toggle
Capture mode no T1HS1 toggle
Capture mode with T1HS1 toggle
TMR1 Overflow
T1HS2 rising-edge
Prescaler Input
Prescaler Input
Prescaler Input
TMR1 Overflow
T1HS2 falling-edge
TMR1 Overflow
T1HS2 falling-edge
6.2 Pulse Width Modulation (PWM) Mode
In PWM Mode, the Timer 1 circuit may be configured to generate pulses of a specified duty cycle and period on the T1HS1
(G0), T1HS2 (G5), and/or ADSTROBE (G1) timer outputs. The 12-bit TMR1 counter increments at the FT1CLK clock rate
defined by the FSEL bit of the PSCALE register. Refer to the previous PSCALE Register and Timer 1 Clock Configuration
section of the datasheet for details.
A PWM cycle begins with the TMR1 counter incrementing from 0x000 until it matches the value stored in the T1RA register.
At this point, the TMR1 counter completes its T1RA count and overflows (a transitions from T1RA to 0x000) setting the
T1PND flag of the T1CNTRL register ending the PWM cycle. The Timer 1 circuit has two additional TMR1 compare
(T1CMPA and T1CMPB) registers used to generate the T1HS1, T1HS2, and ADSTROBE output signals. All three output
signals are initialized to a resting (off) state. Once the TMR1 counter is enabled (by setting the T1C0 bit of the T1CNTRL
register), both compare registers are matched against the incrementing TMR1 counter. When the TMR1 completes its count
equal to the value stored in the T1CMPA and T1CMPB registers, the T1HS1, T1HS2, and ADSTROBE output signals are set
to an active (on) state until the TMR1 counter matches the value stored in the T1RA compare register (overflows). Once the
TMR1 counter overflows, the output signals are cleared returning them to a resting (off) state. Refer to Figure 11 for a Timer 1
PWM Mode block diagram.
REV. 1.0.2 6/23/04
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FMS7401/7401L
PRODUCT SPECIFICATION
The PWM Timer 1 can be programmed to toggle one or both PWM output signals (T1HS1 and T1HS2) to support a variety of
output configurations (half bridge, full bridge,8 low side or high side driving). These outputs may be used to drive an external
half-bridge driver and are enabled by programming the T1C1 and T1C2 bits in the T1CNTRL register (see Table 16). The
T1HS1 (G0) and T1HS2 (G5) output signals may be configured with opposite phases and dead time controlled edges (see
Figure 12). The phases of the output signals are configured by the bits of the PORTGD I/O configuration register.9 Upon device
power-up, the T1HS1 and T1HS2 signals may be programmed to default as active high/low outputs by the default I/O configu-
ration register bits in the non-volatile Initialization Register 4.10 Both G0/T1HS1 and G5/T1HS2 pins will configure to their
programmed default state after TDIO2 from the system reset trigger (e.g. from a POR). The G0/T1HS1 and G5/T1HS2 pins may
both be configured as outputs with common or opposite phases. If configured as outputs, the PORTGD[0] and PORTGD[5] bits
configure the T1HS1 and T1HS2 signals as active high or low. If the PORTGD bit is 0, the output signal is active high, other-
wise it is active low. The PORTGD[1] bit also configures the G1/ADSTROBE pin as an active high/low signal once configured
as an output. The Initialization Register 4 bits only default the G0/T1HS1 and G5/T1HS2 pins not the G1/ADSTROBE pin.
From factory, the G0/T1HS1, G5/T1HS2 and G1/ADSTROBE device pins are defaulted as tri-stated inputs. The pins must be
configured by the Initialization Register 4 bits or by software directly through the PORTGC and PORTGD register as an output
port before enabling the TMR1 counter and its outputs.
The dead time counter of the Timer 1 circuit controls the dead time (TDT) delay between the T1HS1 and T1HS2 output edge
transitions through the DT[4:0] bits of the DTIME register. The dead time counter delay is first triggered after the TMR1
counter equals to the T1CMPA value and the T1HS1 signal transitions from its resting (off) to its active (on) state. Once the
programmed TDT completes, the T1HS2 signal then transitions from its resting (off) to its active (on) state. The dead time
counter delay is triggered for a second time after the TMR1 counter equals to the T1RA value and the T1HS2 signal transitions
from its active (on) to its resting (off) state. Once the programmed TDT completes, the T1HS1 signal then transitions from its
active (on) to its resting (off) state ending the PWM cycle. The PWM cycle is considered complete once the TMR1 counter
completes the T1RA count plus TDT even in the T1HS1 and T1HS2 outputs are disabled.
The T1HS1 and T1HS2 PWM output signals may be programmed to be automatically disabled by the output of the digital filter
(PWMOFF) in Programmable Comparator circuit. The output may be programmed to disable the Timer 1 circuit completely or
disable only the current PWM cycle. Refer to the Programmable Comparator Circuit section of the datasheet for details.
The Timer 1’s ADSTROBE output signal may be configured as the G1/ADSTROBE device output if the T1BOUT bit of the
T1CNTRL register is set. The ADSTROBE signal, however, is always generated by the Timer 1 circuit. Initially, the
ADSTROBE begins its PWM cycle at its resting (off) state and transitions to its active (on) state once the TMR1 counter com-
pletes its count equal to the T1CMPB value. The active (on) edge transition of the ADSTROBE output may be programmed to
automatically trigger an ADC conversion cycle if the ENDAS bit of the ADCNTRL2 register is set. Refer to the ADC Circuit
section of the datasheet for details.
The T1PND bit of the T1CNTRL register is set once the TMR1 counter completes the count equal to the T1RA value (over-
flows). Software may use the T1PND bit to monitor the PWM cycles and/or trigger microcontroller hardware interrupts
(TMRI1) if the T1EN bit of the T1CNTRL register is set. Software must clear the T1PND bit in order to detect a new overflow
condition and/or trigger a new interrupt.6
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PRODUCT SPECIFICATION
FMS7401/7401L
Figure 11. Timer 1’s PWM Mode Block Diagram
ENDAS
ADSTROBE
TMR1=T1CMPA
TMR1=T1CMPB
T1CMPA
[11:0]
T1CMPB
[11:0]
G1/AIN3
T1BOUT
PWMOFF
12
[11:0]
2
1
T1HS2/G5
T1HS1/G0
FT1CLK
Clock
Fin
Fout
TMR1
Dead Time
Control
DIVIDER
12
[11:0]
PS2 PS1 PS0
T1PND
T1RA
5
PSCALE
DT[4:0]
1
5
0
DTIME
PORTGD
Figure 12. Example PWM Output Signals a) and b)
a)
T1HS1
T1HS2
TDT
TDT
TDT
TPWM
b)
0xFFF
T1RA
T1CMPB
T1CMPA
0x00
T1HS1
T1HS2
TDT
TDT
TDT
TDT
ADSTROBE
Sample
&
Hold
Sample
&
Hold
Sample
&
Hold
Sample
&
Hold
ADC
ADC
Conversion
ADC
Conversion
ADC
Conversion
ADC
Conversion
Block
TSMP
TCONV
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FMS7401/7401L
PRODUCT SPECIFICATION
6.3 Input Capture Mode
When the PWM Timer 1 circuit is configured in Input Capture Mode, the T1HS2 signal is used as an input of the Timer 1
circuit instead of an output as in PWM Mode. The G5/T1HS2 device pin should be configured by software as an input port.
The Timer 1 circuit may be programmed to capture the TMR1 counter value in the T1RA register with every rising or falling
edge transition of the T1HS2 input. With each TMR1 capture, the T1PND bit of the T1CNTRL register is set. For synchroniza-
tion purposes, the T1HS2 input is synchronized with the FT1CLK clock before being allowed to trigger a TMR1 capture. A max-
imum of three FT1CLK cycle TMR1 capture delay will occur with each edge transition on the G5/T1HS2 device pin.
Once the Timer 1 circuit is configured for Input Capture Mode, the TMR1 counter starts incrementing continuously from
0x000 through 0xFFF until the Timer 1 is returned to a disabled PWM operating mode. Once the TMR1 counter overflows
(transitions from 0xFFF to 0x000) the T1C0 pending bit on through T1CNTRL register is set.
In Input Capture Mode, it is still possible to generate output signals with variable duty-cycle thanks to the T1CMPA and
T1CMPB compare registers. If enabled, the T1HS1 and ADSTROBE output signals may be generated as in PWM Mode. Refer
to the previous Pulse Width Modulation (PWM) Mode section of the datasheet for details.
Figure 13. Timer 1’s Input Capture Mode Block Diagram
ENDAS
ADSTROBE
TMR1=T1CMPA
TMR1=T1CMPB
T1C2
T1CMPB
[11:0]
T1CMPA
[11:0]
G1/AIN3
Edge
T1BOUT
G5/T1HS2
Control
12
[11:0]
G0/T1HS1
T1C0
TMR1
FT1CLK
CLOCK
DIVIDER
Fin
Fout
12
[11:0]
1
0
T1PND
PS2 PS1 PS0
T1RA
PSCALE
PORTGD
1. Refer to Table 30 of the Device Memory section of the datasheet for the detailed memory map.
2. Refer to the Electrical Characteristics section of the datasheet.
3. The PLL’s (F(FS=0)) output is not affected by the FS[1:0] bit value of the PSCALE register and merely shares the FS[1:0]=00 divide factor.
4. Refer to the ADC Circuit section of the datasheet for additional details.
5. The three PS bits have no affect on the dead time, only the TMR1 counter.
6. Hardware interrupts are not executed by the microcontroller core unless the Global Interrupt enable (G) flag of the Status register is set. Refer to the 8-Bit Micro-
controller Core section of the datasheet for details.
7. The Timer 1 hardware interrupt will be executed in the defined priority order. Refer to the 8-Bit Microcontroller Core section of the datasheet for details.
8. The full bridge requires two additional output ports to complete the bridge configuration.
9. Refer to the I/O Ports section of the datasheet for additional details.
10.Refer to the Device Memory section of the datasheet for details regarding the initialization registers.
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PRODUCT SPECIFICATION
FMS7401/7401L
7 Timer 0 Circuit
Timer 0’s main circuit is a 12-bit free running up-counter whose clock source is the main system instruction clock (FICLK). The
main counter may be used to generate microcontroller hardware interrupts and serve as a prescaler for the Idle and Watchdog
Timers.
After power-up or any system reset, the Timer 0’s 12-bit counter is initialized to 0x000 and continuously increments with each
instruction clock. The 12-bit counter is not memory mapped; therefore, software cannot read or write to the counter registers.
However, software may monitor the Timer 0’s main counter by reading the state of the Timer 0 Pending (T0PND) bit of the
Timer 0 Control (T0CNTRL) memory mapped register.1 The T0PND flag is automatically set with each counter overflow
(a transition from 0xFFF to 0x000) which occurs after every 4,096 cycles. At every overflow, the counter rolls over to 0x000
and continues to increment. In order for software to properly monitor the main counter, the T0PND bit must be cleared before
the next counter overflow.
The T0CNTRL register houses two hardware interrupt enable bits. The WKINTEN register bit is the MIW hardware interrupt
enable bit. For details regarding its usage refer to the Multi-input Wakeup Circuit section of the datasheet. The T0INTEN
register bit is Timer 0’s microcontroller hardware interrupt (TMRI0) enable bit. If set, hardware interrupts are enabled and
trigger by the T0PND flag.2 As long as a Timer 0 pending flag is set, the hardware interrupt will continue to execute software’s
Timer 0 interrupt service routine until the pending flag is cleared.3
The SBIT or RBIT instructions may be used to either set or clear the T0INTEN or WKINTEN bits. The SBIT and RBIT
instructions both take two instruction clock cycles to complete their execution. In the first cycle, all register bits are automati-
cally read to obtain their most current value. In the second cycle, the bit to be set/cleared is given its new value and all bits are
then re-written to the register. Using the SBIT/RBIT instruction to set/clear an enable bit with a pending flag in the same regis-
ter may cause a potential hazard. Software may inadvertently clear a recently triggered pending flag if the trigger happened
during the second phase of the SBIT/RBIT instruction execution. To avoid this condition, the LD instruction must be used to
set or clear the interrupt enable bits. The Timer 0 circuit is designed such that software may not trigger a pending flag by writ-
ing a 1 to a T0PND register bit, it may only be cleared. The action of writing a 1 to a T0PND register bit holds the current bit
value. The action of writing a 0 to a T0PND register bit clears the bit value. Therefore, the “LD T0CNTRL, #083H” instruction
will set both interrupt enable bits without clearing T0PND.
Table 18.Timer 0 Control (T0CNTRL) Register Definitions4
T0CNTRL Register (addr. 0xB6)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WKINTEN
x
x
x
x
x
T0PND
T0INTEN
7.1 Idle Timer
Once the device enters Idle Mode, the microcontroller core and other main circuits are disabled for current conservation. The
Idle Timer will automatically wake the device from Idle Mode, if the MIW has not already done so, after a maximum of 8,192
cycles.5
The Idle Timer is a 1-bit extension of the Timer 0’s main 12-bit up-counter. With each overflow of the main counter, the Idle
Timer extension bit is toggled essentially causing the Idle Timer overflow to occur after 8,192 cycles. Once the Idle Timer
overflow flag is triggered, the device wakes from Idle Mode and starts its instruction execution with the next clock cycle.
The Idle Timer overflow flag cannot be monitored by software. Therefore, in order to maximize the time that the device
remains in Idle Mode software must monitor the T0PND flag. Once the T0PND flag is triggered, software may then issue the
Idle Mode command. Software may also loop on the Idle Mode command to extend the average time the device remains in Idle
Mode, thereby reducing the overall current consumption.
7.2 Watchdog Timer
The Watchdog Timer is used to safely recover the device in the rare event of a processor “runaway condition” by issuing a sys-
tem reset. A Watchdog Timer runs continuously with Timer 0’s main 12-bit up-counter; however, a Watchdog Reset will not
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FMS7401/7401L
PRODUCT SPECIFICATION
issue a system reset unless the feature is enabled by the Watchdog Enable (WDEN) bit of the Initialization Register 1.6 The
WDEN bit can only be set while the device is in programming mode.7 If set, the Watchdog Timer’s system reset ability will
always power-up enabled. Software cannot disable Watchdog Resets. The Watchdog Reset can only be disabled in program-
ming mode by clearing the WDEN bit as long as the memory write protect (WDIS) feature is not enabled.
The Watchdog Timer is a 4-bit extension of the Timer 0’s main 12-bit up-counter. With each overflow of the main counter, the
Watchdog Timer extension bits may increment to a count of 16. If the Watchdog Timer is allowed to increment to the 16th
count, a Watchdog Reset is issued triggering a system reset. The system reset will initialize all device circuits and instruction
execution will restart at the default program counter address (0xC00) after TRESET delay.8
In order to service the Watchdog Timer to prevent a reset, software must write 0x1B to the Watchdog Service Register
(WDSVR) before every 61,440 cycles (the 16th Watchdog Timer count) and not earlier than the first 4,096 cycles (the 1st
Watchdog Timer count) since the last Watchdog Timer service or system reset. Once the Watchdog Timer is serviced, the 4-bit
Watchdog Timer is cleared and then continues to increment. The Watchdog Timer will issue a reset if it is serviced too fre-
quently or not frequently enough where the servicing of the Watchdog Timer is controlled completely by software.
The Watchdog Timer, like Timer 0’s counter, is not memory mapped and cannot be accessed by software. Software must
monitor the Watchdog Timer by keeping a count of the number of T0PND flags since the last service or reset. If software clears
the T0PND flags before the next Timer 0 counter overflow, software may count the number of triggered T0PND flags in order
to determine when to next service the Watchdog Timer. The Watchdog Timer remains operational during Idle Mode; therefore,
software should service the Watchdog Timer prior to entering Idle Mode to prevent false resets.
It is not recommended to service the Watchdog Timer within an interrupt service routine (ISR). For example, the most obvious
place to issue the Watchdog service command seems to be within the Timer 0 ISR since it guarantees the Watchdog Timer ser-
vice to occur within the allowed 4,096-61,440 cycle window. However, this action takes place automatically since the Timer 0
circuit runs independently from the microcontroller program execution without knowledge of the state of the microcontroller
core. If the program execution is stuck in an infinite loop due to some unforeseen circumstances, the TMRI0 hardware interrupt
will still be triggered executing software’s ISR, the Watchdog Timer will then be serviced, and program execution will return to
the infinite loop once the ISR completes. The infinite loop or “runaway condition” will continue undetected defeating the pur-
pose of the Watchdog Reset feature. The ISRs may be used to keep track of the number of cycles since the last Watchdog ser-
vice (e.g. keep a count of the number of T0PND flags triggered). However, the actual Watchdog service command must be
issued within software’s main program code.
Table 19. Watchdog Service Register (WDSVR) Definition
WDSVR (addr. 0xB5)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
1
1
0
1
1
1. Refer to Table 30 of the Device Memory section of the datasheet for the detailed memory map.
2. Hardware interrupts are not executed by the microcontroller core unless the Global Interrupt enable (G) flag of the Status register is set. Refer to the 8-Bit Micro-
controller Core section of the datasheet for details.
3. The Timer 0 hardware interrupt will be executed in the defined priority order. Refer to the 8-Bit Microcontroller Core section of the datasheet for details.
4. After a system reset, the T0CNTRL register is defaulted to 0x00.
5. Refer to the Power Saving Modes section of the datasheet for Idle Mode wakeup conditions.
6. Refer to the Device Memory section of the datasheet for details regarding the Initialization Registers.
7. The FMS7401/7401L must be placed in a special programming mode in order to have full write and read access of all of the device memories. Refer to the In-circuit
Programming Specification section of the datasheet for details.
8. Refer to the Electrical Characteristics section of the datasheet for details.
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PRODUCT SPECIFICATION
FMS7401/7401L
8 I/O Ports
The eight I/O pins (six on the 8-pin package option) are bi-directional (see Figure 14). The bi-directional I/O pins can be indi-
vidually configured by software to operate as high-impedance inputs, as inputs with weak pull-up, or as push-pull outputs. The
operating state is determined by the contents of the corresponding bits in the data and configuration registers. Each bi-direc-
tional I/O pin can be used for general purpose I/O, or in some cases, for a specific alternate function determined by the on-chip
hardware.
The high voltage FMS7401 device’s G0/T1HS1 and G5/T1HS2 output port levels can be as high as the Vdd supply voltage if
powered from the Vdd pin, (see Figure 15). The FMS7401L device’s G0/T1HS1 and G5/T1HS2 output port levels can be only
as high as the Vcc supply voltage since it is a low voltage device. All the other output ports for both the low and high voltage
devices are supplied by the Vcc pin (see Figure 15).
Figure 14. PORTGD Logic Diagram
GXPULLEN
GXBUFEN
GXOUT
GXIN
GX
Figure 15. Output Port Configurations
VDD
VDD
Voltage
Voltage
Regulator
(3.3V)
Regulator
(3.3V)
VCC
VCC
ACE
CORE
ACE
Outputs
CORE
Outputs
G1, G2, G3
G4, G6 & G7
T1HS1/G0
&
T1HS2/G5
For the FMS7401L device, VDD and VCC are internally connected.
8.1 I/O Registers
The I/O pins (G0–G7) have three memory mapped port registers associated with the I/O circuitry: a Port Configuration
(PORTGC), Port Data (PORTGD) and Port Input (PORTGP) register.1 PORTGC is used to configure the pins as inputs or out-
puts. A pin may be configured as an input by writing a 0 or as an output by writing a 1 to its corresponding PORTGC bit. If a
pin is configured as an output, its PORTGD bit represents the state of the pin (1 = logic high, 0 = logic low). If the pin is con-
figured as an input, its PORTGD bit selects whether the pin is a weak pull-up or a high-impedance input. Table 20 provides
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FMS7401/7401L
PRODUCT SPECIFICATION
details of the port configuration options. The port configuration and data registers can both be read from or written to. Reading
PORTGP returns the value of the port pins regardless of how the pins are configured. Since this device supports MIW, all input
ports have Schmitt triggers.
Upon power-up, the PORTGC and PORTGD registers are initialized to 0x00. However, the G0/T1HS1 and G5/T1HS2 pins
may be defaulted to the different I/O configurations defined by the default I/O configuration bits of the Initialization Register 4.
Refer to Table 29 in the Device Memory section of the datasheet for details.
Table 20. I/O Register Bit Assignments
PORTGC, PORTGD, PORTGD Registers (addr. 0xB3, 0xB2, 0xB4)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
G72
G62
G53
G4
G3
G2
G1
G03
Table 21. I/O Configuration Options
Port Pin Configuration
High-impedance input (tri-state input)
Input with pull-up (weak one input)
Push-pull zero output
PORTGC Bit
PORTGD Bit
0
0
1
1
0
1
0
1
Push-pull one output
1. Refer to Table 30 of the Device Memory section of the datasheet for the detailed memory map.
2. Available only on the 14-pin package option.
3. The G0/T1HS1 and G5/T1HS2 pins on the FMS7401 have special high voltage outputs. Refer to Figure 15 for details.
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PRODUCT SPECIFICATION
FMS7401/7401L
9 Multi-input Wakeup Circuit
The Multi-input Wakeup (MIW) circuit may be used to wake the device from either Halt or Idle Mode1 with an external event,
generate flags for software monitoring and microcontroller hardware interrupts by any one or all I/O ports (G0–G7). The MIW
circuit is configured using the Wakeup Enable (WKEN), Wakeup Edge (WKEDG), Wakeup Pending (WKPND) and
T0CNTRL memory mapped registers.2 The WKEN, WKEDG and WKPND are 8-bit registers where each bit corresponds to
an I/O port pin (see Table 21). All four registers are initialized to 0x00 upon a system reset.
The PWMOFF output signal may also be programmed as an input of the G6 port MIW circuit. Interrupts may be triggered if
the PWMOFF/G6 input MIW circuit is enabled and configured to trigger its microcontroller hardware interrupt (EDGEI).
Bit 6 (PWMINT) of the DDELAY register, if set to 1, selects the PWMOFF signal in place of its G6 input to the MIW circuit.
Software must then enable the MIW PWMOFF/G6 circuit by setting the WKEN[6] bit. The WKEDG[6] bit must also be
cleared to select the rising edge transitions on the PWMOFF signal as its WKPND[6] bit trigger. Software may monitor the
WKPND[6] flag or enable the MIW hardware interrupt (EDGEI) to help detect when the PWMOFF signal is triggered. Refer
to the Programmable Comparator Circuit sections of the datasheet for addition details.
9.1 MIW Configuration Registers
The Wakeup Enable (WKEN) register individually enables an I/O port’s edge transition to trigger a wakeup/interrupt pending
flag. If the WKEN register bit is 1, the corresponding I/O port’s MIW circuitry (defined by its bit number) is enabled; other-
wise, the port circuitry remains disabled and the pending flag may not be triggered.
The Wakeup Edge (WKEDG) register bits are used to program an enabled I/O port’s pending flag to be triggered from either a
rising-/falling-edge transition. If the WKEDG register bit is 1, a falling-edge transition of the enabled I/O port will trigger the
pending flag. If zero, a rising-edge transition of the enabled I/O port will trigger the pending flag.
The MIW circuit shares a single hardware interrupt (EDGEI) among all pending flags and is enabled by the Wakeup Interrupt
enable (WKINTEN) bit of the T0CNTRL register.2 The WKINTEN bit enables hardware interrupts for the MIW circuit if set
to 1.3
The Wakeup Pending (WKPND) register contains the pending flags corresponding to each of the I/O port pins. If a WKPND
register bit is 1, the programmed I/O port edge transition has triggered its pending flag. If zero, the flag is not pending and no
transition has occurred from the last pending reset. A pending flag may only be triggered by enabled I/O ports (if its WKEN
register bit is 1). Once a pending flag is triggered, all flags are logically-ORed together to trigger a WAKEOUT if in Halt/Idle
Mode and/or hardware interrupts (if enabled). If software is to re-enter Halt/Idle Mode, all pending flags must be cleared, oth-
erwise the command is ignored. Since all MIW pending flags share a single hardware interrupt, software must take care with
the handling of the pending flags when more than one pending flag is enabled. As long as a MIW pending flag is set, the hard-
ware interrupt will continue to execute software’s MIW interrupt service routine with highest priority until all pending flags are
cleared.4
Upon exiting Halt/Idle Mode or before leaving software’s MIW interrupt service routine, the RBIT instruction may be used to
clear a particular pending flag. The RBIT instruction takes two instruction clock cycles to complete its execution. In the first
cycle, all eight register bits are automatically read to obtain their most current value. In the second cycle, the bit to be cleared is
given its new value and all bits are then re-written to the register. Using the RBIT instruction to clear an individual pending flag
causes no potential hazards if only one wakeup I/O port is enabled. However, if more than one I/O port is enabled software
may inadvertently clear a recently triggered pending flag if the trigger happened during the second phase of the RBIT instruc-
tion execution. To avoid this condition, the LD instruction must be used to clear a set pending flag. The MIW circuit is
designed such that software may not trigger a pending flag by writing a 1 to a WKPND register bit, it may only be cleared. The
action of writing a 1 to a WKPND register bit holds the current bit value. The action of writing a 0 to a WKPND register bit
clears the bit value. Therefore, the “LD WKPND, #0F7H” instruction will clear the WKPND[3] while all others bits remain the
same.
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FMS7401/7401L
PRODUCT SPECIFICATION
The MIW circuit can be used with the I/O ports configured as both an input and output. The MIW configuration and function is
the same for both I/O configurations. However, when using the MIW circuit to wake the device from Halt/Idle Mode the
wakeup I/O port must be configured as an input, otherwise the device will never exit the mode.
Table 22. Multi-input Wakeup (MIW) Register Bit Assignments
WKEN, WKEDG, WKPND Registers (addr. 0xB1, 0xAF, 0xB0)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
G75
PWMOFF6/G65
G5
G4
G3
G2
G1
G0
Figure 16. Multi-input Wakeup (MIW) Block Diagram6
Data Bus
7
0
WKEN[7:0]
7
G7
B
A
PWMOFF
G6
WAKEOUT
EDGEI
Y
Sel
0
G0
WKINTEN
PWMINT
WKPND[7:0]
WKEDG[7:0]
1. Refer to the Power Saving Modes section of the datasheet for detail regarding Halt and Idle Mode.
2. Refer to Table 30 of the Device Memory section of the datasheet for the detailed memory map.
3. Hardware interrupts are not executed by the microcontroller core unless the Global Interrupt enable (G) flag of the Status register is set. Refer to the 8-Bit
Microcontroller Core section of the datasheet for details.
4. No other hardware interrupts will be executed, aside from the software interrupt instruction, until the MIW hardware interrupt is no longer executed. Refer to the
8-Bit Microcontroller Core section of the datasheet for details.
5. Available only on the 14-pin package option.
6. The PWMOFF and PWMINT signals are the outputs from the Programmable Comparator’s Digital Filter circuit. Refer to Programmable Comparator Circuitsection
of the datasheet for details.
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PRODUCT SPECIFICATION
FMS7401/7401L
10 8-Bit Microcontroller Core
The FMS7401/7401L’s 8-bit microcontroller core is specifically designed for low cost applications involving bit manipulation,
shifting and block encryption. It is based on a modified Harvard architecture meaning peripheral, I/O and RAM locations are
addressed separately from instruction data.
The core differs from the traditional Harvard architecture by aligning the data and instruction memory sequentially. This
allows the X-pointer (11-bits) to point to any memory location in either segment of the memory map. This modification
improves the overall code efficiency of the microcontroller core and takes advantage of the flexibility found on the von Neu-
mann architecture and stored program concept.
10.1 Core Registers
The microcontroller core has five general-purpose registers. These registers are the Accumulator (A), X-Pointer (X), Program
Counter (PC), Stack Pointer (SP) and Status Register (SR). The X, SP and SR registers are memory mapped while A and PC
are not.
Figure 17. Core Program Model
A
7
0
0
0
0
8-bit accumulator register
11-bit X pointer register
10-bit program counter
4-bit stack pointer
X
10
PC
SP
SR
9
3
R 0 0 G Z C H N
8-bit status register
NEGATIVE flag
HALF CARRY flag
CARRY flag
ZERO flag
GLOBAL INTERRUPT enable
READY flag
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PRODUCT SPECIFICATION
10.1.1 Accumulator (A)
The Accumulator is a general-purpose 8-bit register that is used to hold data and results of arithmetic calculations or data
manipulations.
10.1.2 X-Pointer (X)
The X-Pointer register allows for an 11-bit indexing value to be added to an 8-bit offset creating an effective address used for
reading and writing among the memory space. This provides software with the flexibility of storing lookup tables in the code
EEPROM memory space for the core’s accessibility during normal operation.1
The microcontroller core allows software to access the entire 11-bit X-Pointer register using the special X-pointer instructions
e.g. LD X, #040H (see Table 24). Software may also access the register through any of the memory mapped instructions using
the XHI (X[10:8]) and XLO (X[7:0]) variables located at address 0xBE and 0xBF (see Table 30).
The X register is divided into two sections. The most significant bit (MSB) is write only and selects between the data
(0x000 to 0x0FF) or program (0xC00 to 0xFFF) memory space. The 10 least significant bits (LSBs) represent the specific
address location within the data or program memory space.
For example: If X[10] = 0, the LD A, [#0,X] instruction will take the data at address X[9:0] from the data memory space
(0x000 to 0x0FF) and load it into A. However, if X[10] = 1 the LD A, [#0,X] instruction will take the data at address X[9:0]
from the program memory space (0xC00 to 0xFFF) and load it into A.
The X register can also serve as a counter or temporary storage register. However, this is true only for the 10-LSBs since the
MSB is dedicated for memory space selection.
10.1.3 Program Counter (PC)
The 10-bit Program Counter (PC) register contains the address of the next instruction to be executed. After a system reset,
PC is initialized to 0xC00 and the microcontroller core begins executing the instruction program residing in the code EEPROM
memory at the initialized PC value.
10.1.4 Stack Pointer (SP)
The microcontroller core has an automatic program stack with a 4-bit stack pointer. The stack can be initialized to any location
between addresses 0x30-0x3F in SRAM. Normally, the stack pointer is initialized by one of the first instructions in an applica-
tion program. After a reset, the stack pointer is defaulted to 0xF pointing to the top of the stack at address 0x3F.
The stack is configured as a data structure which decrements from high to low memory. Each time a new address is pushed
onto the stack, the microcontroller core decrements the stack pointer by two. Each time an address is pulled from the stack, the
microcontroller core increments the stack pointer is by two. At any given time, the stack pointer points to the next free location
in the stack.
When a subroutine is called by a jump-to-subroutine (JSR) instruction, the instruction’s address is automatically pushed onto
the stack with the least significant byte first. When the subroutine is finished, a return-from-subroutine (RET) instruction is
executed. The RET instruction pulls the previously stacked return address and loads it into the program counter. Instruction
execution then continues at the pulled return address.
10.1.5 Status Register (SR)
The 8-bit Status Register (SR) contains four condition code indicators (C, H, Z, and N), a global interrupt (G) mask bit, and the
data EEPROM write ready (R) flag. The condition codes are automatically updated by most instructions (see Table 25). All sta-
tus register bits except for the global interrupt mask are read only when using direct, indirect, or indexed instructions. The carry
and half carry bits may be written by using their special inherent (SC, RC, LDC, RRC and RLC) instructions. Software cannot
restore SR using the traditional microcontroller methods. Refer to the Interrupt Handling section for additional details.
48
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PRODUCT SPECIFICATION
Carry/Borrow (C)
FMS7401/7401L
The carry flag is set if the arithmetic logic unit (ALU) performs a carry or borrows during an arithmetic operation and by its
special inherent instructions—set carry (SC), load carry (LDC) and invert carry (INVC). The rotate instructions—rotate right/
left through carry (RRC/RLC)—operate with and through the carry bit to facilitate multiple-word shift operations. The RC,
SC, INVC, LDC and STC (store carry) instructions facilitate direct bit manipulation using the carry flag.
Half Carry (H)
The half carry flag indicates whether an overflow has taken place on the boundary between the two nibbles in the accumulator.
It is primarily used for Binary Coded Decimal (BCD) arithmetic calculation. The RC and SC instructions facilitate direct bit
manipulation of the half carry flag.
Zero (Z)
The zero flag is set if the result of an arithmetic, logic, or data manipulation operation is zero. Otherwise, the zero flag is
cleared.
Negative (N)
The result from an arithmetic, logic, or data manipulation operation is negative if the MSB is one, therefore setting the negative
flag. Otherwise, the negative flag is cleared.
Global Interrupt Mask (G)
The global interrupt bit (G) is a global mask that disables all maskable interrupt sources. If G is cleared, interrupts can become
pending but the operation of the core continues uninterrupted (even if the individual interrupts are enabled). However, if G is
set when an interrupt becomes pending the core will be interrupted and execute the appropriate interrupt service routine.
After a reset, G is defaulted to zero and can only be set by a software instruction. When an interrupt is recognized, G is auto-
matically cleared after the program counter value is stacked and the interrupt vector addressing the interrupt service routine is
fetched. Once the interrupt is serviced, a return-from-interrupt (RETI) instruction is normally executed to restore the program
counter to the value before the interrupt occurred. G is the restored to one after the return from interrupt is executed. Although
G can be set within an interrupt service routine, “nesting” interrupts in this way should only be done when there is a clear
understanding of latency and of the arbitration mechanism.
Table 23. Interrupt Priority Sequence
Priority (5 highest, 1 lowest)
Interrupt
5
4
3
2
1
Software
MIW
(INTR)
(EDGEI)
(TMRI0)
(TMRI1)
(ADCI)
Timer 0
PWM Timer 1
ADC
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PRODUCT SPECIFICATION
FMS7401/7401L
10.1.6 Interrupt Handling
When an interrupt is recognized, the current instruction completes its execution. The return address (the current value in the
program counter, PC) is pushed onto the stack, the global interrupt (G) mask of the status register (SR) is cleared, and execu-
tion continues at the address specified by the respective interrupt vector (see Table 30). This process takes five instruction
cycles to complete. The interrupt vector contains the address of the software’s interrupt service routine (ISR). Initially, the ISR
may save (if necessary) the status register’s contents. Software, however, cannot restore SR using the traditional microcontrol-
ler methods. Just before ending the ISR, software may restore the contents of SR by using only the special inherent instructions
(e.g. SC, RC and LDC) or specially defined software routines since all SR bits except for G are read only when using direct,
indirect, or indexed instructions (e.g. LD , ST, RBIT or SBIT). Upon exiting the ISR, software must clear the appropriate
triggering pending flag and execute a return-from-interrupt (RETI) instruction. The RETI instruction pulls the saved return
address off the stack in reverse order restoring PC and setting G of SR to one. Instruction execution resumes at the restored the
program counter address.
The microcontroller core is capable of supporting five interrupts. Four are maskable through G of the SR and the fifth (software
interrupt) is not inhibited by G (see Figure 18). The execution of the INTR instruction generates a software interrupt. Once the
INTR instruction is executed, the microcontroller core will interrupt whether G is set or not. The INTR interrupt is executed in
the same manner as the other maskable interrupts where PC is stacked and G is cleared. This means, if G was enabled prior to
the software interrupt the RETI instruction must be used to return from interrupt in order to restore G to one. However, if G
was not enabled prior to the software interrupt the RET instruction must be used.
In the case of simultaneous multiple interrupts, the microcontroller core prioritizes the interrupts. See Table 23 for the interrupt
service priority sequence.
Figure 18. Basic Interrupt Structure
INTR
PWM T1
T0
T1PND
T0PND
WKPND
APND
Interrupt
MIW
ADC
G
Interrupt
Pending
Flags
Global Interrupt
Enable
T0INT
EN
WKINT
EN
AINT
EN
T1EN
Interrupt Enable Bits
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PRODUCT SPECIFICATION
FMS7401/7401L
10.2 Addressing Modes
The microcontroller core has seven instruction addressing modes: inherent, immediate, direct, indirect, indexed, absolute jump
and relative jump (see Table 24).
Inherent
The inherent addressing mode instructions either have no operand associated or the contents of the operand are already known
to the microcontroller core. The microcontroller core then inherently knows how to execute the instruction without needing
any additional information provided by additional operands.
Immediate
The immediate addressing mode instructions contain a 3-bit,2 8-bit or 12-bit3 immediate field as an operand. Immediate
addressing is so-named because the value needed to complete the instruction is provided immediately to the core within the
instruction code. That is to say, the instruction itself dictates what the data value is to be e.g. stored in a register.
Direct
The direct addressing mode instructions contain an 8-bit address operand that directly points to a location within the data
memory space. Direct addressing is so-named because the value needed to complete the instruction must be directly accessed
by the core from the memory address provided by the instruction code.
Indirect
The indirect addressing mode instructions use the content in XLO, X[7:0], to address a specific location within the data mem-
ory space (0x00 – 0xFF).4 Indirect addressing is so-named because the value needed to complete the instruction must be
retrieved indirectly by the core from the address provided by the X-pointer.
Indexed
The indexed offset addressing mode instructions add an 8-bit unsigned offset value to the X-pointer yielding a new effective
address to select a specific location anywhere within the memory map (both program and data memory space, 0x000-0xFFF).
Indexed addressing expands the functions of indirect addressing by providing the only means to access the data stored within
the program memory space.
Absolute
The absolute jump addressing mode instructions (e.g. JMP and JSR) replace the program counter with the value in the operand
field. This allows jumping to any location within the program memory space.5
Relative
The opcode instruction field for the relative jump addressing mode instruction, JP, is calculated from the distance to the abso-
lute program memory location in the operand addressing the next instruction to be executed. The base opcode for JP is 0xC0
where bit 5 indicates the direction within memory to jump. Bits 4 to 0 indicate the number of bytes to jump where the maxi-
mum distance is 31 bytes. If bit 5 is zero, the address for the next instruction executed is determined by subtracting the lower 5
bits of the opcode (0xC1-0xDF) from the program counter; otherwise, the lower 5 bits of the opcode (0xE0-0xFF) are added to
the program counter.6
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FMS7401/7401L
PRODUCT SPECIFICATION
Table 24. Instruction Addressing Modes
Instruction
Immediate
Direct
Indexed
Indirect
Inherent
Relative
Absolute
ADC
ADD
AND
OR
SUBC
XOR
A, #
A, #
A, #
A, #
A, #
A, #
A, M
A, M
A, M
A, M
A, M
A, M
A, [#, X]
A, [#, X]
A, [#, X]
A, [#, X]
A, [#, X]
A, [#, X]
A, [X]
A, [X]
A, [X]
A, [X]
A, [X]
A, [X]
CLR
INC
DEC
M
M
M
A
A
A
X
X
X
IFEQ
IFGT
IFNE
IFLT
A, #
A, #
A, #
X, #
X, #
X, #
X, #
M, #
M, #
A, M
A, M
A, M
A, [#, X]
A, [#, X]
A, [#, X]
A, [X]
A, [X]
A, [X]
SC
RC
IFC
IFNC
INVC
LDC
STC
no-op
no-op
no-op
no-op
no-op
#, M
#, M
RLC
RRC
M
M
A
A
LD
ST
A, #
X, #
M, #
A, M
A, M
M, M
A, [#, X]
A, [#, X]
A, [X]
A, [X]
NOP
no-op
IFBIT
IFNBIT
SBIT
#, A
#, A
#, M
#, [X]
#, [X]
#, [X]
#, [X]
#, M
#, M
#, M
RBIT
JP
Rel.
JSR
JMP
RET
RETI
INTR
[#, X]
[#, X]
M
M
no-op
no-op
no-op
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PRODUCT SPECIFICATION
FMS7401/7401L
Table 25. Instruction Cycles and Bytes
Flags
Flags
Mnemonic
ADC
ADC
ADC
ADC
ADD
ADD
ADD
ADD
AND
AND
AND
AND
CLR
Operand
A, [X]
A, [#,X]
A, M
A, #
Bytes
1
2
2
2
1
2
2
2
1
2
2
2
1
1
2
1
1
2
1
2
1
1
2
1
2
2
3
3
2
1
2
2
3
3
1
2
1
1
2
1
2
2
3
3
1
2
Cycles
1
affected
Mnemonic
INC
Operand
Bytes
1
1
1
3
2
1
3
2
2
2
1
2
3
3
3
2
1
1
2
2
2
1
2
1
1
1
1
2
1
2
1
2
1
2
1
2
2
1
2
2
2
1
2
2
2
Cycles
1
affected
C,H,Z,N
C,H,Z,N
C,H,Z,N
C,H,Z,N
Z,N
X
Z
None
C
3
INTR
INVC
JMP
JMP
JP
5
2
1
2
M
4
None
None
None
None
None
None
None
None
None
None
None
None
C
A, [X]
A, [#,X]
A, M
A, #
1
[#, X]
3
3
Z,N
1
2
Z,N
JSR
JSR
LD
M
[#, X]
A, #
5
2
Z,N
5
A, [X]
A, [#,X]
A, M
A, #
1
Z,N
2
3
Z,N
LD
A, [#,X]
A, [X]
A, M
M, #
3
2
Z,N
LD
1
2
Z,N
LD
2
X
1
Z
LD
3
CLR
A
1
C,H,Z,N
C,H,Z,N
Z
LD
M, M
X, #
3
CLR
M
1
LD
3
DEC
DEC
DEC
IFBIT
IFBIT
IFBIT
IFC
X
1
LDC
NOP
OR
#, M
2
A
1
Z,N
1
None
Z, N
M
2
Z,N
A, [X]
A, [#,X]
A, M
1
#, A
1
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
Z,N
OR
3
Z,N
#, M
#, [X]
2
OR
2
Z,N
1
OR
A, #
2
Z,N
1
RBIT
RBIT
RC
#, [X]
#, M
2
Z,N
IFEQ
IFEQ
IFEQ
IFEQ
IFEQ
IFEQ
IFGT
IFGT
IFGT
IFGT
IFGT
IFLT
A, [#, X]
A, [X]
A, #
3
2
Z,N
1
1
C,H
2
RET
RETI
RLC
RLC
RRC
RRC
SBIT
SBIT
SC
5
None
None
C,Z,N
C,Z,N
C,Z,N
C,Z,N
Z,N
A, M
M, #
2
5
3
A
M
1
X, #
3
2
A, [#, X]
A, [X]
A, #
3
A
1
1
M
2
2
#, [X]
#, M
2
A, M
X, #
2
2
Z,N
3
1
C,H
X, #
3
ST
A, [#,X]
A, [X]
A, M
3
None
None
None
Z,N
IFNBIT
IFNBIT
IFNBIT
IFNC
IFNE
IFNE
IFNE
IFNE
IFNE
IFNE
INC
#, A
1
ST
1
#, M
2
ST
2
#, [X]
1
STC
SUBC
SUBC
SUBC
SUBC
XOR
XOR
XOR
XOR
#, M
2
1
A, [X]
A, [#,X]
A, M
1
C,H,Z,N
C,H,Z,N
C,H,Z,N
C,H,Z,N
Z,N
A, [#, X]
A, [X]
A, #
A, M
X, #
M, #
A
3
3
1
2
2
A, #
2
2
A, [X]
A, [#,X]
A, M
1
3
3
Z,N
3
2
Z,N
1
A, #
2
Z,N
INC
M
2
Z,N
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53
FMS7401/7401L
PRODUCT SPECIFICATION
1. The FMS7401/7401L’s normal mode operation begins after a system reset and is when the 8-bit microcontroller core begins executing the instruction program
residing in the code EEPROM memory. During this time, the code EEPROM memory may only be read by software not written. Refer to the Device Memorysection
of the datasheet for additional memory addressing information.
2. A 3-bit value in cases like the IFBIT and IFNBIT instructions.
3. A 12-bit value in the case of instructions writing to X.
4. The content of XHI (X[10:8]) is ignored.
5. The program memory space for the FMS7401/7401L is 0xC00 to 0xFFF; however, the program counter will use only the 10 least significant bits of the address
provided.
6. Although the JP instruction can jump forward 31 bytes, it can only jump backwards 30 bytes because the program counter is automatically incremented while the
JP instruction is being executed.
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PRODUCT SPECIFICATION
FMS7401/7401L
11 Device Memory
The FMS7401/7401L has 64 bytes of SRAM and 64 bytes of EEPROM (data EEPROM) available for data storage. It also has 1K
Byte of EEPROM (code EEPROM) memory for program storage. During the device’s normal operation, software has both read and
write access of SRAM and data EEPROM memories but has only read access of the code EEPROM.1 That is, the code EEPROM is
protected from unauthorized writes that can corrupt its contents during normal operating conditions. The code EEPROM can only be
written to when the device is in programming mode2 and if the write disable (WDIS) bit of Initialization Register 1 is set to 0
While in normal operating mode, the user can write to the data EEPROM array by polling the ready (R) flag of the status register then
executing the appropriate instruction. If the R flag is 1, the data EEPROM block is ready to perform the next write. If the R flag is 0,
the data EEPROM is busy performing a write operation. The data EEPROM array will set the R flag to 1 after completing the write
operation. Attempts to read, write, or enter Halt/Idle Mode while the data EEPROM is busy (R=0) can affect the current data being
written and cause the intruding read or write command to also fail.
The SRAM, data EEPROM, code EEPROM, and all other data register are memory mapped for easy access by software (see
Table 30). The microcontroller core has an 11-bit X-pointer register that may be used to address data bytes within the memory
map.3 Bit 10 of the X-pointer (X[10] or XHI[1]) selects between the code and data memory space within the memory map.
When X[10] is set to 1, the X-pointer selects the code memory space (addr. 0xC00 to 0xFFF) physically addresses a byte in the
code EEPROM memory. Since the code EEPROM memory is 1K bytes, it requires only 10 address bits to physically address a
byte of its memory. Bits 9-0 of the X-pointer (X[9:0] or {XHI[1:0],XLO[7:0]}) is the physical address of the code EEPROM
used during a byte read instruction operation. When X[10] is set to 0, the X-pointer automatically addresses the data memory
space (addr. 0x00 to 0xFF). Bits 9-0 of the X-pointer is the memory mapped (not physical) address for the entire data memory
space (including the SRAM, data EEPROM, and all other data registers) used during a byte read/write instruction operation. In
addition, when using X-pointer instructions with the "[X]" syntax, only the lower 8 bits of X are considered addressing the data
memory space only. However, instructions with the "[#0,X]" syntax allow read access of the code memory space for look-up
tables, etc. When using the X-pointer to address a byte in either the data or code memory space, software should load X with
its 12-bit memory mapped address.
11.1 Initialization Registers
The FMS7401/7401L has four 8-bit wide non-volatile initialization registers that are only accessible by the user in program-
ming mode (if the memory security bits are not enabled). Each register has a corresponding shadow volatile register that is
automatically updated during a reset and is used to initialize specific on-chip peripherals.
The Initialization Register 1 contains the three memory security bits, three feature enable bits, and the clock selection bit. Table
26 provides a detailed description of the Initialization Register 1. This register is defaulted to zero by the factory.
The Initialization Register 2 contains the internal oscillator frequency trim setting, FOSC.4 Prior to leaving the factory, the inter-
nal oscillator is trimmed to the appropriate frequency and the non-volatile register is pre-programmed. During a reset, the vol-
atile shadow register (at address 0xBA) is updated with the factory programmed trim value. The shadow register associated
with the Initialization Register 2 is accessibly by software during normal operation and may be written to in order to perform
fine adjustments e.g. of the PWM timer outputs. If the software saved the original factory trim value, the software may restore
the frequency to its original frequency.5
The Initialization Register 3 contains the factory calibration values for the two internal analog comparator circuits (Brown-out
Reset and Programmable Comparator). The calibration is performed in order to configure the comparators to their proper lev-
els (see Table 27). The non-volatile register is preprogrammed prior to leaving the factory.
The Initialization Register 4 contains the factory calibration value for the internal current source generator as well as the
default G0/T1HS1 and G5/T1HS2 port configuration. The factory calibrates the current source generator to ensure that, if
enabled, G3 can source ISRC4 of current. During the initial clock cycles of the reset sequence, the shadow register is updated
configuring the G0/T1HS1 and G5/T1HS2 I/O ports to their pre-determined initial states. This offers the capability of driving
G0/T1HS1 and G5/T1HS2 high within the first TDIO4 after the device is powered. The non-volatile register is pre-programmed
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55
FMS7401/7401L
PRODUCT SPECIFICATION
prior to leaving the factory with the appropriate calibration value and with the ports configured as tri-state inputs. In program-
ming mode, the default port configuration may be changed; however, be sure to maintain the factory current source calibration
value since writes to a single register must affect all bits.
The Initialization Registers 1, 2, 3 and 4 can be read from and written to while in programming mode. However, re-trimming
the internal oscillator and re-calibrating the analog circuits once the device has left the factory is discouraged and will void all
device guarantees.
Table 26. Initialization Register 1 Bit Definitions
Initialization Register 1 (volatile/non-volatile addr. 0xB9, 0xBB)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
WDIS6
Bit 0
RDIS6
CLK_ADJ
CMODE
unused
WDEN
BOREN
UBD
(7)
CLKADJ
When set, the internal clock trimming register (volatile Initialization Register 2, Addr. 0xBA) can be
accessed by the core in order to modify the internal clock frequency.
(6)
(4)
(3)
(2)
CMODE
WDEN
BOREN
UBD
Clock mode select: 0 = Internal Oscillator, 1 = External Oscillator
If set, the on-chip processor Watchdog Timer resets are enabled.
If set, the on-chip Brown-out Reset comparator circuit is enabled.
If set, write access of the upper 32 bytes of the data EEPROM (0x60-0x7F) is disabled in both
programming and normal mode.1,2
(1)
(0)
WDIS6
RDIS6
If set, write access of the device memory is permanently disabled while in programming mode.2
If set, read access of the device memory is permanently disabled while in programming mode.2
Table 27. Initialization Register 3 Bit Definitions
Initialization Register 3 (volatile/non-volatile addr. 0xD0, 0xD1)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
unused
unused
BOR_TRIM
COMP_TRIM
(5:3)
(2:0)
BOR_TRIM
These three bits allow for the calibration of the Brown-out Reset comparator circuit.
These three bits allow for the calibration of the Programmable Comparator’s upper range circuit.
COMP_TRIM
Table 28. Initialization Register 4 Bit Definitions
Initialization Register 4 (volatile/non-volatile addr. 0xD3, 0xD4)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
T1HS_DIR
T1HS2_LEV
T1HS1_LEV
ISOURCE_TRIM[4:0]
(7)
T1HS_DIR
T1HSx_LEV
Initializes during reset, the T1HS1 (G0) and T1HS2 (G5) I/O ports both either inputs or outputs.
This bit shadows directly to bits 0 and 5 of PORTGC.
(6:5)
(4:0)
Initializes during reset, the individual T1HS1 (G0) and T1HS2 (G5) I/O port level. These bits
shadow directly to bits 0 and 5 of PORTGD.
ISOURCE_TRIM
These five bits allow for the calibration of internal current source generator.
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PRODUCT SPECIFICATION
FMS7401/7401L
Table 29. T1HS1 (G0) and T1HS2 (G5) Default Configuration
T1HS_DIR
T1HS2_LEV
T1HS1_LEV
Description
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
T1HS1 and T1HS2 tri-state inputs
T1HS1 input with pull-up, T1HS2 input tri-state
T1HS1 input tri-state, T1HS2 input with pull-up
T1HS1 and T1HS2 input with pull-up
T1HS1 and T1HS2 push-pull 0 outputs
T1HS1 push-pull 1 output, T1HS2 push-pull 0 output
T1HS1 push-pull 0 output, T1HS2 push-pull 1 output
T1HS1 and T1HS2 push-pull 1 outputs
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FMS7401/7401L
PRODUCT SPECIFICATION
11.2 Memory Map
All I/O ports, peripheral registers, and core registers (except the accumulator and the program counter) are mapped into the
memory space.
Table 30. Memory Mapped Registers
Address
0x00 – 0x3F
0x40 – 0x7F
0x9D
Memory Space
Data
Block
Contents
SRAM
EEPROM
ADC
Data RAM
Data
Data EEPROM
Data
ADATA register7
ADCNTRL1 register
ADCNTRL2 register
DDELAY register
PSCALE register
DTIME register
0x9F
Data
ADC
0xA0
Data
ADC
0xA2
Data
Prog. Comparator
PWM Timer 1
PWM Timer 1
PWM Timer 1
PWM Timer 1
PWM Timer 1
PWM Timer 1
PWM Timer 1
PWM Timer 1
PWM Timer 1
PWM Timer 1
PWM Timer 1
MIW
0xA4
Data
0xA5
Data
0xA6
Data
T1CMPALO register
T1CMPAHI register
T1CMPBLO register
T1CMPBHI register
T1RALO register
T1RAHI register
TMR1LO register7
TMR1HI register7
T1CNTRL register
WKEDG register
WKPND register
WKEN register
0xA7
Data
0xA8
Data
0xA9
Data
0xAA
Data
0xAB
Data
0xAC
Data
0xAD
Data
0xAE
Data
0xAF
Data
0xB0
Data
MIW
0xB1
Data
MIW
0xB2
Data
I/O
PORTGD register
PORTGC register
PORTGP register7
WDSVR
0xB3
Data
I/O
0xB4
Data
I/O
0xB5
Data
Timer 0
0xB6
Data
Timer 0
T0CNTRL register
0xB7
Data
Clock
Halt Mode register
0xB9
Data
Init Register
ACE Core
Init Register
Init Register
Prog. Comparator
ACE Core
ACE Core
ACE Core
ACE Core
ACE Core
ACE Core
Init Register
Signature
Init Register
Init Register
EEPROM
ACE Core
ACE Core
ACE Core
ACE Core
ACE Core
Initialization Register 1 (volatile)8
Internal Clock trimming register (volatile)
Initialization Register 18
Initialization Register 28
COMP register
0xBA
Data
0xBB
Data
0xBC
Data
0xBD
Data
0xBE
Data
XHI register
0xBF
Data
XLO register
0xC0
Data
Power mode clear (PMC)
0xCE
Data
SP register
0xCF
Data
Status Register (SR)9
Initialization Register 3 (volatile)8
Initialization Register 38
Device_ID register7
0xD0
Data
0xD1
Data
0xD2
Data
0xD3
Data
Initialization Register 4 (volatile)8
Initialization Register 48
Code EEPROM
0xD4
Data
0xC00 – 0xFF5
0xFF6 – 0xFF7
0xFF8 – 0xFF9
0xFFA – 0xFFB
0xFFC – 0xFFD
0xFFE – 0xFFF
Program
Program
Program
Program
Program
Program
Timer0 Interrupt vector
PWM Timer1 Interrupt vector
MIW Interrupt vector
Software Interrupt vector
ADC Interrupt vector
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PRODUCT SPECIFICATION
FMS7401/7401L
Table 31. Memory Mapped Registers and their Register Bit Definitions
Definitions of Register Bits
Address
0x9D
0x9F
0xA0
0xA2
0xA4
0xA5
0xA6
0xA7
0xA8
0xA9
0xAA
0xAB
0xAC
0xAD
0xAE
0xAF
0xB0
0xB1
0xB2
0xB3
0xB4
0xB5
0xB6
0xB7
0xBB
0xBC
0xBD
0xBE
0xBF
0xCE
0xCF
0xD1
0xD4
Name10
ADATA
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
8-bit digital value of ADC conversion
ADCNTRL1
ADCNTRL2
DDELAY
PSCALE
DTIME
APND
REFBY2
COMPEN
PLLEN
X
AINTEN
COMPSEL
PWINT
ASTART
ENAMP
EPWM
REFSEL
ENDAS
ACHSEL [3:0]
ASPEED [1:0] ENIS
GAIN
OFFMODE
FSEL
DD [3:0]
PS [2:0]
FS [1:0]
FMODE
X
X
X
X
X
DT [4:0]
T1CMPALO
T1CMPAHI
T1CMPBLO
T1CMPBHI
T1RALO
T1RAHI
TMR1LO
TMR1HI
T1CNTRL
WKEDG
WKPND
WKEN
Low 8 bits of 12-bit T1CMPA register
High 4 bits of 12-bit T1CMPA register
Low 8 bits of 12-bit T1CMPB register
X
X
X
X
X
X
X
X
High 4 bits of 12-bit T1CMPB register
Low 8 bits of 12-bit T1RA register
X
High 4 bits of 12-bit T1RA register
Low 8 bits of 12-bit TMR1 register
X
X
X
X
High 4 bits of 12-bit TMR1 register
T1C3
T1C2
T1C1
T1C0
T1PND
T1EN
X
T1BOUT
Bit number = port number, Edge direction
Bit number = port number, Pending flag for port
Bit number = port number, Interrupt enable for port
PORTGD
PORTGC
PORTGP
WDSVR
T0CNTRL
HALT
Bit number = port number, Data when output, Weak pull-up when input
Bit number = port number, Input or output setting of port
Bit number = port number, Digital value at pin, Read-only
Accepts the value 0x1B as a watchdog service
WKINTEN
Reserved
CLK_ADJ
X
X
X
X
X
T0PND
EIDLE
WDIS
T0INTEN
EHALT
RDIS
Reserved
CMODE
Reserved
unused
Reserved
WDEN
Reserved
BOREN
Reserved
UBD
InitReg1
InitReg2
COMP
8-bit value used internally to trim the internal oscillator frequency
CL [5:0]
VLOOP
COUT
XHI
X
X
X
X
X
code/data
X [9:8]
XLO
Low 8 bits of 11-bit X register
X
SP
X
X
X
SP [3:0]
STATUS
InitReg3
InitReg4
EE Ready
unused
unused
unused
unused
Global Int.
Zero
Carry
Half Carry
Negative
BOR_TRIM [2:0]
COMP_TRIM [2:0]
T1HS_DIR T1HS2_LEV T1HS1_LEV
ISOURCE_TRIM [4:0]
1. The FMS7401/7401L’s normal mode operation begins after a system reset and is when the 8-bit microcontroller core begins executing the instruction program
residing in the code EEPROM memory.
2. The FMS7401/7401L must be placed in a special programming mode of operation in order to have full write and read access of all of the device memories. Refer
to the In-circuit Programming Specification section of the datasheet for details.
3. Refer to the the 8-Bit Microcontroller Core section of the datasheet for additional details.
4. Refer to the Electrical Characteristics section of the datasheet.
5. The Initialization Register 2 shadow register will automatically be restored with its original factory setting during a system reset.
6. Once the read and/or write protection is enabled, the only possible external action of accessing the memory in programming mode is to issue a “Program Erase”
command through the programming interface that clears the entire code EEPROM memory contents including the volatile Initialization Register 1. This allows full
access to the user enabling new device memory programming for the single programming mode session (unless the non-volatile WDIS and RDIS bits are cleared).
Refer to the In-circuit Programming Specification section of the datasheet for addition details.
7. The register can only be read.
8. The register cannot be access during normal operation only in programming mode.
9. All SR bits except for bit 7 (the global interrupt mask) are read only when using direct, indirect, or indexed instructions. Software cannot restore SR using the tradi-
tional microcontroller methods. Refer to the 8-Bit Microcontroller Core section of the datasheet for additional details.
10.A) Names in all capital letters are predefined in the assembler. B) Names of the individual bits are not predefined and must be definced using an EQU statement
in the user program source code: for example, “APND
shadow register.
EQU 7”. C) The initialization registers listed are the non-volatile registers. Each register has a volatile
REV. 1.0.2 6/23/04
59
FMS7401/7401L
PRODUCT SPECIFICATION
12 In-circuit Programming Specification
The FMS7401/7401L supports in-circuit programming of all internal memory mapped registers including the data EEPROM, code
EEPROM, and initialization registers. In-circuit programming consists of a 4-wire serial interface used to place the device in pro-
gramming mode and issue all programming commands.1 The external programmer should follow the device pinout1 defined in Fig-
ure 19 and the timing rules defined by the parameters listed in Table 31 as shown in Figure 20 and Figure 21.
Figure 19. Programming Mode Pin Configurations
1
2
3
4
8
NC/VCC
VCC
NC
1
2
3
4
8
SHIFT_IN
GND
VCC
7
6
5
LOAD
7
6
5
NC/VCC
NC
CLOCK
SHIFT_OUT
SHIFT_IN
GND
SHIFT_OUT
CLOCK
LOAD
FMS7401L 8-Pin PDIP/SOIC
FMS7401L 8-Pin TSSOP
1
2
3
4
5
6
7
14
13
12
11
10
9
VCC
1
2
3
4
5
6
7
14
13
12
11
10
9
SHIFT_IN
NC
SHIFT_IN
NC
VCC
NC/VCC
NC/VCC
VDD
GND
GND
NC/VCC
NC
NC
RESET
NC
RESET
NC
NC
NC
LOAD
SHIFT_OUT
CLOCK
LOAD
SHIFT_OUT
CLOCK
8
8
NC/GND
AGND
FMS7401L 14-Pin PDIP/SOIC/TSSOP
FMS7401 14-Pin PDIP/SOIC/TSSOP
Table 32. Programming Interface Electrical Characteristics2
Symbol
THI
Parameter
CLOCK high time
Conditions
25 °C
Min.
500
500
100
100
100
900
500
5
Typ.
Max.
DC
Units
nS
TLO
CLOCK low time
25 °C
DC
nS
TDIS
SHIFT_IN setup time
SHIFT_IN hold time
SHIFT_OUT setup time
SHIFT_OUT hold time
SHIFT_OUT sample time
Loading time
25 °C
nS
TDIH
25 °C
nS
TDOS
25 °C
nS
TDOH
25 °C
nS
TACCESS
TLOAD1, TLOAD2
TLOAD3, TLOAD4
TREADY
25 °C
DC
nS
,
25 °C
µS
EEPROM write time
System Reset time
25 °C
25 °C
3.7
3.7
mS
mS
TRESET
12.1 Programming Mode Interface
In order to place the device in programming mode, a 10-bit opcode (0x34B) must be shifted into the device during its system
reset. A system reset may be triggered during the device power-up by the Power-on Reset circuit or with the device already
powered with a low pulse on the device RESET pin.3 After power-up, the external programmer must shift in the 10-bit opcode
before the system reset sequence completes. If the correct opcode is shifted, the device will automatically enter programming
mode once the system reset sequence has completed.
The 10-bit opcode is serially shifted with the most significant bit (MSB) first into the device through the SHIFT_IN pin. Each
opcode data bit must be valid by TDIS before the rising edge of CLOCK. As the opcode is shifted, the current 10-bit pattern is
compared against 0x34B. If the 10-bit pattern is a match, the device will set the program mode flag and the device will enter
programming mode once the system reset sequence completes (see Figure 20).
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PRODUCT SPECIFICATION
FMS7401/7401L
The opcode must be shifted in after Vcc settles to its nominal voltage level and before the system reset sequence (TRESET) com-
pletes. Otherwise, the device will begin with its normal operation executing the instruction program residing in the code
EEPROM memory. If an external reset is applied by bringing the RESET pin low, the 10-bit opcode may be shifted once
RESET is released and before the system reset sequence completes.
12.2 Programming Protocol
Once the device is in programming mode, the programming protocol and commands may be issued. An externally controlled
4-wire interface consisting of a LOAD (G3) control, serial data SHIFT_IN (G4) input, serial data SHIFT_OUT (G2) output,
and CLOCK (G1) pins are used to access the internal memory and registers. Communication between the external programmer
and the FMS7401/7401L is performed through a 32-bit command and response word, as described in Table 23. The serial data
timing for the 4-wire interface is shown in Figure 21 and the programming protocol is shown in Figure 20. In order to exit pro-
gramming mode, the device must be powered down or an external reset must be applied.
12.2.1 Byte Write Sequence
After the external programmer puts the FMS7401/7401L into programming mode, the LOAD pin must be set to Vcc before
serially shifting the first 32-bit command word using the SHIFT_IN and CLOCK signals. By definition, bit 31 of the command
word must be shifted first followed by all other bits. With each bit of the 32-bit write command word shifted, the device shifts
out a bit of the 32-bit response word from the previous command through the SHIFT_OUT pin. The external programmer may
sample SHIFT_OUT after TACCESS from the rising edge of CLOCK. The serial response word sent immediately after entering
programming mode may contain indeterminate data.
After all 32 bits of the command word are shifted, the external programmer must set the LOAD signal to 0V and apply two
clock pulses to the CLOCK signal, as shown in Figure 20, to complete the program cycle. Once the LOAD signal is brought
low, the SHIFT_OUT pin acts as the handshaking signal between the device and external programmer hardware. When execut-
ing the write command, the device sets SHIFT_OUT low by the time the external programmer has issued the second rising
edge of CLOCK informing the external programmer that the memory write is in progress. The external programmer must wait
TREADY for SHIFT_OUT to return high before returning the LOAD signal to Vcc to initiate the next command cycle.
12.2.2 Page Write Sequence
Page mode is a convenient and fast way to program the code EEPROM memory. In this mode, 16 bytes of data are written
using a single write command followed by a stream of data bytes. Only full pages can be written in page mode where the
address in the command word points to the beginning of a page.4 After all 16 bytes of data has been shifted, the data will be
written at once speeding up the total write time by a factor of 16 compared to byte mode programming. Figure 22 shows the
page mode programming protocol.
Page mode’s 32-bit write command word is similar to a byte write command except that bit 31 must be set to 1 in order to
enable page mode. The address in the page-write command word (bits 17 to 8) must select the page to program the 16 bytes of
data (the page address is a multiple of the page size: 0x000, 0x010, 0x020, etc.). The first byte of the page to program must be
placed in the last 8 bits of the page-write command word (bits 7 to 0). All other bytes in the page must immediately follow after
the initial page-write command has been entered.
The LOAD pin must be set to Vcc before serially shifting in the 32-bit page-write command word using the SHIFT_IN and
CLOCK signals. By definition, bit 31 of the command word must be shifted first followed by all other bits. After all 32 bits of
the command word are shifted, the external programmer must set the LOAD signal to 0V and apply two clock pulses to the
CLOCK signal to latch the first byte of the page in its temporary data buffer. The LOAD signal must be returned to Vcc in
order for the external programmer to shift the second byte of the page into the device (without repeating the command word).
Once all 8 bits of the byte are shifted, the LOAD signal must again be set to 0V followed by two clocks pulses of the CLOCK
signal in order to latch byte into its temporary data buffer. This process must be repeated until all 16 bytes are loaded into their
data buffers.
While the 16th byte of data is being latched, the actual write to the code EEPROM page, selected by the address in the 32-bit
page-write command word, occurs. Once the LOAD signal is brought low, the SHIFT_OUT pin acts as the handshaking signal
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FMS7401/7401L
PRODUCT SPECIFICATION
between the device and external programmer hardware. The device sets SHIFT_OUT low during a page-write command by the
time the external programmer has issued the second rising edge of CLOCK informing the programmer that the memory write
is in progress. The external programmer must wait TREADY for SHIFT_OUT to return high before returning the LOAD signal to
Vcc to initiate the next command cycle.
12.2.3 Byte Read Sequence
The external programmer can only perform memory reads a byte at a time. Before shifting each new command, the external
programmer must set the LOAD signal to Vcc. By definition, bit 31 of the command word must be shifted first followed by all
other bits. With each bit of the 32-bit read command word shifted, the device shifts out a bit of the 32-bit response word from
the previous command through the SHIFT_OUT pin. The external programmer must sample SHIFT_OUT after TACCESS from
the rising edge of CLOCK. The serial response word sent immediately after entering programming mode may contain indeter-
minate data.
After all 32 bits of the read command word are shifted, the external programmer must set the LOAD signal to 0V and apply
two clock pulses to the CLOCK signal, as shown in Figure 20, to complete the read cycle. At the rising edge of the second
clock pulse, the data read from the address provided in the read command word is latched into the lower 8-bits of its response
word. Once LOAD is returned to Vcc, the next 32-bit command word may be shifted while the response word to the previous
read command is shifted out with the data read from memory. If the last read command has been shifted, a dummy read com-
mand must be shifted to collect the last response word containing the last data byte read.
Table 33. 32-Bit Command and Response Word
Bit Number
Bit 31
Input Command Word
Output Response Word
Set to 1 to enable page mode memory access otherwise 0 for byte Same as the input command word.
mode.
Bit 30
Bit 29
Must be set to 0.
Same as the input command word.
Same as the input command word.
Set to 1 to access the data memory space (data EEPROM or
initialization registers) otherwise 0.
Bit 28
Set to 1 to access the code EEPROM otherwise 0.
Must be set to 0.
Same as the input command word.
Same as the input command word.
Same as the input command word.
Same as the input command word.
Same as the input command word.
Bits 27 – 25
Bit 24
Set to 1 to perform a read or 0 to perform a write.
Set to 1 to perform a program memory erase otherwise 0.
Must be set to 0.
Bit 22
Bits 23, 21 – 18
Bits 17 – 8
Lower 10-bits of the memory mapped address byte to read/write or Same as the input command word.
first byte of the page to write.
Bits 7 – 0
Data to be programmed if a write command or all zeros if a read
command.
Same as the previous input write command word
or the data read after an input read command
word.
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PRODUCT SPECIFICATION
FMS7401/7401L
Figure 20. Programming Protocol
Figure 21. Serial Data Timing1
THI
TLO
CLOCK (G1)
TDIS
TDIH
Valid
TDOS
SHIFT_IN (G4)
TDOH
Valid
SHIFT_OUT (G2)
Figure 22. Page Mode Protocol
LOAD
32-bit Command = Page Write
32-bit Command = Page Write
from address 0xC10
SHIFT_IN
from address 0xC00
Page 0
Byte 1
(First)
Page 0
Byte 16
(Last)
Page 1
Byte 1
(First)
Continue with
Next Bytes in
the Page
0x90
PageWr
Page 0
Byte 2
Page 0
Byte 3
0x90
PageWr
0x00
0x00
0x00
0x10
CLOCK
32 Clock
Cycles
8 Clock
Cycles
8 Clock
Cycles
8 Clock
Cycles
32 Clock
Cycles
SHIFT_OUT
Page Write
Ready
Check Ready/Busy
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FMS7401/7401L
PRODUCT SPECIFICATION
12.2.4 Program Memory Erase
The external programmer may erase the entire code EEPROM memory array using two special program erase byte write commands.
This special erase option may also be used to unlock memory protected (WDIS/RDIS=1) devices without compromising design secu-
rity. The special program erase byte write command overrides the WDIS memory security bit if set. Once both special byte write
commands are issued, the volatile Initialization Register 1 is automatically cleared to unprotect the current programming mode
session and allow complete access of the device memories.5 The external programmer may then re-program the code EEPROM with
a new pattern or permanently disable all security features by re-programming the non-volatile Initialization Register 1. All other
memories, including the data EEPROM, are unaffected by the program erase commands.
The special program erase protocol requires the external programmer to shift two 32-bit command words addressing two
separate page addresses. The special program erase 32-bit command word is similar to a byte write command except that bit 22
must be set to 1 to enable the program erase mode. The code EEPROM memory must also be selected by setting bit 28 of the
command word. The first command word must select all even pages of the memory by setting the address bits (bits 17 to 8) to
0x000. The second command word must select all odd pages by setting the address bits to 0x010 of the command word. Any
data value (bits 7 to 0) shifted as part of the individual command word may be used to erase the pages of the code EEPROM.
After each even/odd page program erase command is executed, the even/odd pages of the code EEPROM memory is filled with
the data supplied in the command erasing their previous program code data values. If the external programmer issues only one
of the (even/odd page) erase commands, only half the pages will be erased by the data selected and the volatile Initialization
Register 1 will not be cleared. Therefore, the current programming mode session will remain protected if either the memory
protection (WDIS/RDIS) bits are set.
After the external programmer puts the FMS7401/7401L into programming mode, the LOAD pin must be set to Vcc before
serially shifting the first 32-bit program erase command word using the SHIFT_IN and CLOCK signals. By definition, bit 31
of the command word must be shifted first and then followed by all other bits. With each bit of the 32-bit write command word
shifted, the device shifts out a bit of the 32-bit response word from the previous command through the SHIFT_OUT pin. The
external programmer may sample SHIFT_OUT after TACCESS from the rising edge of CLOCK. The serial response word sent
immediately after entering programming mode may contain indeterminate data. After all 32 bits of the command word are
shifted, the external programmer must set the LOAD signal to 0V and apply two clock pulses to the CLOCK signal, as shown
in Figure 20, to complete the program cycle. Once the LOAD signal is brought low, the SHIFT_OUT pin acts as the handshak-
ing signal between the device and external programmer hardware. When executing the write command, the device sets
SHIFT_OUT low by the time the external programmer has issued the second rising edge of CLOCK informing the external
programmer that the memory write is in progress. The external programmer must wait TREADY for SHIFT_OUT to return high
before returning the LOAD signal to Vcc to initiate the second program erase command cycle. The volatile Initialization
Register 1 will only be cleared if both commands are successfully executed. All other memory accesses from this point forward
are executed normally.
1. During in-circuit programming, G5 must be either not connected or driven high.
2. The following characteristics are guaranteed by design but are not 100% tested.
3. For addition detail regarding the device power-up and reset conditions refer the Reset Circuit section of the datasheet.
4. Each page in the code EEPROM has 16 bytes and starts at address 0xC00, 0xC10, 0xC20, etc.
5. For additional details regarding the WDIS, RDIS, and initialization registers, refer to the Device Memory section of the datasheet.
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PRODUCT SPECIFICATION
FMS7401/7401L
13 Electrical Characteristics*
Absolute Maximum Ratings
Parameter
Ambient Storage Temperature
Input Voltage
Min.
-65
Typ.
4.0
5
Max.
+150
Unit
°C
V
-0.3
Vcc + 0.3
Vcc Input Voltage
V
Lead Temperature (10s max)
Electrostatic Discharge on all pins
Internal Voltage Regulator output current
+300
°C
V
2000
mA
Operating Conditions
Relative Humidity (non-condensing)
EEPROM write limits
95%
See AC Electrical Characteristics
*. Contact your local Fairchild Sales Representative for FMS7401 availability.
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FMS7401/7401L
PRODUCT SPECIFICATION
13.1 FMS7401L (2.7V to 3.6V)
DC Electrical Characteristics
All measurements are valid for TA=+25°C unless otherwise stated.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
1
2
ICC
Active Supply Current
FICLK=FOSC
0.75
1.2
mA
(without data EEPROM writes in progress)
-40°C to 125°C
2
Active Supply Current
(with data EEPROM writes in progress)
FICLK=FOSC
0.9
6.5
2.0
13
mA
mA
-40°C to 125°C
2
Active Supply Current
FICLK=F(FS=0)
(without data EEPROM writes in progress)
-40°C to 125°C
3
ISTR
ICCH
Start-up Current
250
5
µA
µA
µA
µA
Halt Mode Current
-40°C to 85°C
-40°C to 125°C
-40°C to 125°C
1.3
8.3
15
4
ICCL
SVcc
VIL
Idle Mode Current
180
270
3
Power Supply Ramp Rate
Input Low with Schmitt Trigger buffer
Input High with Schmitt Trigger buffer
Tri-State Leakage
1V/10mS
0.8Vcc
1V/1µs
0.2Vcc
-40°C to 125°C
-40°C to 125°C
-40°C to 125°C
VIN=0V
V
V
VIH
ITL
0.01
85
1
µA
µA
V
IIP
Input Pull-up Current
350
VOL
Output Low Voltage
(G1, G2, G3, G4, G6, G7)
5mA sink current
-40°C to 125°C
0.3Vcc
Output Low Voltage
(G0, G5)
2mA sink current
-40°C to 125°C
0.3Vcc
V
V
V
VOH
Output Low Voltage
(G1, G2, G3, G4, G6, G7)
5mA source current
-40°C to 125°C
0.7Vcc
0.7Vcc
Output Low Voltage
(G0, G5)
2mA source current
-40°C to 125°C
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PRODUCT SPECIFICATION
FMS7401/7401L
AC Electrical Characteristics
All measurements are valid for TA=+25°C unless otherwise stated.
Symbol
Parameter
Conditions
Vcc=3.3V
Min.
Typ.
Max.
Units
5
FOSC
Internal oscillator frequency
1.96
2.00
2.04
MHz
(factory trim set-point)
∆ckv
∆ckt
Internal oscillator frequency voltage variation
Internal oscillator frequency temperature variation
-0.5
-3
+0.5
+3
%
%
Vcc=3.3V
-40°C to 85°C
Vcc=3.3V
-4
+4
%
-40°C to 125°C
FPLL
PLL input reference frequency
PLL Lock time
2.00
MHz
µS
3
TPLL_LOCK
TEEW
-40°C to 125°C
-40°C to 125°C
60
5
EEPROM Writing time
System reset time
3.7
3.7
40
mS
mS
µS
3
TRESET
2.5
4.7
3
TDIO
T1HS1 and T1HS2 default I/O configuration settling
time
3
THALT_REC
Internal device start time after exiting from Halt where -40°C to 125°C
FICLK = FOSC
5
7
µS
2
Brown-out Reset (BOR) Electrical Characteristics
All measurements are valid for TA=+25°C unless otherwise stated.
Parameter
Conditions
Min.
2.64
2.60
2.59
Typ.
Max.
Units
BOR Trigger Vcc Threshold Level
2.71
2.78
2.83
2.83
V
V
V
-40°C to +85°C
-40°C to 125°C
Programmable Comparator Electrical Characteristics
All measurements are valid for TA=+25°C unless otherwise stated.
Parameter
Conditions
Min.
-6%
-8%
Typ.
Max.
Units
V
All 32 thresholds (VTHU
)
VTHU
VTHU
VTHL
VTHL
359
173
95
+6%
Upper Range (0.45V to 2.0V)
-40°C to 125°C
+8%
V
All 31 thresholds (VTHL
)
VTHU – 30mV
VTHU – 35mV
VTHU + 30mV
VTHU + 35mV
V
Lower Range (0.03V to 0.43V)
Comparator Response Time3
-40°C to 125°C
2mV overdrive
5mV overdrive
10mV overdrive
V
nS
nS
nS
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FMS7401/7401L
PRODUCT SPECIFICATION
ADC Electrical Characteristics
All measurements are valid for TA=+25°C unless otherwise stated.
Parameter
Conditions
Min.
Typ.
Max.
Units
ADC Integral Non Linearity (INL) Best Fit3
VAREF=Vcc
1.5
LSB
ASPEED=0 where (FICLK=FOSC)/12
VAREF=Internal Reference (VREF
)
1.5
0.5
LSB
LSB
ASPEED=0 where (FICLK=FOSC)/12
VAREF=Internal Reference (VREF
)
ASPEED=2 where (FICLK=FOSC)/42
-40°C to +125°C
ADC Differential Non
Linearity (DNL)3
Vref=Vcc
2.5
1.5
1
LSB
LSB
LSB
ASPEED=0 where (FICLK=FOSC)/12
V
AREF=Internal Reference (VREF
)
ASPEED=0 where (FICLK=FOSC)/12
VAREF=Internal Reference (VREF
)
ASPEED=2 where (FICLK=FOSC)/42
-40°C to +125°C
ADC Conversion Time3
ASPEED=0 where (FICLK=FOSC)/12
-40°C to +125°C
20
µS
3
Internal Voltage Reference (VREF
Amplifier x16 Gain Error3
)
1.215
V
%
-40°C to +125°C
-40°C to +125°C
2
2
Current Source (ISRC
on G3/AIN1
)
0.9
1
1
1.1
mA
Current Source (ISRC
on G3/AIN1
)
0.89
1.11
mA
Independent Amplifier Electrical Characteristics3
Parameter
Input Bias Current
Conditions
-40°C to +125°C
Min.
Typ.
Max.
Units
-1
+1
µA
mV
dB
Input Offset Voltage
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
4
Open Loop Voltage Gain
Gain Bandwidth Product
Sink/Source Current
97
3.7
MHz
mA
0.5
4.5
68
REV. 1.0.2 6/23/04
PRODUCT SPECIFICATION
FMS7401/7401L
Figure 23. Internal Oscillator Frequency (FOSC) vs. Temperature
Internal Oscillator Frequency (FOSC) vs. Temperature
2.004
2.002
2.000
1.998
1.996
1.994
1.992
1.990
3.6V
3.3V
2.7V
-40
0
25
85
125
Temperature (°C)
Figure 24. Icc Active vs. Temperature (no PLL or data EEPROM writes)
Icc Active vs. Temperature
(no PLL or data EEPROM writes)
900
850
800
750
700
650
600
3.6V
3.3V
2.7V
-40
0
25
85
125
Temperature (°C)
REV. 1.0.2 6/23/04
69
FMS7401/7401L
PRODUCT SPECIFICATION
Figure 25. Icc Active vs. Temperature (no PLL, with data EEPROM writes)
Icc Active vs. Temperature
(no PLL, with data EEPROM writes)
1100
1050
1000
950
3.6V
3.3V
2.7V
900
850
800
750
700
-40
0
25
85
125
Temperature (°C)
Figure 26. Icc Active vs. Temperature (with PLL, no data EEPROM writes)
Icc Active vs. Temperature
(with PLL, no data EEPROM write)
8.5
8.0
7.5
7.0
6.5
6.0
5.5
5.0
4.5
3.6V
3.3V
2.7V
-40
0
25
85
125
Temperature (°C)
70
REV. 1.0.2 6/23/04
PRODUCT SPECIFICATION
FMS7401/7401L
Figure 27. Halt Current vs. Temperature
HALT Current vs. Temperature
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
3.6V
3.3V
2.7V
-40
0
25
85
125
Temperature (°C)
Figure 28. Idle Current vs. Temperature (no PLL)
Idle Current vs. Temperature
(no PLL)
210
200
190
180
170
160
150
3.6V
3.3V
2.7V
-40
0
25
85
125
Temperature (°C)
REV. 1.0.2 6/23/04
71
FMS7401/7401L
PRODUCT SPECIFICATION
Figure 29. Idle Current vs. Temperature (with PLL)
Idle Current vs. Temperature
(with PLL)
1.70
1.60
1.50
1.40
1.30
1.20
3.6V
3.3V
2.7V
-40
0
25
85
125
Temperature (°C)
Figure 30. VOL vs. IOL @ 25°C (G1–G4, G6, G7)
VOL vs. IOL @ 25°C
(G1-G4, G6, G7)
2.5
2.0
1.5
1.0
0.5
0.0
3.6V
3.3V
2.7V
2
5
7
10
15
IOL (mA)
72
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PRODUCT SPECIFICATION
FMS7401/7401L
Figure 31. VOL vs. IOL @ 25°C (G0, G5)
VOL vs. IOL @ 25°C
(G0, G5)
2.5
2.0
1.5
1.0
0.5
3.6V
3.3V
2.7V
0.0
2
5
7
10
15
IOL (mA)
Figure 32. VOH vs. IOH @ 25°C (G1–G4, G6, G7)
VOH vs. IOH @ 25°C
(G1-G4, G6, G7)
3.5
3.0
2.5
2.0
1.5
1.0
0.5
3.6V
3.3V
2.7V
0.0
2
5
7
10
15
I
OH (mA)
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FMS7401/7401L
PRODUCT SPECIFICATION
Figure 33. VOH vs. IOH @ 25°C (G0, G5)
VOH vs. IOH @ 25°C
(G0, G5)
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
3.6V
3.3V
2.7V
2
5
7
10
15
IOH (mA)
Figure 34. BOR Level vs. Temperature
Brown-out Reset Level vs. Temperature
2.75
2.74
2.74
2.73
2.73
2.72
2.72
2.71
2.71
2.70
BOR Level
-40
0
25
85
125
Temperature (°C)
74
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PRODUCT SPECIFICATION
FMS7401/7401L
Figure 35. Programmable Comparator Voltage Level vs. Temperature
Programmable Comparator Voltage Level vs. Temperature
2.5
2.0
1.5
1.0
0.5
0.0
Level 1
Level 31
Level 47
Level 63
-40
0
25
85
125
Temperature (°C)
Figure 36. VREF vs. Temperature
VREF vs. Temperature
1.222
1.22
1.218
1.216
1.214
1.212
1.21
3.6V
3.3V
2.7V
1.208
1.206
1.204
1.202
-40
0
25
85
125
Temperature (°C)
REV. 1.0.2 6/23/04
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FMS7401/7401L
PRODUCT SPECIFICATION
Figure 37. Current Source (ISRC) vs. Temperature
Current Source (ISCR) vs. Temperature
1040
1030
1020
1010
1000
990
3.6V
3.3V
2.7V
980
970
960
950
940
-40
0
25
85
125
Temperature (°C)
Figure 38. Gain 16 Error vs. Temperature
Gain 16 Error vs. Temperature
2.0
1.5
1.0
0.5
3.6V
3.3V
2.7V
0.0
-0.5
-1.0
-1.5
-2.0
-40
0
25
85
125
Temperature (°C)
76
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PRODUCT SPECIFICATION
FMS7401/7401L
1. ICC Active current is dependent on the program code and number of active circuits.The ICC Active current specified is measured with the microcontroller core, PWM
Timer 1, Timer 0, ADC, Uncommitted Amplifier, and Programmable Comparator circuits all active.
2. Refer to the Clock Circuit section of the datasheet for details regarding the FMS7401/7401L’s main system instruction clock (FICLK) and its clock sources (FOSC or
F(FS=0)).
3. The parameter is guaranteed by design but is not 100% tested.
4. The ICC Idle current is based on a continuous Idle Mode looping program and is dependent on the program code.
5. The upper FOSC frequency (4MHz) device option is available upon request.
REV. 1.0.2 6/23/04
77
FMS7401/7401L
PRODUCT SPECIFICATION
Packaging Option
Ordering Information*,†
FSID
FMS7401LEN
FMS7401LVN
FMS7401LEN14
FMS7401LVN14
Package
PDIP8
Supply Voltage
2.7V to 3.6V
2.7V to 3.6V
2.7V to 3.6V
2.7V to 3.6V
Temperature Range
-40°C to 85°C
Method
Qty
40
40
25
25
Rail
Rail
Rail
Rail
PDIP8
-40°C to 125°C
-40°C to 85°C
PDIP14
PDIP14
-40°C to 125°C
*SOIC and TSSOP packages are available upon request. Contact your local Fairchild Sales Representative.
†Contact your local Fairchild Sales Representative for FMS7401 availability.
78
REV. 1.0.2 6/23/04
PRODUCT SPECIFICATION
FMS7401/7401L
Physical Dimensions††
8-Pin PDIP
0.373 - 0.400
(9.474 - 10.16)
0.090
(2.286)
8
7
0.032 0.005
(0.813 0.127)
RAD
8
7
6
5
4
0.092
(2.337)
DIA
0.250 - 0.005
(6.35 0.127)
Pin #1
IDENT
+
Pin #1 IDENT
1
Option 1
1
2
3
Option 2
0.280
MIN
0.040
(1.016)
Typ.
(7.112)
0.030
0.145 - 0.200
(3.683 - 5.080)
0.039
(0.991)
MAX
(0.762)
0.300 - 0.320
(7.62 - 8.128)
20° 1°
0.130 0.005
(3.302 0.127)
0.125 - 0.140
95°
5
(3.175 - 3.556)
0.065
(1.651)
0.125
(3.175)
DIA
0.020
90° 4°
Typ
0.009 - 0.015
(0.508)
Min
(0.229 - 0.381)
NOM
0.018 0.003
(0.457 0.076)
+0.040
-0.015
0.325
0.100 0.010
+1.016
-0.381
8.255
(2.540 0.254)
0.045 0.015
(1.143 0.381)
0.060
(1.524)
0.050
(1.270)
8-Pin PDIP
14-Pin PDIP
0.740 – 0.770
(18.80 – 19.56)
0.090
(2.286)
14 13 12 11 10
9
6
8
14 13 12
INDEX
AREA
0.250 – 0.010
(6.350 – 0.254)
PIN NO. 1
IDENT
PIN NO. 1
IDENT
1
2
3
4
5
7
1
2
3
0.092
(2.337)
0.030
(0.762)
MAX
DEPTH
DIA
OPTION 1
OPTION 02
0.135 0.005
(3.429 0.127)
0.300 – 0.320
(7.620 – 8.128)
0.065
(1.651)
0.060
TYP
0.145 – 0.200
(3.683 – 5.080)
4° TYP
OPTIONAL
(1.524)
0.008 – 0.016
(0.203 – 0.406)
95° 5°
TYP
0.020
(0.508)
MIN
90° 4° TYP
0.125 – 0.150
(3.175 – 3.810)
0.075 0.015
(1.905 0.381)
0.280
(7.112)
MIN
0.014 – 0.023
(0.355 – 0.584)
TYP
0.100 0.010
(2.540 0.254)
TYP
TYP
0.050 0.010
(1.270 – 0.254)
+0.040
0.325
–0.015
+1.016
–0.381
8.255
14-Pin PDIP
††Dimensions are in inches (millimeters) unless otherwise noted.
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79
FMS7401/7401L
PRODUCT SPECIFICATION
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO
ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME
ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
6/23/04 0.0m 005
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2004 Fairchild Semiconductor Corporation
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