FQB9N50C_09 [FAIRCHILD]
500V N-Channel MOSFET; 500V N沟道MOSFET
| 型号： | FQB9N50C_09 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | 500V N-Channel MOSFET |
| 文件： | 总9页 (文件大小：797K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TM
QFET
FQB9N50C/FQI9N50C
500V N-Channel MOSFET
General Description
Features
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild’s proprietary,
planar stripe, DMOS technology.
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulse in the
avalanche and commutation mode. These devices are well
suited for high efficiency switched mode power supplies,
active power factor correction, electronic lamp ballasts
based on half bridge topology.
•
•
•
•
•
•
9 A, 500V, R
=
0.8 Ω @V = 10 V
GS
DS(on)
Low gate charge ( typical 28 nC)
Low Crss ( typical 24 pF)
Fast switching
100% avalanche tested
Improved dv/dt capability
D
!
D
"
! "
"
"
!
G
I2-PAK
FQI Series
D2-PAK
FQB Series
G
S
!
S
G D S
Absolute Maximum Ratings
T = 25°C unless otherwise noted
C
Symbol
Parameter
FQB9N50C/FQI9N50C
Units
V
V
I
Drain-Source Voltage
500
9
DSS
- Continuous (T = 25°C)
Drain Current
A
D
C
- Continuous (T = 100°C)
5.4
A
C
I
(Note 1)
Drain Current
- Pulsed
36
A
DM
V
E
I
Gate-Source Voltage
± 30
360
V
GSS
AS
(Note 2)
(Note 1)
(Note 1)
(Note 3)
Single Pulsed Avalanche Energy
Avalanche Current
mJ
A
9
AR
E
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
13.5
4.5
mJ
V/ns
W
AR
dv/dt
P
Power Dissipation (T = 25°C)
135
D
C
- Derate above 25°C
Operating and Storage Temperature Range
1.07
-55 to +150
W/°C
°C
T , T
J
STG
Maximum lead temperature for soldering purposes,
T
300
°C
L
1/8" from case for 5 seconds
Thermal Characteristics
Symbol
Parameter
Typ
--
Max
0.93
40
Units
°C/W
°C/W
°C/W
R
R
R
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Ambient *
Thermal Resistance, Junction-to-Ambient
θJC
θJA
θJA
--
--
62.5
©2009 Fairchild Semiconductor Corporation
Rev. A, Jun 2009
Electrical Characteristics
T = 25°C unless otherwise noted
C
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
BV
V
= 0 V, I = 250 µA
GS D
Drain-Source Breakdown Voltage
500
--
--
--
--
V
DSS
∆BV
Breakdown Voltage Temperature
Coefficient
DSS
I
= 250 µA, Referenced to 25°C
0.57
V/°C
D
/
∆T
J
I
V
V
V
V
= 500 V, V = 0 V
--
--
--
--
--
--
--
--
1
µA
µA
nA
nA
DSS
DS
GS
Zero Gate Voltage Drain Current
= 400 V, T = 125°C
10
DS
GS
GS
C
I
= 30 V, V = 0 V
Gate-Body Leakage Current, Forward
Gate-Body Leakage Current, Reverse
100
-100
GSSF
DS
I
= -30 V, V = 0 V
GSSR
DS
On Characteristics
V
V
V
V
= V , I = 250 µA
Gate Threshold Voltage
2.0
--
--
4.0
0.8
--
V
Ω
S
GS(th)
DS
GS
DS
GS
D
R
Static Drain-Source
On-Resistance
DS(on)
= 10 V, I = 4.5 A
0.65
6.5
D
g
= 40 V, I = 4.5 A
(Note 4)
Forward Transconductance
--
FS
D
Dynamic Characteristics
C
C
C
Input Capacitance
--
--
--
790
130
24
1030
170
30
pF
pF
pF
iss
V
= 25 V, V = 0 V,
GS
DS
Output Capacitance
oss
rss
f = 1.0 MHz
Reverse Transfer Capacitance
Switching Characteristics
t
t
t
t
Turn-On Delay Time
Turn-On Rise Time
Turn-Off Delay Time
Turn-Off Fall Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
--
--
--
--
--
--
--
18
65
93
64
28
4
45
140
195
125
35
ns
ns
d(on)
V
= 250 V, I = 9 A,
DD
D
r
R
= 25 Ω
G
ns
d(off)
f
(Note 4, 5)
(Note 4, 5)
ns
Q
Q
Q
nC
nC
nC
g
V
V
= 400 V, I = 9 A,
DS
D
--
= 10 V
gs
gd
GS
15
--
Drain-Source Diode Characteristics and Maximum Ratings
I
Maximum Continuous Drain-Source Diode Forward Current
--
--
--
--
--
--
--
9
36
1.4
--
A
A
S
I
Maximum Pulsed Drain-Source Diode Forward Current
SM
V
t
V
V
= 0 V, I
= 0 V, I
=
=
9 A
Drain-Source Diode Forward Voltage
Reverse Recovery Time
--
V
SD
GS
S
S
9 A,
335
2.95
ns
µC
rr
GS
dI / dt = 100 A/µs
(Note 4)
Q
Reverse Recovery Charge
--
F
rr
Notes:
1. Repetitive Rating : Pulse width limited by maximum junction temperature
2. L = 8 mH, I = 9A, V = 50V, R = 25 Ω, Starting T = 25°C
AS
DD
G
J
3. I ≤ 9A, di/dt ≤ 200A/µs, V ≤ BV
Starting T = 25°C
SD
DD
DSS,
J
4. Pulse Test : Pulse width ≤ 300µs, Duty cycle ≤ 2%
5. Essentially independent of operating temperature
©2009 Fairchild Semiconductor Corporation
Rev. A, Jun 2009
Typical Characteristics
VGS
Top :
15.0 V
10.0 V
8.0 V
7.0 V
6.0 V
5.5 V
5.0 V
101
100
10-1
101
150oC
Bottom : 4.5 V
-55oC
25oC
100
※
Notes :
μ
※
Notes :
1. 250 s Pulse Test
1. VDS = 40V
℃
2. TC = 25
μ
2. 250 s Pulse Test
-1
10
10
-1
100
101
2
4
6
8
10
VGS, Gate-Source Voltage [V]
VDS, Drain-Source Voltage [V]
Figure 1. On-Region Characteristics
Figure 2. Transfer Characteristics
2.0
1.5
1.0
0.5
101
VGS = 10V
100
VGS = 20V
℃
150
※
Notes :
1. VGS = 0V
2. 250 s Pulse Test
℃
25
※
℃
Note : T = 25
μ
J
-1
10
0
5
10
15
20
25
0.2
0.4
0.6
0.8
1.0
1.2
1.4
ID, Drain Current [A]
VSD, Source-Drain voltage [V]
Figure 3. On-Resistance Variation vs
Drain Current and Gate Voltage
Figure 4. Body Diode Forward Voltage
Variation with Source Current
and Temperature
2000
1600
1200
800
400
0
12
10
8
C
iss = Cgs + Cgd (Cds = shorted)
oss = Cds + Cgd
rss = Cgd
C
C
VDS = 100V
VDS = 250V
VDS = 400V
C
iss
Coss
6
※
Notes ;
4
C
1. VGS = 0 V
2. f = 1 MHz
rss
2
※
Note : ID = 9A
25
0
-1
10
100
101
0
5
10
15
20
30
QG, Total Gate Charge [nC]
VDS, Drain-Source Voltage [V]
Figure 5. Capacitance Characteristics
Figure 6. Gate Charge Characteristics
©2009 Fairchild Semiconductor Corporation
Rev. A, Jun 2009
Typical Characteristics (Continued)
1.2
1.1
1.0
3.0
2.5
2.0
1.5
1.0
0.5
0.0
※
Notes :
0.9
0.8
1. VGS = 0 V
※
Notes :
μ
2. ID = 250
A
1. VGS = 10 V
2. ID = 4.5 A
-100
-50
0
50
100
150
200
-100
-50
0
50
100
150
200
TJ, Junction Temperature [oC]
T, Junction Temperature [oC]
J
Figure 7. Breakdown Voltage Variation
vs Temperature
Figure 8. On-Resistance Variation
vs Temperature
102
10
8
Operationin This Area
is Limited by R DS(on)
10 µs
100 µs
1 ms
101
6
10 ms
100 ms
DC
4
100
※
Notes :
1. TC = 25 o
2. TJ = 150 o
3. Single Pulse
C
2
C
-1
10
0
25
0
10
101
102
103
50
75
100
125
150
℃
TC, Case Temperature [ ]
VDS, Drain-Source Voltage [V]
Figure 9. Maximum Safe Operating Area
Figure 10. Maximum Drain Current
vs Case Temperature
1 0 0
D = 0 .5
0 .2
※
N o te s
:
1 0 -1
0 .1
℃
/W M a x .
1 . Z θ (t)
=
0 .9 3
J C
2 . D u ty F a c to r, D = t1 /t2
3 . T JM
-
T C
=
P D
* Z θ (t)
J C
0 .0 5
M
0 .0 2
0 .0 1
PDM
t1
s in g le p u lse
t2
1 0 -2
1 0 -5
1 0 -4
1 0 -3
1 0 -2
1 0 -1
1 0 0
1 0 1
t1 , S q u a re W a ve P u ls e D u ra tio n [s e c ]
Figure 11. Transient Thermal Response Curve
©2009 Fairchild Semiconductor Corporation
Rev. A, Jun 2009
Gate Charge Test Circuit & Waveform
VGS
Same Type
50Kꢀ
as DUT
Qg
12V
200nF
10V
300nF
VDS
VGS
Qgs
Qgd
DUT
3mA
Charge
Resistive Switching Test Circuit & Waveforms
RL
VDS
90%
VDS
VDD
VGS
RG
10%
VGS
DUT
10V
td(on)
tr
td(off)
tf
t on
t off
Unclamped Inductive Switching Test Circuit & Waveforms
BVDSS
--------------------
BVDSS - VDD
L
1
2
2
----
EAS
=
LIAS
VDS
ID
BVDSS
IAS
RG
VDD
ID (t)
VDD
VDS (t)
DUT
10V
t p
t p
Time
©2009 Fairchild Semiconductor Corporation
Rev. A, Jun 2009
Peak Diode Recovery dv/dt Test Circuit & Waveforms
+
DUT
VDS
_
I SD
L
Driver
RG
Same Type
as DUT
VDD
VGS
• dv/dt controlled by RG
• ISD controlled by pulse period
Gate Pulse Width
--------------------------
VGS
D =
Gate Pulse Period
10V
( Driver )
IFM , Body Diode Forward Current
I SD
di/dt
( DUT )
IRM
Body Diode Reverse Current
Body Diode Recovery dv/dt
VSD
VDS
( DUT )
VDD
Body Diode
Forward Voltage Drop
©2009 Fairchild Semiconductor Corporation
Rev. A, Jun 2009
Mechanical Dimensions
D2 - PAK
Dimensions in Millimeters
©2009 Fairchild Semiconductor Corporation
Rev. A, Jun 2009
Mechanical Dimensions
I2-PAK
4.50 ±0.20
9.90 ±0.20
+0.10
–0.05
1.30
1.27 ±0.10
1.47 ±0.10
0.80 ±0.10
+0.10
–0.05
0.50
2.40 ±0.20
2.54 TYP
2.54 TYP
10.00 ±0.20
Dimensions in Millimeters
Rev. A, Jun 2009
©2009 Fairchild Semiconductor Corporation
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PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Datasheet contains the design specifications for product development. Specifications
may change in any manner without notice.
Advance Information
Formative / In Design
Datasheet contains preliminary data; supplementary data will be published at a later
date. Fairchild Semiconductor reserves the right to make changes at any time without
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First Production
Datasheet contains final specifications. Fairchild Semiconductor reserves the right to
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Full Production
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Not In Production
Rev. I40
©2009 Fairchild Semiconductor Corporation
Rev. A, Jun 2009
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