FQI33N10TU [FAIRCHILD]
Power Field-Effect Transistor, 33A I(D), 100V, 0.052ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-262AA, I2PAK-3;
| 型号： | FQI33N10TU |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Power Field-Effect Transistor, 33A I(D), 100V, 0.052ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-262AA, I2PAK-3 开关 脉冲 晶体管 |
| 文件： | 总11页 (文件大小：620K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
April 2000
TM
QFET
FQB33N10 / FQI33N10
100V N-Channel MOSFET
General Description
Features
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild’s proprietary,
planar stripe, DMOS technology.
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulse in the
avalanche and commutation mode. These devices are well
suited for low voltage applications such as audio amplifier,
high efficiency switching DC/DC converters, and DC motor
control.
•
•
•
•
•
•
•
33A, 100V, R
= 0.052Ω @V = 10 V
DS(on) GS
Low gate charge ( typical 38 nC)
Low Crss ( typical 62 pF)
Fast switching.
100% avalanche tested
Improved dv/dt capability
175°C maximum junction temperature rating
D
!
D
"
! "
"
G !
"
G
S
D2-PAK
FQB Series
I2-PAK
FQI Series
G
D
S
!
S
Absolute Maximum Ratings
ꢀꢀ
T = 25°C unless otherwise noted
C
Symbol
Parameter
FQB33N10 / FQI33N10
Units
V
V
I
Drain-Source Voltage
100
33
DSS
- Continuous (T = 25°C)
Drain Current
A
D
C
- Continuous (T = 100°C)
23
A
C
I
(Note 1)
Drain Current
- Pulsed
132
A
DM
V
E
I
Gate-Source Voltage
±ꢀ25
435
V
GSS
(Note 2)
(Note 1)
(Note 1)
(Note 3)
Single Pulsed Avalanche Energy
Avalanche Current
mJ
A
AS
33
AR
E
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
12.7
6.0
mJ
V/ns
W
AR
dv/dt
Power Dissipation (T = 25°C) *
3.75
127
P
A
D
Power Dissipation (T = 25°C)
W
C
- Derate above 25°C
Operating and Storage Temperature Range
0.85
-55 to +175
W/°C
°C
T , T
J
STG
Maximum lead temperature for soldering purposes,
T
300
°C
L
1/8ꢀ from case for 5 seconds
Thermal Characteristics
Symbol
Parameter
Typ
--
Max
1.18
40
Units
°CꢁW
°CꢁW
°CꢁW
R
R
R
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Ambient *
Thermal Resistance, Junction-to-Ambient
θ
θ
θ
JC
JA
JA
--
--
62.5
* When mounted on the minimum pad size recommended (PCB Mount)
©2000 Fairchild Semiconductor International
Rev. A, April 2000
Electrical Characteristics
ꢀꢀꢀꢀꢀ
T
= 25°C unless otherwise noted
C
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
BV
V
= 0 V, I = 250 µA
GS D
Drain-Source Breakdown Voltage
100
--
--
--
--
V
DSS
∆BV
Breakdown Voltage Temperature
Coefficient
DSS
J
I
= 250 µA, Referenced to 25°C
0.11
V/°C
D
/
I
∆T
V
V
V
V
= 100 V, V = 0 V
--
--
--
--
--
--
--
--
1
µA
µA
nA
nA
DSS
DS
GS
Zero Gate Voltage Drain Current
= 80 V, T = 150°C
10
DS
GS
GS
C
I
I
= 25 V, V = 0 V
Gate-Body Leakage Current, Forward
Gate-Body Leakage Current, Reverse
100
-100
GSSF
DS
= -25 V, V = 0 V
GSSR
DS
On Characteristics
V
V
V
V
= V , I = 250 µA
Gate Threshold Voltage
2.0
--
--
4.0
V
Ω
S
GS(th)
DS
GS
DS
GS
D
R
Static Drain-Source
On-Resistance
DS(on)
=10V,I =16.5A
0.040 0.052
D
g
= 40 V, I = 16.5 A
(Note 4)
Forward Transconductance
--
22
--
FS
D
Dynamic Characteristics
C
C
C
Input Capacitance
--
--
--
1150
320
62
1500
420
80
pF
pF
pF
iss
V
= 25 V, V = 0 V,
GS
DS
Output Capacitance
oss
rss
f = 1.0 MHz
Reverse Transfer Capacitance
Switching Characteristics
t
t
t
t
Turn-On Delay Time
Turn-On Rise Time
Turn-Off Delay Time
Turn-Off Fall Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
--
--
--
--
--
--
--
15
195
80
40
400
170
230
51
ns
ns
d(on)
V
= 50 V, I = 33 A,
DD
D
r
R
= 25 Ω
G
ns
d(off)
f
(Note 4, 5)
(Note 4, 5)
110
38
ns
Q
Q
Q
nC
nC
nC
g
V
V
= 80 V, I = 33 A,
DS
D
7.5
18
--
= 10 V
gs
gd
GS
--
Drain-Source Diode Characteristics and Maximum Ratings
I
Maximum Continuous Drain-Source Diode Forward Current
--
--
--
--
--
--
--
33
132
1.5
--
A
A
S
I
Maximum Pulsed Drain-Source Diode Forward Current
SM
V
t
V
V
= 0 V, I = 33 A
Drain-Source Diode Forward Voltage
Reverse Recovery Time
--
V
SD
GS
S
= 0 V, I = 33 A,
80
0.22
ns
µC
rr
GS
S
(Note 4)
dI / dt = 100 A/µs
Q
Reverse Recovery Charge
--
F
rr
Notes:
1. Repetitive Rating : Pulse width limited by maximum junction temperature
2. L = 0.6mH, I = 33A, V = 25V, R = 25 Ω, Starting T = 25°C
AS
DD
G
J
3. I ꢀ 33A, di/dt ꢀ 300A/µs, V ꢀ BV
Starting T = 25°C
4. Pulse Test : Pulse width ꢀ 300µs, Duty cycle ꢀ 2%
SD
DD
DSS, J
5. Essentially independent of operating temperature
©2000 Fairchild Semiconductor International
Rev. A, April 2000
Typical Characteristics
V
102
102
101
100
Top :
15.0GVS
10.0 V
8.0 V
7.0 V
6.0 V
5.5 V
5.0 V
Bottom: 4.5 V
101
ꢀ
175
ꢀ
25
ꢀ
Notes :
ꢀ
Notes :
ꢁ
1. VDS = 40V
2. 250 s Pulse Test
1. 250 s Pulse Test
2. TC = 25
ꢀ
-55
ꢁ
ꢂ
100
-1
100
101
2
4
6
8
10
10
VGS, Gate-Source Voltage [V]
VDS, Drain-Source Voltage [V]
Figure 1. On-Region Characteristics
Figure 2. Transfer Characteristics
0.20
0.15
0.10
0.05
0.00
102
101
100
VGS = 10V
VGS = 20V
ꢀ
Notes :
ꢀ
175
ꢀ
25
1. VGS = 0V
2. 250 s Pulse Test
ꢀ
ꢁ
Note : T = 25
J
ꢁ
0
20
40
60
80
100
120
0.2
0.4
0.6
0.8
1.0
1.2
1.4
ID, Drain Current [A]
V , Source-Drain voltage [V]
SD
Figure 3. On-Resistance Variation vs.
Drain Current and Gate Voltage
Figure 4. Body Diode Forward Voltage
Variation vs. Source Current
and Temperature
3000
12
10
8
C
iss = Cgs + Cgd (Cds = shorted)
Coss = Cds + C
gd
Crss = C
gd
VDS = 50V
VDS = 80V
2500
2000
1500
1000
500
C
iss
ꢀ
Notes :
C
oss
1. VGS = 0 V
2. f = 1 MHz
6
4
C
rss
2
ꢀ
Note : ID = 33A
0
0
5
10
15
20
25
30
35
40
0
10
-1
100
101
QG, Total Gate Charge [nC]
VDS, Drain-Source Voltage [V]
Figure 5. Capacitance Characteristics
Figure 6. Gate Charge Characteristics
©2000 Fairchild Semiconductor International
Rev. A, April 2000
Typical Characteristics
(Continued)
1.2
1.1
1.0
0.9
0.8
3.0
2.5
2.0
1.5
1.0
0.5
0.0
ꢀ
Notes :
1. V = 0 V
2. IDG=S 250
ꢀ
Notes :
ꢁ
A
1. VGS = 10 V
2. ID = 16.5 A
-100
-50
0
50
100
150
200
-100
-50
0
50
100
150
200
TJ, Junction Temperature [oC]
T, Junction Temperature [oC]
J
Figure 7. Breakdown Voltage Variation
vs. Temperature
Figure 8. On-Resistance Variation
vs. Temperature
35
30
25
20
15
10
5
Operation in This Area
is Limited by R DS(on)
102
101
100
100
s
µ
1 ms
10 ms
DC
ꢀ
Notes :
1. TC = 25 o
2. TJ = 175 o
C
C
3. Single Pulse
0
25
100
101
102
50
75
100
125
150
175
ꢀ
]
TC, Case Temperature [
VDS, Drain-Source Voltage [V]
Figure 9. Maximum Safe Operating Area
Figure 10. Maximum Drain Current
vs. Case Temperature
1 0 0
D = 0 . 5
ꢀ
N o t e s
:
0 .2
0 .1
ꢁ
1 . C(t )
Z
=
1 .1 8
/W M a x .
ꢀ
J
2 . D u t y F a c t o r , D = t 1 /t 2
3 . T J
-
T C
=
P D
*
Z
C(t )
ꢀ
M
M
J
1 0 -1
0 .0 5
PDM
0 .0 2
t1
0 .0 1
t2
s in g l e p u ls e
1 0 -2
1 0 -5
1 0 -4
1 0 -3
1 0 -2
1 0 -1
1 0 0
1 0 1
t1
, S q u a r e W a v e P u ls e D u r a tio n [s e c ]
Figure 11. Transient Thermal Response Curve
©2000 Fairchild Semiconductor International
Rev. A, April 2000
Gate Charge Test Circuit & Waveform
VGS
Same Type
50Kꢀ
as DUT
Qg
12V
200nF
10V
300nF
VDS
VGS
Qgs
Qgd
DUT
3mA
Charge
Resistive Switching Test Circuit & Waveforms
RL
VDS
90%
VDS
VDD
VGS
RG
10%
VGS
DUT
10V
td(on)
tr
td(off)
tf
t on
t off
Unclamped Inductive Switching Test Circuit & Waveforms
BVDSS
--------------------
BVDSS - VDD
L
1
2
2
----
EAS
=
L IAS
VDS
I D
BVDSS
IAS
RG
VDD
ID (t)
VDD
VDS (t)
DUT
10V
t p
t p
Time
©2000 Fairchild Semiconductor International
Rev. A, April 2000
Peak Diode Recovery dv/dt Test Circuit & Waveforms
+
DUT
VDS
_
I SD
L
Driver
RG
Same Type
as DUT
VDD
VGS
• dv/dt controlled by RG
• ISD controlled by pulse period
Gate Pulse Width
--------------------------
VGS
D =
Gate Pulse Period
10V
( Driver )
IFM , Body Diode Forward Current
I SD
di/dt
( DUT )
IRM
Body Diode Reverse Current
Body Diode Recovery dv/dt
VSD
VDS
( DUT )
VDD
Body Diode
Forward Voltage Drop
©2000 Fairchild Semiconductor International
Rev. A, April 2000
Package Dimensions
D2PAK
4.50 ±0.20
9.90 ±0.20
+0.10
–0.05
1.30
0.10 ±0.15
2.40 ±0.20
0.80 ±0.10
1.27 ±0.10
+0.10
0.50
–0.05
2.54 TYP
2.54 TYP
10.00 ±0.20
(8.00)
(4.40)
10.00 ±0.20
(2XR0.45)
0.80 ±0.10
©2000 Fairchild Semiconductor International
Rev. A, April 2000
Package Dimensions
(Continued)
I2PAK
4.50 ±0.20
9.90 ±0.20
+0.10
–0.05
1.30
1.27 ±0.10
1.47 ±0.10
0.80 ±0.10
+0.10
–0.05
0.50
2.40 ±0.20
2.54 TYP
2.54 TYP
10.00 ±0.20
©2000 Fairchild Semiconductor International
Rev. A, April 2000
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
ACEx™
HiSeC™
SuperSOT™-8
SyncFET™
TinyLogic™
UHC™
Bottomless™
CoolFET™
CROSSVOLT™
E2CMOS™
FACT™
ISOPLANAR™
MICROWIRE™
POP™
PowerTrench®
QFET™
VCX™
FACT Quiet Series™
QS™
FAST®
Quiet Series™
SuperSOT™-3
SuperSOT™-6
FASTr™
GTO™
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FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR
INTERNATIONAL.
As used herein:
result in significant injury to the user.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, or (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
2. A critical component is any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or In
Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Obsolete
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
©2000 Fairchild Semiconductor International
Rev. A, January 2000
Product Folder - Fairchild P/N FQI33N10 - 100V N-Channel QFET
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Distributor and field sales
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These N-Channel enhancement mode power
field effect transistors are produced using
Fairchild’s proprietary, planar stripe, DMOS
technology.
This advanced technology has been especially
tailored to minimize on-state resistance,
provide superior switching performance, and
withstand high energy pulse in the avalanche
and commutation mode. These devices are well
suited for low voltage applications such as
audio amplifier, high efficiency switching
DC/DC converters, and DC motor control.
Quality and reliability
This pagePrint version
Design tools
technical information
buy products
technical support
my Fairchild
back to top
Features
company
●
33A, 100V, R
10 V
= 0.052Ω @V
=
DS(on)
GS
●
●
●
●
●
●
Low gate charge ( typical 38 nC)
Low Crss ( typical 62 pF)
Fast switching
100% avalanche tested
Improved dv/dt capability
175°Cmaximum junction temperature
rating
back to top
Product status/pricing/packaging
Product
Product status
Full Production
Pricing*
Package type
Leads
Packing method
FQI33N10TU
$0.83 TO-262(I2PAK)
3
RAIL
Product Folder - Fairchild P/N FQI33N10 - 100V N-Channel QFET
* 1,000 piece Budgetary Pricing
back to top
Models
Package & leads
PSPICE
Condition
Temperature range Software version Revision date
Electrical/Thermal
TO-262(I2PAK)-3
-55°C to 175°C
9.2
May 11, 2001
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© Copyright 2002 Fairchild Semiconductor
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