FQP6P25J69Z

更新时间:2024-09-18 14:22:44
品牌:FAIRCHILD
描述:Power Field-Effect Transistor, 6A I(D), 250V, 1.1ohm, 1-Element, P-Channel, Silicon, Metal-oxide Semiconductor FET, TO-220, 3 PIN

FQP6P25J69Z 概述

Power Field-Effect Transistor, 6A I(D), 250V, 1.1ohm, 1-Element, P-Channel, Silicon, Metal-oxide Semiconductor FET, TO-220, 3 PIN 功率场效应晶体管

FQP6P25J69Z 规格参数

生命周期:Obsolete零件包装代码:SFM
包装说明:FLANGE MOUNT, R-PSFM-T3针数:3
Reach Compliance Code:unknownECCN代码:EAR99
风险等级:5.66Is Samacsys:N
雪崩能效等级(Eas):540 mJ配置:SINGLE WITH BUILT-IN DIODE
最小漏源击穿电压:250 V最大漏极电流 (ID):6 A
最大漏源导通电阻:1.1 ΩFET 技术:METAL-OXIDE SEMICONDUCTOR
JESD-30 代码:R-PSFM-T3元件数量:1
端子数量:3工作模式:ENHANCEMENT MODE
最高工作温度:150 °C封装主体材料:PLASTIC/EPOXY
封装形状:RECTANGULAR封装形式:FLANGE MOUNT
极性/信道类型:P-CHANNEL最大脉冲漏极电流 (IDM):24 A
认证状态:Not Qualified表面贴装:NO
端子形式:THROUGH-HOLE端子位置:SINGLE
晶体管应用:SWITCHING晶体管元件材料:SILICON
Base Number Matches:1

FQP6P25J69Z 数据手册

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April 2000  
TM  
QFET  
FQP6P25  
250V P-Channel MOSFET  
General Description  
Features  
These P-Channel enhancement mode power field effect  
transistors are produced using Fairchild’s proprietary,  
planar stripe, DMOS technology.  
This advanced technology has been especially tailored to  
minimize on-state resistance, provide superior switching  
performance, and withstand high energy pulse in the  
avalanche and commutation mode. These devices are well  
suited for high efficiency switching DC/DC converters.  
-6.0A, -250V, R  
= 1.1@V = -10 V  
DS(on) GS  
Low gate charge ( typical 21 nC)  
Low Crss ( typical 20 pF)  
Fast switching  
100% avalanche tested  
Improved dv/dt capability  
S
!
G!  
G
D
TO-220  
S
!
D
FQP Series  
Absolute Maximum Ratings  
 
T = 25°C unless otherwise noted  
C
Symbol  
Parameter  
FQP6P25  
-250  
-6.0  
-3.8  
-24  
Units  
V
V
I
Drain-Source Voltage  
DSS  
- Continuous (T = 25°C)  
Drain Current  
A
D
C
- Continuous (T = 100°C)  
A
C
I
(Note 1)  
Drain Current  
- Pulsed  
A
DM  
V
E
I
Gate-Source Voltage  
±30  
540  
V
GSS  
(Note 2)  
(Note 1)  
(Note 1)  
(Note 3)  
Single Pulsed Avalanche Energy  
Avalanche Current  
mJ  
A
AS  
-6.0  
9.0  
AR  
E
Repetitive Avalanche Energy  
Peak Diode Recovery dv/dt  
mJ  
V/ns  
W
AR  
dv/dt  
-5.5  
90  
P
Power Dissipation (T = 25°C)  
D
C
- Derate above 25°C  
Operating and Storage Temperature Range  
0.72  
W/°C  
°C  
T , T  
-55 to +150  
J
STG  
Maximum lead temperature for soldering purposes,  
T
300  
°C  
L
1/8from case for 5 seconds  
Thermal Characteristics  
Symbol  
Parameter  
Thermal Resistance, Junction-to-Case  
Thermal Resistance, Case-to-Sink  
Thermal Resistance, Junction-to-Ambient  
Typ  
--  
Max  
1.39  
--  
Units  
°CW  
°CW  
°CW  
R
R
R
θ
θ
θ
JC  
CS  
JA  
0.5  
--  
62.5  
©2000 Fairchild Semiconductor International  
Rev. A, April 2000  
Electrical Characteristics  
ꢀꢀꢀꢀꢀ  
T
= 25°C unless otherwise noted  
C
Symbol  
Parameter  
Test Conditions  
Min  
Typ  
Max  
Units  
Off Characteristics  
BV  
V
= 0 V, I = -250 µA  
GS D  
Drain-Source Breakdown Voltage  
-250  
--  
--  
--  
--  
V
DSS  
BV  
Breakdown Voltage Temperature  
Coefficient  
DSS  
J
I
= -250 µA, Referenced to 25°C  
-0.1  
V/°C  
D
/
I
T  
V
V
V
V
= -250 V, V = 0 V  
--  
--  
--  
--  
--  
--  
--  
--  
-1  
µA  
µA  
nA  
nA  
DSS  
DS  
GS  
Zero Gate Voltage Drain Current  
= -200 V, T = 125°C  
-10  
DS  
GS  
GS  
C
I
I
= -30 V, V = 0 V  
Gate-Body Leakage Current, Forward  
Gate-Body Leakage Current, Reverse  
-100  
100  
GSSF  
DS  
= 30 V, V = 0 V  
GSSR  
DS  
On Characteristics  
V
V
V
V
= V , I = -250 µA  
Gate Threshold Voltage  
-3.0  
--  
--  
-5.0  
1.1  
--  
V
S
GS(th)  
DS  
GS  
DS  
GS  
D
R
Static Drain-Source  
On-Resistance  
DS(on)  
= -10 V, I = -3.0 A  
0.82  
3.3  
D
g
= -40 V, I = -3.0 A  
(Note 4)  
Forward Transconductance  
--  
FS  
D
Dynamic Characteristics  
C
C
C
Input Capacitance  
--  
--  
--  
600  
115  
20  
780  
150  
25  
pF  
pF  
pF  
iss  
V
= -25 V, V = 0 V,  
GS  
DS  
Output Capacitance  
oss  
rss  
f = 1.0 MHz  
Reverse Transfer Capacitance  
Switching Characteristics  
t
t
t
t
Turn-On Delay Time  
Turn-On Rise Time  
Turn-Off Delay Time  
Turn-Off Fall Time  
Total Gate Charge  
Gate-Source Charge  
Gate-Drain Charge  
--  
--  
--  
--  
--  
--  
--  
13  
75  
35  
160  
90  
110  
27  
--  
ns  
ns  
d(on)  
V
= -125 V, I = -6.0 A,  
DD  
D
r
R
= 25 Ω  
G
40  
ns  
d(off)  
f
(Note 4, 5)  
50  
ns  
Q
Q
Q
21  
nC  
nC  
nC  
g
V
V
= -200 V, I = -6.0 A,  
DS  
D
4.7  
10.7  
= -10 V  
gs  
gd  
GS  
(Note 4, 5)  
--  
Drain-Source Diode Characteristics and Maximum Ratings  
I
Maximum Continuous Drain-Source Diode Forward Current  
--  
--  
--  
--  
--  
--  
--  
-6.0  
-24  
-5.0  
--  
A
A
S
I
Maximum Pulsed Drain-Source Diode Forward Current  
SM  
V
t
V
V
= 0 V, I = -6.0 A  
Drain-Source Diode Forward Voltage  
Reverse Recovery Time  
--  
V
SD  
GS  
S
= 0 V, I = -6.0 A,  
170  
1.1  
ns  
µC  
rr  
GS  
S
(Note 4)  
dI / dt = 100 A/µs  
Q
Reverse Recovery Charge  
--  
F
rr  
Notes:  
1. Repetitive Rating : Pulse width limited by maximum junction temperature  
2. L = 24mH, I = -6.0A, V = -50V, R = 25 Ω, Starting T = 25°C  
AS  
DD  
G
J
3. I -6.0A, di/dt 300A/µs, V BV  
Starting T = 25°C  
4. Pulse Test : Pulse width 300µs, Duty cycle 2%  
SD  
DD  
DSS, J  
5. Essentially independent of operating temperature  
©2000 Fairchild Semiconductor International  
Rev. A, April 2000  
Typical Characteristics  
VGS  
Top :  
-15V  
-10V  
-8.0V  
-7.0V  
-6.5V  
-6.0V  
101  
101  
Bottom : -5.5V  
150  
100  
100  
25  
-55  
Notes :  
Notes :  
1. 250 s Pulse Test  
2. TC = 25  
1. VDS = -40V  
-1  
10  
2. 250 s Pulse Test  
-1  
10  
-1  
10  
100  
101  
2
4
6
8
10  
-VGS , Gate-Source Voltage [V]  
-VDS , Drain-Source Voltage [V]  
Figure 1. On-Region Characteristics  
Figure 2. Transfer Characteristics  
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
0.0  
1
10  
VGS = - 10V  
VGS = - 20V  
0
10  
150  
25  
Notes :  
1. VGS = 0V  
2. 250 s Pulse Test  
Note : T = 25  
J
-1  
10  
0
4
8
12  
16  
20  
0.0  
0.5  
1.0  
1.5  
2.0  
2.5  
3.0  
-ID , Drain Current [A]  
-VSD , Source-Drain Voltage [V]  
Figure 3. On-Resistance Variation vs.  
Drain Current and Gate Voltage  
Figure 4. Body Diode Forward Voltage  
Variation vs. Source Current  
and Temperature  
1400  
1200  
1000  
800  
600  
400  
200  
0
12  
10  
8
C
iss = Cgs + Cgd (Cds = shorted)  
Coss = Cds + C  
gd  
VDS = -50V  
VDS = -125V  
VDS = -200V  
Crss = C  
gd  
C
iss  
C
oss  
6
Notes :  
1. VGS = 0 V  
2. f = 1 MHz  
4
C
rss  
2
Note : ID = -6.0 A  
0
-1  
0
10  
1
10  
0
4
8
12  
16  
20  
24  
10  
QG, Total Gate Charge [nC]  
-VDS, Drain-Source Voltage [V]  
Figure 5. Capacitance Characteristics  
Figure 6. Gate Charge Characteristics  
©2000 Fairchild Semiconductor International  
Rev. A, April 2000  
Typical Characteristics  
(Continued)  
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
0.0  
1.2  
1.1  
1.0  
0.9  
0.8  
Notes:  
Notes :  
1. VGS = 0 V  
2. ID= -250  
1. VGS = -10 V  
2. ID = -3.0A  
A
-100  
-50  
0
50  
100  
150  
200  
-100  
-50  
0
50  
100  
150  
200  
T, Junction Temperature [oC]  
T, Junction Temperature [oC]  
J
J
Figure 7. Breakdown Voltage Variation  
vs. Temperature  
Figure 8. On-Resistance Variation  
vs. Temperature  
102  
6
5
4
3
2
1
0
Operation in This Area  
is Limited by R DS(on)  
100 µs  
101  
1 ms  
10 ms  
DC  
100  
Notes :  
1. TC = 25 o  
C
2. TJ = 150 o  
C
3. Single Pulse  
-1  
10  
100  
101  
102  
25  
50  
75  
100  
125  
150  
TC, Case Temperature [  
]
-VDS, Drain-Source Voltage [V]  
Figure 9. Maximum Safe Operating Area  
Figure 10. Maximum Drain Current  
vs. Case Temperature  
1 0 0  
D = 0 .5  
N o te s  
:
0 .2  
0 .1  
1 . J C(t)  
Z
=
1 .3 9  
/W M a x .  
2 . D u ty F a c to r, D = t1 /t2  
3 . T J M  
-
T C  
=
P D  
*
Z
J C(t)  
M
1 0 -1  
0 .0 5  
PDM  
0 .0 2  
0 .0 1  
t1  
s in g le p u ls e  
t2  
1 0 -2  
1 0 -5  
1 0 -4  
1 0 -3  
1 0 -2  
1 0 -1  
1 0 0  
1 0 1  
t1 , S q u a re W a v e P u ls e D u ra tio n [s e c ]  
Figure 11. Transient Thermal Response Curve  
©2000 Fairchild Semiconductor International  
Rev. A, April 2000  
Gate Charge Test Circuit & Waveform  
VGS  
Same Type  
50K  
as DUT  
Qg  
12V  
200nF  
-10V  
300nF  
VDS  
VGS  
Qgs  
Qgd  
DUT  
-3mA  
Charge  
Resistive Switching Test Circuit & Waveforms  
RL  
t on  
t off  
VDS  
td(on)  
tr  
td(off)  
tf  
VDD  
VGS  
VGS  
RG  
10%  
DUT  
-10V  
90%  
VDS  
Unclamped Inductive Switching Test Circuit & Waveforms  
BVDSS  
--------------------  
BVDSS - VDD  
L
1
2
2
----  
EAS  
=
L IAS  
VDS  
I D  
t p  
Time  
VDD  
VDS (t)  
RG  
VDD  
ID (t)  
DUT  
-10V  
IAS  
BVDSS  
t p  
©2000 Fairchild Semiconductor International  
Rev. A, April 2000  
Peak Diode Recovery dv/dt Test Circuit & Waveforms  
+
VDS  
DUT  
_
I SD  
L
Driver  
RG  
Compliment of DUT  
(N-Channel)  
VDD  
VGS  
• dv/dt controlled by RG  
• ISD controlled by pulse period  
Gate Pulse Width  
--------------------------  
VGS  
D =  
Gate Pulse Period  
10V  
( Driver )  
Body Diode Reverse Current  
IRM  
I SD  
( DUT )  
di/dt  
IFM , Body Diode Forward Current  
VSD  
VDS  
( DUT )  
Body Diode  
VDD  
Forward Voltage Drop  
Body Diode Recovery dv/dt  
©2000 Fairchild Semiconductor International  
Rev. A, April 2000  
Package Dimensions  
TO-220  
4.50 ±0.20  
9.90 ±0.20  
(8.70)  
+0.10  
–0.05  
1.30  
ø3.60 ±0.10  
1.27 ±0.10  
1.52 ±0.10  
0.80 ±0.10  
+0.10  
–0.05  
0.50  
2.40 ±0.20  
2.54TYP  
2.54TYP  
[2.54 ±0.20]  
[2.54 ±0.20]  
10.00 ±0.20  
©2000 Fairchild Semiconductor International  
Rev. A, April 2000  
TRADEMARKS  
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is  
not intended to be an exhaustive list of all such trademarks.  
ACEx™  
HiSeC™  
SuperSOT™-8  
SyncFET™  
TinyLogic™  
UHC™  
Bottomless™  
CoolFET™  
CROSSVOLT™  
E2CMOS™  
FACT™  
ISOPLANAR™  
MICROWIRE™  
POP™  
PowerTrench®  
QFET™  
VCX™  
FACT Quiet Series™  
QS™  
FAST®  
Quiet Series™  
SuperSOT™-3  
SuperSOT™-6  
FASTr™  
GTO™  
DISCLAIMER  
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY  
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY  
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;  
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.  
LIFE SUPPORT POLICY  
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT  
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR  
INTERNATIONAL.  
As used herein:  
result in significant injury to the user.  
1. Life support devices or systems are devices or systems  
which, (a) are intended for surgical implant into the body,  
or (b) support or sustain life, or (c) whose failure to perform  
when properly used in accordance with instructions for use  
provided in the labeling, can be reasonably expected to  
2. A critical component is any component of a life support  
device or system whose failure to perform can be  
reasonably expected to cause the failure of the life support  
device or system, or to affect its safety or effectiveness.  
PRODUCT STATUS DEFINITIONS  
Definition of Terms  
Datasheet Identification  
Product Status  
Definition  
Advance Information  
Formative or In  
Design  
This datasheet contains the design specifications for  
product development. Specifications may change in  
any manner without notice.  
Preliminary  
First Production  
This datasheet contains preliminary data, and  
supplementary data will be published at a later date.  
Fairchild Semiconductor reserves the right to make  
changes at any time without notice in order to improve  
design.  
No Identification Needed  
Obsolete  
Full Production  
This datasheet contains final specifications. Fairchild  
Semiconductor reserves the right to make changes at  
any time without notice in order to improve design.  
Not In Production  
This datasheet contains specifications on a product  
that has been discontinued by Fairchild semiconductor.  
The datasheet is printed for reference information only.  
©2000 Fairchild Semiconductor International  
Rev. A, January 2000  

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