FSA266L8X [FAIRCHILD]
TinyLogic Low Voltage UHS Dual SPST Normally Open Analog Switch or 2-Bit Bus Switch; TinyLogic低电压UHS双SPST常开模拟开关或2位总线开关
| 型号： | FSA266L8X |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | TinyLogic Low Voltage UHS Dual SPST Normally Open Analog Switch or 2-Bit Bus Switch |
| 文件： | 总10页 (文件大小：204K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
May 2000
Revised November 2003
FSA266 • NC7WB66
TinyLogic Low Voltage UHS Dual SPST
Normally Open Analog Switch or 2-Bit Bus Switch
General Description
Features
■ Useful in both analog and digital applications
■ Space saving US8 surface mount package
■ MicroPak leadless package
The FSA266 or NC7WB66 is an ultra high-speed (UHS)
dual single-pole/single-throw (SPST) analog switch or 2-bit
bus switch. The device is fabricated with advanced sub-
micron CMOS technology to achieve high speed enable
and disable times and low On Resistance over a broad
■ Typical 7Ω On Resistance @ 5V VCC
VCC range. The device is specified to operate over the 1.65
■ Broad VCC operating range: 1.65V to 5.5V
to 5.5V VCC operating range. The device is organized as a
■ Rail-to-Rail signal handling
dual switch with independent CMOS compatible switch
enable (OE) controls. When OE is HIGH, the switch is ON
and Port A is connected to Port B. When OE is LOW, the
■ Power down high impedance control inputs
■ Control inputs are overvoltage tolerant
■ Control inputs are CMOS compatible
■ >300 MHz −3dB bandwidth
switch is OPEN and
a high-impedance state exists
between the two ports. The enable inputs tolerate voltages
up to 5.5V independent of the VCC operating range.
Ordering Code:
Product
Order
Number
Package
Code
Package Description
Supplied As
Number Top Mark
FSA266K8X
FSA266L8X
MAB08A
MAC08A
WB66
P4
8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide 3K Units on Tape and Reel
8-Lead MicroPak, 1.6 mm Wide 5K Units on Tape and Reel
8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide 3K Units on Tape and Reel
8-Lead MicroPak, 1.6 mm Wide 5K Units on Tape and Reel
NC7WB66K8X MAB08A
NC7WB66L8X MAC08A
WB66
P4
TinyLogic is a registered trademark of Fairchild Semiconductor Corporation.
MicroPak is a trademark of Fairchild Semiconductor Corporation.
© 2003 Fairchild Semiconductor Corporation
DS500373
www.fairchildsemi.com
Logic Symbol
Connection Diagrams
Pin Assignments for US8
(Top View)
Pad Assignments for MicroPak
Analog Symbol
(Top Thru View)
Pin Descriptions
Pin Names
Description
Switch Port A
Switch Port B
Control Input
A
B
OE
Function Table
Switch Enable Input (OE)
Function
Disconnect
L
H
B Connected to A
H = HIGH Logic Level
L = LOW Logic Level
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2
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions (Note 3)
Supply Voltage (VCC
)
−0.5V to +7.0V
−0.5V to VCC + 0.5V
−0.5V to +7.0V
DC Switch Voltage (VS)
DC Input Voltage (VIN) (Note 2)
DC Input Diode Current
@ (IIK) VIN < 0V
Supply Voltage (VCC
Control Input Voltage (VIN
Switch Input Voltage (VIN
)
1.65V to 5.5V
0V to 5.5V
)
)
0V to VCC
−50 mA
±128 mA
Switch Output Voltage (VOUT
Operating Temperature (TA)
)
0V to VCC
DC Switch Output Current (IOUT
)
−40°C to +85°C
DC VCC or Ground Current (ICC/IGND
)
±100 mA
Input Rise and Fall Time (tr, tf)
Control Input VCC = 1.65V−2.7V
Control Input VCC = 3.0V−3.6V
Control Input VCC = 4.5V−5.5V
Storage Temperature Range (TSTG
Junction Lead Temperature
under Bias (TJ)
)
−65°C to +150°C
0 ns/V to 20 ns/V
0 ns/V to 10 ns/V
0 ns/V to 5 ns/V
250°C/W
+150°C
+260°C
250 mW
Junction Lead Temperature (TL)
(Soldering, 10 Seconds)
Power Dissipation (PD) @ +85°C
SC70-6
Thermal Resistance (θJA)
Note 1: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Note 2: The input and output negative voltage ratings may be exceeded if
the input and output diode current ratings are observed.
Note 3: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
VCC
T
A = +25°C
TA= −40°C to +85°C
Symbol
Parameter
Units
Conditions
(V)
Min
Typ
Max
Min
Max
VIH
HIGH Level Input Voltage
1.65 to 1.95 0.75 VCC
0.75 VCC
0.7 VCC
V
V
2.3 to 5.5
1.65 to 1.95
2.3 to 5.5
0 to 5.5
0.7 VCC
VIL
LOW Level Input Voltage
Input Leakage Current
0.25 VCC
0.3 VCC
±0.1
±0.1
10
0.25VCC
0.3 VCC
±1.0
±1.0
10
IIN
µA
µA
0 ≤ VIN ≤ 5.5V
IOFF
RON
Switch OFF Leakage Current 1.65 to 5.5
Switch On Resistance
0 ≤ A, B ≤ VCC
6
7
VI = 0V, IO = 30 mA
VI = 2.4V, IO = −30 mA
VI = 4.5V, IO = −30 mA
VI = 0V, IO = 24 mA
VI = 3V, IO = −24 mA
VI = 0V, IO = 8 mA
VI = 2.3V, IO = −8 mA
VI = 0V, IO = 4 mA
VI = 1.65V, IO = −4 mA
(Note 4)
4.5
13.5
10
13.5
10
Ω
6
7.5
8.5
9
15
15
3.0
Ω
Ω
Ω
15
15
20
20
2.3
10.5
12.5
17
20
20
1.65
30
30
30
30
ICC
Quiescent Supply Current
All Channels ON or OFF
Analog Signal Range
VIN = VCC or GND
5.5
1
10
µA
I
OUT = 0
VCC
4.5
0
VCC
15
0
VCC
15
V
RRange On Resistance Over
Signal Range
8
I
I
I
I
I
I
I
I
O = −30 mA, 0 ≤ VI ≤ VCC
O = −24 mA, 0 ≤ VI ≤ VCC
O = −8 mA, 0 ≤ VI ≤ VCC
O = −4 mA, 0 ≤ VI ≤ VCC
O = −30 mA, VI = 3.15
O = −24 mA, VI = 2.1
O = −8 mA, VI = 1.6
3.0
15
30
30
Ω
Ω
(Note 4)(Note 5)
2.3
45
75
75
1.65
4.5
150
0.2
0.2
0.5
0.6
275
275
∆RON
On Resistance Match
Between Channels
(Note 4)(Note 7)
3.0
2.3
1.65
O = −4 mA, VI = 1.15
3
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DC Electrical Characteristics (Continued)
VCC
T
A = +25°C
TA= −40°C to +85°C
Symbol
Parameter
Units
Conditions
(V)
4.5
Min
Typ
2.5
8
Max
6
Min
Max
6
Rflat
On Resistance Flatness
(Note 4)(Note 5)(Note 6)
I
I
I
I
O = −30 mA, 0 ≤ VI ≤ VCC
O = −24 mA, 0 ≤ VI ≤ VCC
O = −8 mA, 0 ≤ VI ≤ VCC
O = −4 mA, 0 ≤ VI ≤ VCC
3.0
17.5
60
17.5
60
2.3
33
1.65
135
250
250
Note 4: Measured by the voltage drop between A and B pins at the indicated current through the switch. On Resistance is determined by the lower of the
voltages on the two (A or B) pins.
Note 5: Guaranteed by design.
Note 6: Flatness is defined as the difference between the minimum and maximum value of ON Resistance over the specified range of conditions.
Note 7: ∆RON = RON max − RON min measured at identical VCC, temperature and voltage levels.
AC Electrical Characteristics
VCC
TA= −40°C to +85°C
Figure
Symbol
Parameter
Units
Conditions
(V)
Min
Typ
0.35
0.7
1.1
2.0
2.0
2.5
3.2
5.7
2.6
3.4
4.2
6.2
Max
Number
tPHL, tPLH Propagation Delay Bus-to-Bus
(Note 8)
4.5 to 5.5
3.0 to 3.6
2.3 to 2.7
1.65 to 1.95
4.5 to 5.5
3.0 to 3.6
2.3 to 2.7
1.65 to 1.95
4.5 to 5.5
3.0 to 3.6
2.3 to 2.7
1.65 to 1.95
1.65 to 5.5
1.0
1.5
2.5
4.0
3.2
3.9
5.6
10
VI = OPEN
L = 50 pF, RU = RD = 500Ω
Figures
2, 1
ns
C
t
PZL, tPZH Output Enable Time
Turn on Time
0.8
1.2
1.5
2.5
0.8
1.5
2.0
3.0
VI = 0V for tPZH
Figures
2, 1
ns
ns
VI = 2 x VCC for tPZL
C
L = 50 pF, RU = RD = 500Ω
tPLZ, tPHZ Output Disable Time
Turn Off Time
4.1
5.0
6.9
10.5
VI = 0V for tPHZ
Figures
2, 1
VI = 2 x VCC for tPLZ
C
C
R
R
L = 50 pF, RU = RD = 500Ω
L = 0.1 nF, VGEN = 0V,
GEN = 0 Ω, f = 1 MHz
L = 50 Ω, CL = 5 pF,
Q
Charge Injection (Note 9)
Off Isolation (Note 10)
Crosstalk
pC
dB
Figure 3
Figure 4
Figure 5
Figure 8
OIRR
Xtalk
1.65 to 5.5
1.65 to 5.5
1.65 to 5.5
5
-55
−70
f = 10 MHz
L = 50 Ω, CL = 5 pF,
f = 10 MHz
dB
R
BW
−3dB Bandwidth
Total Harmonic Distortion
(Note 9)
>300
.016
MHz
%
R
L = 50 Ω
L = 600Ω
THD
R
0.5 VP-P
f = 600 Hz to 20 KHz
Note 8: This parameter is guaranteed by design. The switch contributes no propagation delay other than the RC delay of the On Resistance of the switch
and the 50 pF load capacitance.
Note 9: Guaranteed by design.
Note 10: Off Isolation = 20 log10 [VA/VBn
]
Capacitance
Symbol
CIN
Parameter
Typ
2.5
5
Max
Units
pF
Conditions
Figures
Control Pin Input Capacitance
V
V
V
CC = 0V
CI/O (OFF) Switch Port Off Capacitance
pF
CC = 5.0V
CC = 5.0V
Figure 6
Figure 7
CI/O (ON) Switch Port Capacitance when Switch is Enabled
10
pF
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4
AC Loading and Waveforms
Input driven by 50Ω source terminated in 50Ω
CL includes load and stray capacitance.
Input PRR = 1.0 MHz; tw = 500 ns
FIGURE 1. AC Test Circuit
FIGURE 2. AC Waveforms
FIGURE 3. Charge Injection Test
5
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AC Loading and Waveforms (Continued)
FIGURE 4. Off Isolation
FIGURE 5. Crosstalk
FIGURE 6. Channel Off Capacitance
FIGURE 7. Channel On Capacitance
FIGURE 8. Bandwidth
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6
Tape and Reel Specification
TAPE FORMAT for US8
Package
Tape
Section
Number
Cavities
125 (typ)
250
Cavity
Status
Empty
Filled
Cover Tape
Status
Designator
Leader (Start End)
Carrier
Sealed
K8X
Sealed
Trailer (Hub End)
75 (typ)
Empty
Sealed
TAPE DIMENSIONS inches (millimeters)
TAPE FORMAT for MicroPak
Package
Tape
Section
Number
Cavities
125 (typ)
250
Cavity
Status
Empty
Filled
Cover Tape
Status
Designator
Leader (Start End)
Carrier
Sealed
L8X
Sealed
Trailer (Hub End)
75 (typ)
Empty
Sealed
TAPE DIMENSIONS inches (millimeters)
7
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Tape and Reel Specification (Continued)
REEL DIMENSIONS inches (millimeters)
Tape
Size
A
B
C
D
N
W1
W2
W3
7.0
0.059
0.512
0.795
2.165 0.331 + 0.059/−0.000
0.567
W1 + 0.078/−0.039
(W1 + 2.00/−1.00)
8 mm
(177.8) (1.50) (13.00) (20.20) (55.00) (8.40 + 1.50/−0.00)
(14.40)
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8
Physical Dimensions inches (millimeters) unless otherwise noted
8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide
Package Number MAB08A
9
www.fairchildsemi.com
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
8-Lead MicroPak, 1.6 mm Wide
Package Number MAC08A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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10
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