FSD210M [FAIRCHILD]
Green Mode Fairchild Power Switch (FPSTM); 绿色模式飞兆功率开关（ FPSTM ）
| 型号： | FSD210M |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Green Mode Fairchild Power Switch (FPSTM) |
| 文件： | 总18页 (文件大小：392K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
www.fairchildsemi.com
FSD210, FSD200
TM
Green Mode Fairchild Power Switch (FPS )
Features
• Single Chip 700V Sense FET Power Switch
• Precision Fixed Operating Frequency (134kHz)
• Advanced Burst-Mode operation Consumes under 0.1W
at 265Vac and no load (FSD210 only)
OUTPUT POWER TABLE
(3)
230VAC ±15%
85-265VAC
PRODUCT
Open
Frame
Open
Frame
(1)
(1)
Adapter
Adapter
(2)
(2)
• Internal Start-up Switch and Soft Start
• Under Voltage Lock Out (UVLO) with Hysteresis
• Pulse by Pulse Current Limit
• Over Load Protection (OLP)
• Internal Thermal Shutdown Function (TSD)
• Auto-Restart Mode
FSD210
FSD200
5W
5W
5W
5W
7W
4W
4W
4W
4W
5W
7W
5W
FSD210M
FSD200M
7W
5W
7W
5W
• Frequency Modulation for EMI
• FSD200 does not require an auxiliary bias winding
Table 1. Notes: 1. Typical continuous power in a non-ven-
tilated enclosed adapter measured at 50°C ambient. 2.
Maximum practical continuous power in an open frame
design at 50°C ambient. 3. 230 VAC or 100/115 VAC with
doubler.
Applications
• Charger & Adaptor for Mobile Phone, PDA & MP3
• Auxiliary Power for White Goods, PC, C-TV & Monitor
Typical Circuit
Description
The FSD200 and FSD210 are integrated Pulse Width Modu-
lators (PWM) and Sense FETs specially designed for high
performance off-line Switch Mode Power Supplies (SMPS)
with minimal external components. Both devices are mono-
lithic high voltage power switching regulators which com-
bine an LDMOS Sense FET with a voltage mode PWM
control block. The integrated PWM controller features in-
clude: a fixed oscillator with frequency modulation for re-
duced EMI, Under Voltage Lock Out (UVLO) protection,
Leading Edge Blanking (LEB), optimized gate turn-on/turn-
off driver, thermal shut down protection (TSD), temperature
compensated precision current sources for loop compensa-
tion and fault protection circuitry. When compared to a dis-
crete MOSFET and controller or RCC switching converter
solution, the FSD200 and FSD210 reduce total component
count, design size, weight and at the same time increase effi-
ciency, productivity, and system reliability. The FSD200
eliminates the need for an auxiliary bias winding at a small
cost of increased supply power. Both devices are a basic plat-
form well suited for cost effective designs of flyback convert-
ers.
AC
IN
DC
OUT
Vstr
PWM
Drain
Vfb
Vcc
Source
Figure 1. Typical Flyback Application using FSD210
AC
IN
DC
OUT
Vstr
PWM
Drain
Vfb
Vcc
Source
Figure 2. Typical Flyback Application using FSD200
Rev.1.0.3
©2004 Fairchild Semiconductor Corporation
FSD210, FSD200
Internal Block Diagram
Vstr
8
L
Vcc
5
Internal
Bias
Voltage
Ref
Drain
H
7
UVLO
8.7/6.7V
Frequency
Modulation
Vck
OSC
SFET
DRIVER
250uA
5uA
S
R
Q
Vfb
4
BURST
BURST
V
LEB
OLP
Iover
Rsense
Vth
S
R
Q
Reset
V
SD
S/S
3mS
TSD
A/R
GND
1, 2, 3
Figure 3. Functional Block Diagram of FSD210
Vstr
8
HV/REG
Vcc
5
ON/OFF
Voltage
Ref.
INTERNAL
BIAS
Drain
7
7V
UVLO
OSC
Frequency
Modulation
Vck
SFET
DRIVER
250uA
5uA
S
R
Q
Vfb
4
BURST
BURST
V
LEB
OLP
Iover
Rsense
Vth
S
R
Q
Reset
V
SD
S/S
3mS
TSD
A/R
GND
1, 2, 3
Figure 4. Functional Block Diagram of FSD200 showing internal high voltage regulator
2
FSD210, FSD200
Pin Definitions
Pin Number
Pin Name
Pin Function Description
1, 2, 3
GND
Sense FET source terminal on primary side and internal control ground.
The feedback voltage pin is the inverting input to the PWM comparator with
nominal input levels between 0.5Vand 2.5V. It has a 0.25mA current source
connected internally while a capacitor and opto coupler are typically
connected externally. A feedback voltage of 4V triggers overload protection
(OLP). There is a time delay while charging between 3V and 4V using an
internal 5uA current source, which prevents false triggering under transient
conditions but still allows the protection mechanism to operate under true
overload conditions.
4
Vfb
FSD210
Positive supply voltage input. Although connected to an auxiliary
transformer winding, current is supplied from pin 8 (Vstr) via an internal
switch during startup (see Internal Block Diagram section). It is not until Vcc
reaches the UVLO upper threshold (8.7V) that the internal start-up switch
opens and device power is supplied via the auxiliary transformer winding.
FSD200
5
Vcc
This pin is connected to a storage capacitor. A high voltage regulator
connected between pin 8 (Vstr) and this pin, provides the supply voltage to
the FSD200 at startup and when switching during normal operation. The
FSD200 eliminates the need for auxiliary bias winding and associated
external components.
The Drain pin is designed to connect directly to the primary lead of the
transformer and is capable of switching a maximum of 700V. Minimizing the
length of the trace connecting this pin to the transformer will decrease
leakage inductance.
7
8
Drain
Vstr
The startup pin connects directly to the rectified AC line voltage source for
both the FSD200 and FSD210. For the FSD210, at start up the internal
switch supplies internal bias and charges an external storage capacitor
placed between the Vcc pin and ground. Once this reaches 8.7V, the
internal current source is disabled. For the FSD200, an internal high voltage
regulator provides a constant supply voltage.
Pin Configuration
7-DIP
7-LSOP
GND
GND
GND
Vfb
Vstr
1
2
8
7
Drain
3
4
5
Vcc
Figure 5. Pin Configuration (Top View)
3
FSD210, FSD200
Absolute Maximum Ratings
(Ta=25°C unless otherwise specified)
Parameter
Symbol
Value
10
Unit
V
Maximum Supply Voltage (FSD200)
Maximum Supply Voltage (FSD210)
Input Voltage Range
V
CC,MAX
CC,MAX
V
20
V
V
−0.3 to V
STOP
V
FB
Operating Junction Temperature.
Operating Ambient Temperature
Storage Temperature Range
T
+150
°C
°C
°C
J
T
A
−25 to +85
−55 to +150
T
STG
Thermal Impedance
Parameter
7DIP
Symbol
Value
Unit
(1)
θJA
74.07(3)
60.44(4)
22.00
°C/W
°C/W
°C/W
Junction-to-Ambient Thermal
(1)
θJA
(2)
Junction-to-Case Thermal
θJC
7LSOP
(1)
θJA
-
-
-
°C/W
°C/W
°C/W
Junction-to-Ambient Thermal
Junction-to-Case Thermal
(1)
θJA
(2)
θJC
Note:
1. Free standing without heat sink.
2. Measured on the GND pin close to plastic interface.
2
3. Soldered to 100mm copper clad.
2
4. Soldered to 300mm copper clad.
4
FSD210, FSD200
Electrical Characteristics
(Ta=25°C unless otherwise specified)
Parameter
Symbol
Condition
Min.
Typ. Max.
Unit
Sense FET SECTION
Drain-Source Breakdown Voltage
Startup Voltage (Vstr) Breakdown
Off-State Current
BV
BV
V
V
= 0V, I = 100µA
700
-
-
-
-
V
V
DSS
CC
DS
D
700
STR
I
= 560V
-
-
-
-
-
-
100
32
48
-
µA
Ω
DSS
Tj = 25°C, I = 25mA
28
42
100
50
D
On-State Resistance
R
DS(ON)
Tj = 100°C, I = 25mA
Ω
D
Rise Time
T
V
V
= 325V, I = 50mA
ns
ns
R
DS
DS
D
Fall Time
T
= 325V, l = 25mA
-
F
D
CONTROL SECTION
Output Frequency
Output Frequency Modulation
Feedback Source Current
Maximum Duty Cycle
Minimum Duty Cycle
F
Tj = 25°C
Tj = 25°C
Vfb = 0V
Vfb = 3.5V
Vfb = 0V
126
-
134
±4
0.25
65
0
142
-
kHz
kHz
mA
%
OSC
F
MOD
I
0.22
60
0
0.28
70
0
FB
D
MAX
D
%
MIN
V
6.3
5.3
8.0
6.0
-
7
7.7
6.7
9.4
7.4
-
V
START
UVLO Threshold Voltage (FSD200)
UVLO Threshold Voltage (FSD210)
V
After turn on
6
V
STOP
V
8.7
6.7
7
V
START
V
After turn on
-
V
STOP
Supply Shunt Regulator (FSD200)
Internal Soft Start Time
V
V
CCREG
T
S/S
-
3
-
ms
BURST MODE SECTION
V
0.58
0.5
-
0.64
0.58
60
0.7
0.64
-
V
V
BURH
Burst Mode Voltage
V
Tj = 25°C
Tj = 25°C
BURL
Hysteresis
mV
PROTECTION SECTION
Drain to Source Peak Current Limit
Current Limit Delay(1)
I
0.275 0.320 0.365
A
ns
°C
V
OVER
T
-
220
145
4.0
5
-
160
4.5
7
CLD
Thermal Shutdown Temperature (Tj)(1)
Shutdown Feedback Voltage
Feedback Shutdown Delay Current
Leading Edge Blanking Time(2)
TOTAL DEVICE SECTION
T
125
3.5
3
SD
SD
V
-
I
Vfb = 4.0V
µA
ns
DELAY
T
200
-
-
LEB
Operating Supply Current (FSD200)
Operating Supply Current (FSD210)
Start Up Current (FSD200)
I
I
Vcc = 7V
Vcc = 11V
Vcc = 0V
Vcc = 0V
Vcc = 0V
-
-
600
700
1
-
-
µA
µA
mA
µA
V
OP
OP
I
I
-
1.2
900
-
START
START
Start Up Current (FSD210)
-
700
-
Vstr Supply Voltage
20
Note:
1. These parameters, although guaranteed, are not 100% tested in production
2. This parameter is derived from characterization
5
FSD210, FSD200
Comparison Between FSDH565 and FSD210
Function
FSDH0565
FSD210
FSD210 Advantages
Soft-Start
not applicable
3mS
• Gradually increasing current limit
during soft-start further reduces peak
current and voltage component
stresses
• Eliminates external components used
for soft-start in most applications
• Reduces or eliminates output
overshoot
Switching Frequency
Frequency Modulation
Burst Mode Operation
100kHz
134kHz
±4kHz
• Smaller transformer
not applicable
not applicable
• Reduced conducted EMI
Yes-built into
controller
• Improve light load efficiency
• Reduces no-load consumption
• Transformer audible noise reduction
Drain Creepage at
Package
1.02mm
3.56mm DIP
3.56mm LSOP
• Greater immunity to acting as a result
of build-up of dust, debris and other
contaminants
6
FSD210, FSD200
Typical Performance Characteristics
(These characteristic graphs are normalized at Ta=25℃)
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-25
-25
-25
0
25
50
75
100
125
-25
0
25
50
75
100
125
Junction Temperature (℃)
Junction Temperature (℃)
Frequency vs. Temp
Operating Current vs. Temp
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0
25
50
75
100
125
-25
0
25
50
75
100
125
Junction Temperature (℃)
Junction Temperature (℃)
Peak Current Limit vs. Temp
Feedback Source Current vs. Temp
1.20
1.00
0.80
0.60
0.40
0.20
0.00
1.20
1.00
0.80
0.60
0.40
0.20
0.00
0
25
50
75
100 125
-25
0
25
50
75
100 125
Junction Temperature (℃)
Junction Temperature (℃)
Vstop Voltage vs. Temp
Vstart Voltage vs. Temp
7
FSD210, FSD200
Typical Performance Characteristics (Continued)
(These characteristic graphs are normalized at Ta=25℃)
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-25
0
25
50
75
100
125
-25
0
25
50
75
100
125
Junction Temperature (℃)
Junction Temperature (℃)
On State Resistance vs. Temp
Breakdown Voltage vs. Temp
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-25
0
25
50
75
100
125
-25
0
25
50
75
100
125
Junction Temperature (℃)
Junction Temperature (℃)
Vcc Regulation Voltage vs. Temp (for FSD200)
Shutdown Feedback Voltage vs. Temp
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-25
0
25
50
75
100
125
-25
0
25
50
75
100
125
Junction Temperature (℃)
Junction Temperature (℃)
Start Up Current vs. Temp (for FSD210)
Start Up Current vs. Temp (for FSD200)
8
FSD210, FSD200
Functional Description
Vin,dc
1. Startup : At startup, the internal high voltage current
source supplies the internal bias and charges the external
Vcc capacitor as shown in figure 7. In the case of the
FSD210, when Vcc reaches 8.7V the device starts switching
and the internal high voltage current source is disabled (see
figure 1). The device continues to switch provided that Vcc
does not drop below 6.7V. For FSD210, after startup, the
bias is supplied from the auxiliary transformer winding. In
the case of FSD200, Vcc is continuously supplied from the
external high voltage source and Vcc is regulated to 7V by
an internal high voltage regulator (HVReg), thus eliminating
the need for an auxiliary winding (see figure 2).
Istr
Vstr
i
=
i
Istr-max 1 00uA
=
Istr-max
1 0 0 u A
J-FET
Vcc
max
100uA
UVLO
Vref
FSD2xx
Vcc
UVLO
start
Vin,dc
Vin,dc
Vcc must not drop
to UVLO stop
Istr
Istr
UVLO
stop
Vstr
Vstr
HV
Auxiliary winding
voltage
Vcc
Vcc
L
Reg.
H
7V
8.7V/
6.7V
FSD210
FSD200
t
Figure 7. Charging the Vcc capacitor through Vstr
Figure 6. Internal startup circuit
Calculating the Vcc capacitor is an important step to design-
ing in the FSD200/210. At initial start-up in both the
FSD200/210, the stand-by maximum current is 100uA, sup-
plying current to UVLO and Vref Block. The charging cur-
rent (i) of the Vcc capacitor is equal to Istr - 100uA. After
Vcc reaches the UVLO start voltage only the bias winding
supplies Vcc current to device. When the bias winding volt-
age is not sufficient, the Vcc level decreases to the UVLO
stop voltage. At this time Vcc oscillates. In order to prevent
this ripple it is recommended that the Vcc capacitor be sized
between 10uF and 47uF.
3. Leading edge blanking (LEB) : At the instant the inter-
nal Sense FET is turned on, there usually exists a high cur-
rent spike through the Sense FET, caused by the primary side
capacitance and secondary side rectifier diode reverse recov-
ery. Exceeding the pulse-by-pulse current limit could cause
premature termination of the switching pulse (see Protection
Section). To counter this effect, the FPS employs a leading
edge blanking (LEB) circuit. This circuit inhibits the over
current comparator for a short time (TLEB) after the Sense
FET is turned on.
2. Feedback Control : The FSD200/210 are both voltage
mode devices as shown in Figure 8. Usually, a H11A817
optocoupler and KA431 voltage reference (or a FOD2741
integrated optocoupler and voltage reference) are used to
implement the isolated secondary feedback network. The
feedback voltage is compared with an internally generated
sawtooth waveform, directly controlling the duty cycle.
When the KA431 reference pin voltage exceeds the internal
reference voltage of 2.5V, the optocoupler LED current
increases pulling down the feedback voltage and reducing
the duty cycle. This event will occur when either the input
voltage increases or the output load decreases.
OSC
Vcc
Vref
5uA
0.25mA
Gate
driver
FB
Vfb
Vo
4
Cfb
R
KA431
OLP
VSD
Figure 8. PWM and feedback circuit
4. Protection Circuit : The FSD200/210 has 2 self protec-
tion functions: over load protection (OLP) and thermal shut-
down (TSD). Because these protection circuits are fully
integrated into the IC with no external components, system
9
FSD210, FSD200
reliability is improved without a cost increase. If either of
these thresholds are triggered, the FPS starts an auto-restart
cycle. Once the fault condition occurs, switching is termi-
nated and the Sense FET remains off. This causes Vcc to
fall. When Vcc reaches the UVLO stop voltage
to detect the temperature of the Sense FET. When the tem-
perature exceeds approximately 145°C, thermal shutdown is
activated.
(6.7V:FSD210, 6V:FSD200), the protection is reset and the
internal high voltage current source charges the Vcc capaci-
tor. When Vcc reaches the UVLO start voltage
Vfb
under Vstop of UVLO
(8.7V:FSD210,7V:FSD200), the device attempts to resume
normal operation. If the fault condition is no longer present
start up will be successful. If it is still present the cycle is
repeated (see figure 10).
OLP
4V
3V
FPS Switching Area
Idelay (5uA) charges Cfb
IC Reset
OSC
t
S
R
Q
5uA
250uA
R
GATE
DRIVER
+
-
t1
t2
t3
Vfb
4
3V
t1<<t2, t3
t1 = -1/RCΧ ln( 1-v(t1)/R )
t2 = CfbΧ {v(t1+t2)-v(t1)}/ Idelay
Cfb
v(t1)=3V
OLP
S
Q
FSD2xx
OLP, TSD
Protection Block
R
RESET
Vth 4V
TSD
A/R
Figure 10. Over load protection delay
5. Soft Start : FSD200/210 has an internal soft start circuit
that gradually increases current through the Sense FET as
shown in figure 11. The soft start time is 3msec in FSD200/
210.
Figure 9. Protection block
4.1 Over Load Protection (OLP) : Over load protection
occurs when the load current exceeds a pre-set level due to
an abnormal situation. If this occurs, the protection circuit
should be triggered to protect the SMPS. It is possible that a
short term load transient can occur under normal operation.
In order to avoid false shutdowns, the over load protection
circuit is designed to trigger after a delay. Therefore the
device can differentiate between transient over loads and
true fault conditions. The maximum input power is limited
using the pulse-by-pulse current limit feature. If the load
tries to
I(A)
3mS
0.3A
Iover
0.25A
0.2A
t
draw more than this, the output voltage will drop below its
set value. This reduces the optocoupler LED current which
in turn reduces the photo-transistor current (see figure 9).
Therefore, the 250uA current source will charge the feed-
back pin capacitor, Cfb, and the feedback voltage, Vfb, will
increase. The input to the feedback comparator is clamped at
3V. Once Vfb reaches 3V, the device switches at maximum
power, the 250uA current source is blocked and the 5uA
source continues to charge Cfb. Once Vfb reaches 4V,
switching stops.and overload protection is triggered. The
resultant shutdown delay time is set by the time required to
charge Cfb from 3Vto 4Vwith 5uA as shown in Fig. 10.
FSD200/210
Figure 11. Internal Soft Start
6. Burst operation : In order to minimize the power dissipa-
tion in standby mode, the FSD200/210 implements burst
mode functionality (see figure 12). As the load decreases, the
feedback voltage decreases. As shown in figure 13, the
device automatically enters burst mode when the feedback
(0.58V). At this point switching
stops and the output voltages start to drop at a rate dependant
on standby current load. This causes the feedback voltage to
voltage drops below V
BURL
rise. Once it passes V
(0.64V) switching starts again.
BURH
The feedback voltage falls and the process repeats. Burst
mode operation alternately enables and disables switching of
the power Sense FET thereby reducing switching loss in
4.2 Thermal Shutdown (TSD) : The Sense FET and the
control IC are integrated, making it easier for the control IC
10
FSD210, FSD200
standby mode.
Internal
Oscillator
OSC
138kHz
GATE
DRIVER
S
R
Q
5uA
250uA
Drain to
Source
voltage
4
on/off
Vfb
0.64V
/0.58V
FSD2xx
Burst Operation Block
Drain to
Source
current
Vds
Waveform
Figure 12. Circuit for burst operation
8kHz
130kHz
134kHz
138kHz
Vo
Voset
Turn-off
point
Turn-on
Figure 14. Frequency Modulation Waveforms
VFB
0.64V
0.58V
CISPR22Q(PK)
CISPR22A(AV)
Ids
Vds
time
Frequency(MHz)
Figure 13. Burst mode operation
Figure 15. FSDH0165 Full Range EMI scan(100kHz, no
Frequency Modulation) with charger set
7. Frequency Modulation : EMI reduction can be accom-
plished by modulating the switching frequency of a SMPS.
Frequency modulation can reduce EMI by spreading the
energy over a wider frequency range. The amount of EMI
reduction is directly related to the level of modulation
(Fmod) and the rate of modulation. As can be seen in Figure
14, the frequency changes from 130kHz to 138kHz in 4mS
for the FSD200/FSD210. Frequency modulation allows the
use of a cost effective inductor instead of an AC input mode
choke to satisfy the requirements of world wide EMI limits.
CISPR22Q(PK)
CISPR22A(AV)
Frequency(MHz)
Figure 16. FSD210 Full Range EMI scan(134kHz, with Fre-
quency Modulation) with charger set
11
FSD210, FSD200
Typical application circuit
Application
Output power
3.38W
Input voltage
Output voltage (Max current)
Cellular Phone Charger
Universal input (85-265Vac)
5.2V (650mA)
Features
• High efficiency (>67% at Universal Input)
• Low zero load power consumption (<100mW at 240Vac) with FSD210
• Low component count
• Enhanced system reliability through various protection functions
• Internal soft-start (3ms)
• Frequency Modulation for low EMI
Key Design Notes
• The constant voltage (CV) mode control is implemented with resistors, R8, R9, R10 and R11, shunt regulator, U2, feedback
capacitor, C9 and opto-coupler, U3.
• The constant current (CC) mode control is designed with resistors, R8, R9, R15, R16, R17 and R19, NPN transistor, Q1 and
NTC, TH1. When the voltage across current sensing resistors, R15,R16 and R17 is 0.7V, the NPN transistor turns on and the
current through the opto coupler LED increases. This reduces the feedback voltage and duty ratio. Therefore, the output
voltage decreases and the output current is regulated.
• The NTC(negative thermal coefficient) is used to compensate the temperature characteristics of the transistor Q1.
1. Schematic
C6 152M-Y, 250Vac
R6
R7
4.7M, 1/4W
4.7M 1/4W
0
L3
L1 330uH
R1 4.7k
D7
SB260
TX1
Vo
1
2
7
8
4uH
Fuse
R3
47k
(5.2V/0.65A)
AC
AC
R9
56R
C7
330uF 16V
C8
330uF 16V
1W, 10R
D1
1N4007
D2
1N4007
C3
102k 1kV
R10
2.2k
R4
47k
R8
510R
C1
U3
C2
H11A817B
4.7UF 400V
4.7uF 400V
.
D3
D4
1N4007
1N4007
C9 470nF
D5
UF4007
C10
4.7uF 50V
U2
TL431
1
Q1
KSP2222A
R12
2k
D6
R5
5
0
Vcc
1N4148 39R
8
4
H11A817B
Vstr
Vfb
TH1
10k
3
4
U1
FSD210
R19
510R
C5
33uF 50V
R15 3R0
R16 3R0
R17 3R0
0
For FSD21x
C4
100nF
12
FSD210, FSD200
2. Demo Circuit Part List
Reference
Part #
Quantity Description
Requirement/Comment
DO41 Type
D1,D2,D3,D4
1N4007
UF4007
1N4148
SB260
4
1
1
1
1
1
1A/1000V Junction Rectifier
D5
D6
D7
Q1
U1
1A/1000V Ultra Fast Diode
10mA/100V Junction Diode
2A/60V Schottky Diode
Ic=600mA, Vce=30V
0.5A/700V
DO41 Type
D0-213 Type
D0-41 Type
KSP2222A
TO-92 Type
FSD210
Iover=0.3A, Fairchildsemi
(FSD200)
U2
U3
KA431AZ
H11A817A
1
1
Vref=2.495V(Typ.)
CTR 80~160%
TO-92 Type, LM431
-
3. Transformer Schematic Diagram
2mm
2mm
1
2
3
8
7
6
5
W4
W3
W2
W1
.
4
CORE : EE1616
BOBBIN : EE1616(H)
4. Winding Specification
No.
Pin (S F)
Wire
Turns
Winding Method
→
W1
1
2
0.16
Φ Χ
1
99 Ts
SOLENOID WINDING
→
INSULATION : POLYESTER TAPE t=0.025mm / 10mm, 2Ts
W2
4
3
0.16
Φ Χ
1
18 Ts
CENTER SOLENOID
WINDING
→
INSULATION : POLYESTER TAPE t=0.025mm / 10mm, 2Ts
open 0.16 50 Ts SOLENOID WINDING
W3
W4
1
1
→
Φ Χ
INSULATION : POLYESTER TAPE t=0.025mm / 10mm, 3Ts
0.40 9 Ts SOLENOID WINDING
8
7
1
→
Φ Χ
INSULATION : POLYESTER TAPE t=0.025mm / 10mm, 3Ts
5. Electrical Characteristics
ITEM
TERMINAL
1 – 2
SPECIFICATION
1.6mH
REMARKS
INDUCTANCE
LEAKAGE L
1kHz, 1V
1 – 2
50uH
3,4,7,8short
100kHz, 1V
13
FSD210, FSD200
Typical application circuit
Application
Output power
1.2W
Input voltage
Universal dc input
(100 ~ 375Vac)
Output voltage (Max current)
Non Isolation Buck
12V (100mA)
Features
• Non isolation buck converter
• Low component count
• Enhanced system reliability through various protection functions
Key Design Notes
• The output voltage(12V) is regulated with resistors, R1, R2 and R3, zener diode, D3, the transistor, Q1 and the capacitor,
C2. While the FSD210 is off diodes, D1 and D2, are on. At this time the output voltage, 12V, can be sensed by the feedback
components above. This output is also used with bias voltage for the FSD210.
• R, 680K, is to prevent the OLP(over load protection) at startup.
• R, 8.2K, is a dummy resistor to regulate output voltage in light load.
1. Schematic
VINDC
D2
5
Vcc
8
4
UF4004
Vstr
Vfb
R2
110
U1
FSD21x
D3(ZD)
1N759A
C1
C5
47uF 50V
4.7uF/400V
R1 110
R
680K
C2
47nF/50V
Q1
KSP2222A
R3
VOUT(12V/100mA)
D1
750
L1
GND
1mH
UF4004
C4
R
1000uF 16V
8.2K
GND
0
2. Demo Circuit Part List
Reference
D1,D2,
Q1
Part #
Quantity Description
Requirement/Comment
UF4007
2
1
1
1
1A/1000V Ultra Fast Diode
Ic=200mA, Vcc=40V
DO41 Type
TO-92 Type
DO-35 Type
Iover=0.3A
KSP2222A
1N759A
ZD1
12VZD/0.5W
0.5A/700V
U1
FSD210
14
FSD210, FSD200
Layout Considerations (for Flyback Convertor)
Copper area for heatsink
#1 : GND
#2 : GND
#3 : GND
#4 : Vfb
#5 : Vcc
#6 : N.C.
#7 : Drain
#8 : Vstr
Figure 17. Layout Considerations for FSD2x0 using 7DIP
15
FSD210, FSD200
Package Dimensions
7-DIP
16
FSD210, FSD200
Package Dimensions (Continued)
7-LSOP
17
FSD210, FSD200
Ordering Information
Product Number
FSD210
Package
7DIP
Rating
Topr (°C)
700V, 0.5A
700V, 0.5A
700V, 0.5A
700V, 0.5A
−25°C to +85°C
−25°C to +85°C
−25°C to +85°C
−25°C to +85°C
FSD200
7DIP
FSD210M
FSD200M
7LSOP
7LSOP
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER
DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
6/21/04 0.0m 001
2004 Fairchild Semiconductor Corporation
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