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FSEZ2016_10 [FAIRCHILD]

Low-Power Green-Mode EZSWITCH without Secondary Side Feedback Circuitry; 低功耗绿色模式EZSWITCH无需次级侧反馈电路
FSEZ2016_10
型号： FSEZ2016_10
厂家： FAIRCHILD SEMICONDUCTOR    FAIRCHILD SEMICONDUCTOR
描述：

Low-Power Green-Mode EZSWITCH without Secondary Side Feedback Circuitry
低功耗绿色模式EZSWITCH无需次级侧反馈电路
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中文：  中文翻译
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January 2010  
FSEZ2016 — Low-Power Green-Mode EZSWITCH without  
Secondary Side Feedback Circuitry  
Features  
Description  
This highly integrated PWM controller provides several  
features to enhance the performance of low-power  
flyback converters. To minimize standby power  
consumption, a proprietary green-mode function provides  
off-time modulation to linearly decrease the switching  
frequency under light-load and zero-load conditions. This  
green mode enables the power supply to meet  
international power conservation requirements. The  
supply voltage VDD is also used for feedback  
compensation, to regulate the output voltage without  
requiring a conventional TL431 and a photo-coupler. A  
typical output CV/CC characteristic is shown in Figure 1.  
ƒ Linearly Decreasing PWM Frequency  
ƒ Green Mode Under Light-load and Zero-Load  
Conditions  
ƒ Constant Voltage (CV) and Constant Current (CC)  
around ±25% without Secondary Side Feedback  
Circuitry  
ƒ Precise Constant Voltage (CV) at ±5% by Secondary  
Side Feedback Circuitry  
ƒ Low Startup Current: 8μA  
ƒ Low Operating Current: 3.6mA  
ƒ Leading-Edge Blanking (LEB)  
ƒ Constant Power Limit  
Another advantage of the FSEZ2016 is that the typical  
startup current is only 8μA, while the typical operating  
current can be as low as 3.6mA. A large startup  
resistance can be used to achieve even higher power  
conversion efficiency.  
ƒ Universal AC Input Range  
ƒ Synchronized Slope Compensation  
ƒ 140°C OTP Sensor with Hysteresis  
ƒ VDD Over-Voltage Clamping  
ƒ Cycle-by-Cycle Current Limiting  
ƒ Under-Voltage Lockout (UVLO)  
ƒ Fixed PWM Frequency with Hopping  
ƒ Gate Output Maximum Voltage Clamped at 17V  
FSEZ2016 integrates frequency hopping function  
internally to reduce EMI emissions with minimum line  
filters. Also, built-in synchronized slope compensation  
maintains the stability of peak current-mode control.  
Proprietary internal compensation ensures constant  
output power limiting over a universal range of AC input  
voltages, from 90VAC to 264VAC  
.
The FSEZ2016 provides many protection functions.  
Pulse-by-pulse current limiting ensures constant output  
current, even if a short circuit occurs. The internal  
protection circuit disables PWM output if VDD exceeds  
22.7V. The gate output is clamped at 17V to protect the  
power MOS from over-voltage damage. The built-in  
over-temperature protection (OTP) function shuts down  
the controller at 140°C with a 30°C hysteresis.  
Applications  
General-purpose switching-mode power supplies and  
flyback power converters, such as:  
ƒ Battery Chargers for Cellular Phones, Cordless  
Phones, PDAs, Digital Cameras, Power Tools  
ƒ Power Adapters for Ink Jet Printers, Video Game  
Consoles, Portable Audio Players  
Maximum  
With Secondary Feedback  
Minimum  
Without Secondary Feedback  
Vo  
8
ƒ Open-Frame SMPS for TV/DVD Standby and  
Auxiliary Supplies, Home Appliances, Consumer  
Electronics  
7
6
5
4
3
2
1
0
ƒ Replacement for Linear Transformers and RCC SMPS  
ƒ PC 5V Standby Power  
Io  
0
0.2  
0.4  
0.6  
0.8  
1
1.2  
1.4  
1.6  
1.8  
2
Figure 1. Typical Output V-I Characteristic  
© 2008 Fairchild Semiconductor Corporation  
FSEZ2016 • Rev. 1.0.1  
www.fairchildsemi.com  
Ordering Information  
Operating  
Temperature Range  
Part Number  
Package  
Packing Method  
Eco Status  
7-Lead, Dual Outline  
Package (DIP-7)  
FSEZ2016NY  
Green  
Tube  
-40°C to +105°C  
For Fairchild’s definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.  
Application Diagram  
Figure 2. Typical Application  
Internal Block Diagram  
Figure 3. Functional Block Diagram  
© 2008 Fairchild Semiconductor Corporation  
www.fairchildsemi.com  
FSEZ2016 • Rev. 1.0.1  
2
Marking Information  
1’st line  
Z: Assembly plant code  
X: Year code  
Y: Week code  
TT: Die run code  
3’rd line  
T: Package type (N=DIP)  
P: Y=Green package  
M: Manufacture flow code  
Figure 4. Top Mark  
Pin Configuration  
Figure 5. Pin Assignments  
Pin Definitions  
Pin #  
Name  
SOURCE  
GND  
Description  
1
2
3
Power MOSFET source. This is the high-voltage power MOSFET source.  
Ground  
VDD  
Power supply  
The FB pin provides feedback information to the internal PWM comparator. This  
feedback is used to control the duty cycle. When no feedback is provided, this pin is  
left open.  
4
FB  
5
6
8
NC  
NC  
No connection  
No connection  
DRAIN  
Power MOSFET drain. This is the high-voltage power MOSFET drain.  
© 2008 Fairchild Semiconductor Corporation  
FSEZ2016 • Rev. 1.0.1  
www.fairchildsemi.com  
3
Absolute Maximum Ratings  
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be  
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.  
In addition, extended exposure to stresses above the recommended operating conditions may affect device  
reliability. The absolute maximum ratings are stress ratings only.  
Symbol  
VDD  
Parameter  
Min.  
Max.  
30  
Unit  
V
DC Supply Voltage(1, 2)  
VFB  
Input Voltage to FB Pin  
Input Voltage to Sense Pin  
Power Dissipation (TA=25°C)  
-0.3  
-0.3  
7.0  
7.0  
1.2  
98.7  
150  
150  
260  
2
V
VSENSE  
PD  
V
W
θJA  
Thermal Resistance (Junction to Air)  
Operating Junction Temperature  
°C/W  
°C  
TJ  
TSTG  
TL  
-40  
-55  
Storage Temperature Range  
°C  
Lead Temperature (Wave Soldering or IR, 10 Seconds)  
°C  
Human Body Model (JEDEC:JESD22_A114)  
Charged Device Model (JEDEC:JESD22_C101)  
KV  
KV  
Electrostatic  
Discharge Capability  
ESD  
1
Notes:  
1. All voltage values, except differential voltages, are given with respect to GND pin.  
2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.  
© 2008 Fairchild Semiconductor Corporation  
FSEZ2016 • Rev. 1.0.1  
www.fairchildsemi.com  
4
Electrical Characteristics  
Unless otherwise noted, VDD=15V and TA=25°C.  
Symbol  
Parameter  
Conditions  
Min. Typ. Max. Units  
VDD Section  
With Secondary Feedback  
20.0  
V
VDD-OP  
Continuously Operation Voltage  
Without Secondary Feedback  
22.7  
VDD-ON  
VDD-OFF  
IDD-ST  
Turn-on Threshold Voltage  
Turn-off Threshold Voltage  
Startup Current  
16  
17  
8.0  
8
18  
8.5  
20  
V
V
7.5  
VDD=VDD-ON – 0.1V  
CL=1nF  
μA  
mA  
IDD-OP  
Operating Supply Current  
3.6  
4.6  
VDD Low-threshold Voltage to Exit  
Green-off Mode  
VDD-OFF  
+1.3  
VDD-G-OFF  
V
Feedback Input Section  
Input-Voltage to Current-Sense  
Attenuation  
AV  
0.35  
4.6  
V/V  
ZFB  
Input Impedance  
IFB=0.1mA to 0.2mA  
kΩ  
V
VFB-OPEN Open-Loop Voltage  
4.5  
FB is Open  
IFB=0.4mA  
20.7  
18.4  
22.7  
20.4  
24.7  
22.4  
V
VDD-FB  
VDD Feedback Threshold Voltage  
V
Current-Sense Section  
tPD  
Propagation Delay  
100  
0.83  
0.74  
0.59  
1.15  
1.04  
0.84  
310  
150  
ns  
V
VDD=18V  
VSTHVA  
Current Limit Valley Threshold Voltage VDD=15V  
VDD=10V  
V
V
VDD=18V  
V
VSTHFL  
Current Limit Flat Threshold Voltage  
Leading-Edge Blanking Time  
VDD=15V  
VDD=10V  
V
V
tLEB  
220  
400  
ns  
Figure 6. Saw Limit  
© 2008 Fairchild Semiconductor Corporation  
FSEZ2016 • Rev. 1.0.1  
www.fairchildsemi.com  
5
Electrical Characteristics (Continued)  
Unless otherwise noted, VDD=15V and TA=25°C.  
Symbol  
Parameter  
Conditions  
Min.  
Typ.  
Max.  
Units  
Oscillator Section  
Center Frequency  
Hopping Range  
60  
65  
±4.7  
4
70  
fOSC  
Frequency  
kHz  
±4.1  
±5.3  
tHOP  
fOSC-G  
VFB-N  
Hopping Period  
ms  
KHz  
V
Green Mode Frequency  
14.5  
2.3  
17.0  
2.6  
19.5  
2.9  
Green Mode Entry FB Voltage  
VFB-N  
0.75  
-
VFB-G  
Green Mode Ending FB Voltage  
V
VFB-Z  
SG  
Zero Duty Cycle FB Voltage  
1.4  
70  
V
Hz/mV  
%
Green Mode Modulation Slope  
Frequency Variation vs. VDD Deviation  
40  
100  
5
fDV  
VDD=10 to 22V  
TA= -20 to 85°C  
Frequency Variation vs. Temperature  
Deviation  
fDT  
1.5  
5.0  
%
Internal MOSFET Section  
DCYMAX  
BVDSS  
Maximum Duty Cycle  
69  
74  
79  
%
V
Drain-Source Breakdown Voltage  
ID=250μA, VGS=0V  
600  
ID=250μA,  
Referenced to 25°C  
Breakdown Voltage Temperature  
Coefficient  
ΔBVDSS/ΔTJ  
0.6  
V/°C  
Maximum Continuous Drain-Source  
Diode Forward Current  
IS  
1
A
Maximum Pulsed Drain-Source Diode  
Forward Current  
ISM  
4
11.5  
5
A
Ω
RDS(ON)  
Static Drain-Source On-Resistance  
ID=0.5A, VGS=10V  
9.3  
VDS=600V, VGS=0V,  
μA  
TC=25°C  
IDSS  
Drain-Source Leakage Current  
VDS=480V, VGS=0V,  
TC=100°C  
10  
24  
μA  
VDS=300V, ID=1.1A,  
RG=25Ω  
tD-ON  
Turn-on Delay Time  
7
ns  
tr  
tD-OFF  
tf  
Rise Time  
21  
13  
27  
52  
36  
64  
ns  
ns  
ns  
Turn-off Delay Time  
Fall Time  
VGS=0V, VDS=25V,  
fS=1MHz  
CISS  
Input Capacitance  
Output Capacitance  
130  
19  
170  
25  
pF  
pF  
COSS  
Over Temperature Protection (OTP)  
TOTP Protection Junction Temperature  
140  
110  
°C  
°C  
TOTP-RESTART Restart Junction Temperature  
© 2008 Fairchild Semiconductor Corporation  
FSEZ2016 • Rev. 1.0.1  
www.fairchildsemi.com  
6
Typical Performance Characteristics  
17  
16.8  
16.6  
16.4  
16.2  
16  
8.4  
8.2  
8
7.8  
7.6  
7.4  
-40  
-25  
-10  
5
20  
35  
50  
65  
80  
95  
110  
125  
-40  
-25  
-10  
5
20  
35  
50  
65  
80  
95  
110  
125  
Temperature (℃ )  
Temperature (℃ )  
Figure 7. Turn-on Threshold Voltage (VDD-ON  
)
Figure 8. Turn-off Threshold Voltage (VDD-OFF  
vs. Temperature  
)
vs. Temperature  
14  
12  
10  
8
3
2.8  
2.6  
2.4  
2.2  
2
6
4
-40  
-25  
-10  
5
20  
35  
50  
65  
80  
95  
110  
125  
-40  
-25  
-10  
5
20  
35  
50  
65  
80  
95  
110  
125  
Temperature (℃ )  
Temperature (℃ )  
Figure 9. Startup Current (IDD-ST  
vs. Temperature  
)
Figure 10. Operating Supply Current (IDD-OP  
)
vs. Temperature  
66  
65  
64  
63  
62  
61  
60  
77  
76  
75  
74  
73  
72  
71  
-40  
-25  
-10  
5
20  
35  
50  
65  
80  
95  
110  
125  
-40  
-25  
-10  
5
20  
35  
50  
65  
80  
95  
110  
125  
Temperature (℃ )  
Temperature (℃ )  
Figure 11. Center Frequency (fOSC  
)
Figure 12. Maximum Duty Cycle (DCYMAX  
)
vs. Temperature  
vs. Temperature  
© 2008 Fairchild Semiconductor Corporation  
FSEZ2016 • Rev. 1.0.1  
www.fairchildsemi.com  
7
Typical Performance Characteristics (Continued)  
2.2  
2
3
2.8  
2.6  
2.4  
2.2  
2
1.8  
1.6  
1.4  
1.2  
-40  
-25  
-10  
5
20  
35  
50  
65  
80  
95  
110  
125  
-40  
-25  
-10  
5
20  
35  
50  
65  
80  
95  
110  
125  
Temperature (  
)
℃
Temperature (  
℃
)
Figure 13. Green-Mode Entry FB Voltage  
(VFB-N) vs. Temperature  
Figure 14. Green-Mode Ending FB Voltage  
(VFB-G) vs. Temperature  
380  
360  
340  
320  
300  
280  
800  
750  
700  
650  
600  
550  
500  
-40  
-25  
-10  
5
20  
35  
50  
65  
80  
95  
110  
125  
-40  
-25  
-10  
5
20  
35  
50  
65  
80  
95  
110  
125  
Temperature (℃ )  
Temperature (℃ )  
Figure 15. Leading-Edge Blanking Time (tLEB  
)
Figure 16. Drain-Source Breakdown Voltage (BVDSS  
)
vs. Temperature  
vs. Temperature  
© 2008 Fairchild Semiconductor Corporation  
FSEZ2016 • Rev. 1.0.1  
www.fairchildsemi.com  
8
Operation Description  
FSEZ2016 devices integrate functions for low-power  
switch-mode power supplies. The following descriptions  
highlight the key features of the FSEZ2016.  
Oscillator Operation  
The oscillation frequency is fixed at 65KHz.  
Startup Current  
Leading-Edge Blanking (LEB)  
The required startup current is only 8μA. This allows a  
high-resistance, low-wattage startup resistor to supply  
the controller’s startup power. A 1.5MΩ/0.25W startup  
resistor can be used over a wide input range (100V-  
240VAC) with very little power loss.  
Each time the power MOSFET is switched on, a turn-on  
spike occurs at the sense-resistor. To avoid premature  
termination of the switching pulse, a 310ns leading-  
edge blanking time is built in. Conventional RC filtering  
is not necessary. During this blanking period, the  
current-limit comparator is disabled and cannot switch  
off the gate drive.  
Operating Current  
The operating current is normally 3.6mA, which results  
in higher efficiency and reduces the required VDD hold-  
up capacitance. A 10μF/25V VDD hold-up capacitor can  
be used over a wide input range (90V-264VAC) with very  
little power loss.  
Constant Output Power Limit  
When the SENSE voltage across the sense resistor RS  
reaches the threshold voltage, the output GATE drive is  
turned off following a small propagation delay, tPD. This  
propagation delay introduces an additional current  
proportional to tPD•VIN/LP. The propagation delay is  
nearly constant, regardless of the input line voltage VIN.  
Higher input line voltages result in larger additional  
currents. Under high input-line voltages, the output  
power limit is higher than under low input-line voltages.  
Over a wide range of AC input voltages, the variation  
can be significant. To compensate for this, the threshold  
Green-Mode Operation  
The proprietary green-mode function provides off-time  
modulation to linearly decrease the switching frequency  
under light-load and zero-load conditions. The on-time  
is limited to provide better protection against brownouts  
and other abnormal conditions. Power supplies using  
the FSEZ2016 can meet international restrictions  
regarding standby power-consumption.  
voltage is adjusted by adding  
a positive ramp  
(Vlimit_ramp). This ramp signal can vary from 0.74V to  
1.04V and flattens out at 1.04V. A smaller threshold  
voltage forces the output GATE drive to terminate  
earlier, reducing total PWM turn-on time and making the  
output power equal to that of the low line input. This  
proprietary internal compensation feature ensures a  
constant output power limit over a wide range of AC  
input voltages (90V-264VAC).  
Constant Voltage (CV) and Constant  
Current (CC) without Feedback  
The FSEZ2016 can tightly regulate the output voltage  
and provide over-current protection without requiring  
secondary-side feedback signals. For improved CV and  
CC accuracy, the transformer leakage inductance  
should be reduced as much as possible.  
Under Voltage Lockout (UVLO)  
The turn-on/turn-off thresholds are fixed internally at  
17V and 8V. To enable the FSEZ2016 during startup,  
the hold-up capacitor must first be charged to 17V  
through the startup resistor. The hold-up capacitor  
continues to supply VDD before energy can be delivered  
from the auxiliary winding of the main transformer. VDD  
must not drop below 8V during this startup process.  
This UVLO hysteresis window ensures that the hold-up  
capacitor can adequately supply VDD during startup.  
Over-Temperature Protection (OTP)  
The FSEZ2016 has a built-in temperature-sensing  
circuit to shut down PWM output if the junction  
temperature exceeds 140°C. While PWM output is shut  
down, the VDD voltage gradually drops to the UVLO  
voltage. Some of the internal circuits are shut down,  
and VDD gradually starts increasing again. When VDD  
reaches 17V, all the internal circuits, including the  
temperature-sensing circuit, operate normally. If the  
junction temperature is still higher than 140°C, the  
PWM controller shuts down immediately. This situation  
continues until the temperature drops below 110°C. The  
PWM output is then turned back on. The temperature  
hysteresis window for the OTP circuit is 30°C.  
Gate Output  
The BiCMOS output stage is a fast totem-pole gate  
driver. Cross-conduction is avoided to minimize heat  
dissipation, increase efficiency, and enhance reliability.  
The output driver is clamped by an internal 17V Zener  
diode to protect the power MOSFET transistors against  
any harmful over-voltage gate signals.  
VDD Over-Voltage Clamping  
VDD over-voltage clamping is built in to prevent damage  
from over-voltage conditions. When VDD exceeds 22.7V,  
PWM output is shut down. Over-voltage conditions may  
be caused by an open photo-coupler loop or a short  
circuit in the output.  
© 2008 Fairchild Semiconductor Corporation  
FSEZ2016 • Rev. 1.0.1  
www.fairchildsemi.com  
9
Operation Description (Continued)  
Slope Compensation  
Noise Immunity  
The sensed voltage across the current sense resistor is  
used for current mode control and pulse-by-pulse  
current limiting. The built-in slope compensation  
improves power supply stability. Furthermore, it  
prevents sub-harmonic oscillations that normally would  
occur because of peak current mode control. A  
positively sloped, synchronized ramp is activated with  
every switching cycle. The slope of the ramp is:  
Noise from the current sense or the control signal may  
cause significant pulse-width jitter, particularly in  
continuous-conduction mode. Slope compensation  
helps alleviate this problem. Good placement and  
layout practices should be followed. The designer  
should avoid long PCB traces and component leads.  
Compensation and filter components should be located  
near the FSEZ2016. Finally, increasing the power-MOS  
gate resistance is advised.  
0.33 × Duty  
(1)  
Duty(max.)  
© 2008 Fairchild Semiconductor Corporation  
FSEZ2016 • Rev. 1.0.1  
www.fairchildsemi.com  
10  
Applications Information  
Figure 17. Reference Circuit (without Secondary-Side Feedback)  
BOM  
Reference  
Component  
CC 4.7nF/1kV  
Reference  
Component  
C1  
C2  
C3  
C4  
C5  
C6  
C7  
C9  
C10  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
F1  
L2  
R 1Ω/1W  
EC 4.7μF/400V 105°C  
EC 4.7μF/400V 105°C  
EC 10μF/50V 105°C  
CC 1nF/1kV  
Inductor 4.7μH  
L3  
Inductor 470μH  
Inductor 80μH  
R 750kΩ  
L4  
R1  
R2  
R3  
R4  
R5  
R6  
R7  
R8  
R9  
T1  
U1  
EC 560μF/10V  
EC 560μF/10V  
Open  
R 750kΩ  
R 100kΩ  
R 10Ω  
CC 1nF  
R 2.2Ω  
Diode 1N4007  
Diode 1N4007  
Diode 1N4007  
Diode 1N4007  
Diode FR107  
Diode FR102  
Diode SB560  
R 47Ω  
R 270Ω  
R 0Ω  
R 2kΩ  
Transformer EE-16  
IC FSEZ2016  
© 2008 Fairchild Semiconductor Corporation  
FSEZ2016 • Rev. 1.0.1  
www.fairchildsemi.com  
11  
Applications Information (Continued)  
Figure 18. Reference Circuit (with Secondary-Side Feedback)  
BOM  
Reference  
Component  
CC 4.7nF/1kV  
Reference  
Component  
Inductor 470μH  
C1  
C2  
C3  
C4  
C5  
C6  
C7  
C8  
C9  
C10  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
F1  
L3  
EC 4.7μF/400V 105°C  
EC 4.7μF/400V 105°C  
EC 10μF/50V 105°C  
CC 1nF/1kV  
L4  
Inductor 80μH  
R 750kΩ  
R 750kΩ  
R 100kΩ  
R 10Ω  
R1  
R2  
R3  
R4  
R5  
R6  
R7  
R8  
R9  
EC 560μF/10V  
EC 560μF/10V  
CC 2.2nF  
R 2.2Ω  
R 47Ω  
Open  
R 270Ω  
CC 1nF  
R 0Ω  
Diode 1N4007  
Diode 1N4007  
Diode 1N4007  
Diode 1N4007  
Diode FR107  
Diode FR102  
Diode SB560  
R 1Ω/1W  
R 2kΩ  
R10  
R11  
R12  
R13  
T1  
R 560Ω  
R 20kΩ  
R 20kΩ  
R 20kΩ  
Transformer EE-16  
IC FSEZ2016  
IC PC817  
IC TL431  
U1  
U2  
L2  
Inductor 4.7μH  
U3  
© 2008 Fairchild Semiconductor Corporation  
FSEZ2016 • Rev. 1.0.1  
www.fairchildsemi.com  
12  
Physical Dimensions  
10.16  
9.47  
7
5
4
PIN 1  
INDICATOR  
6.47  
6.22  
1
(0.675)  
8.128  
7.620  
2.794  
2.286  
4.318  
3.680  
3.556  
3.048  
0.35  
0.20  
0.508 MIN  
D
3.81  
2.92  
(7.632)  
9.271  
7.870  
1.78  
1.14  
0.508  
0.356  
NOTES:  
THIS PACKAGE CONFORMS TO  
A)  
JEDEC MS-001 VARIATION AA EXCEPT LEAD COUNT.  
B) ALL DIMENSIONS ARE IN MILLIMETERS.  
C) DIMENSIONS ARE EXCLUSIVE OF BURRS,  
MOLD FLASH, AND TIE BAR EXTRUSIONS.  
D) DIMENSION WITH TERMINALS CONSTRAINED  
PERPENDICULAR TO PRINTED CIRCUIT BOARD.  
E) DRAWING FILE NAME: MKT-N07CREV1  
Figure 19. 7-Pin DIP-7 Package  
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner  
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify  
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically  
the warranty therein, which covers Fairchild products.  
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:  
http://www.fairchildsemi.com/packaging/.  
© 2008 Fairchild Semiconductor Corporation  
FSEZ2016 • Rev. 1.0.1  
www.fairchildsemi.com  
13  
© 2008 Fairchild Semiconductor Corporation  
FSEZ2016 • Rev. 1.0.1  
www.fairchildsemi.com  
14  

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