FSL127H [FAIRCHILD]
Green Mode Fairchild Power Switch; 绿色模式飞兆功率开关
| 型号： | FSL127H |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Green Mode Fairchild Power Switch |
| 文件： | 总15页 (文件大小：1544K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
September 2010
FSL127H
Green Mode Fairchild Power Switch (FPS™)
Features
Description
The highly integrated FSL127H consists of a current
mode Pulse Width Modulator (PWM) and an avalanche-
rugged 700V SenseFET. It is specifically designed for
high-performance offline Switch Mode Power Supplies
(SMPS) with minimal external components.
Built-in 5ms Soft-Start Function
Internal Avalanche-Rugged 700V SenseFET
Low Audio Noise
High-Voltage Startup
The integrated PWM controller features include a
proprietary green-mode function that provides off-time
modulation to linearly decrease the switching frequency
at light-load conditions to minimize standby power
consumption. To avoid acoustic noise problems, the
minimum PWM frequency is set above 18KHz. This
green-mode function enables the power supply to meet
international power conservation requirements. With the
internal high-voltage startup circuitry, the power loss
due to bleeding resistors is also eliminated. To further
reduce power consumption, the PWM controller is
manufactured using the BiCMOS process, which allows
an operating current of only 3.5mA.
Fixed PWM Frequency at 100KHz
Linearly Decreasing PWM Frequency to 18KHz
Peak-Current-Mode Control
Cycle-by-Cycle Current Limiting
Leading-Edge Blanking (LEB)
Synchronized Slope Compensation
Internal Open-Loop Protection (OLP)
VDD Under-Voltage Lockout (UVLO)
VDD Over-Voltage Protection (OVP)
Constant Power Limit (Full AC Input Range)
Internal OTP Sensor with Hysteresis
The FSL127H built-in synchronized slope compensation
achieves stable peak-current-mode control. The
proprietary external line compensation ensures
constant output power limit over a wide AC input
voltage range, from 90VAC to 264VAC
.
Applications
The FSL127H provides many protection functions. In
addition to cycle-by-cycle current limiting, the internal
open-loop protection circuit ensures safety when an
open-loop or output short-circuit failure occurs. PWM
output is disabled until VDD drops below the UVLO lower
limit, when the controller starts up again. As long as VDD
exceeds ~28V, the internal OVP circuit is triggered.
General-purpose switch-mode power supplies and
flyback power converters, including:
SMPS for VCR, SVR, STB, DVD & VCD Player,
Printer, Facsimile, & Scanner
Adapter for Camcorder
Compared to a discrete MOSFET and controller or RCC
switching converter solution, the FSL127H reduces total
component count, design size, and weight while
increasing efficiency, productivity, and system reliability.
These devices provide a basic platform well suited for
design of cost-effective flyback converters.
Ordering Information
Operating
Temperature Range
Part Number SenseFET
Package
Packing Method
8-Pin Dual In-Line Package (MDIP),
JEDEC MS-001, .300" Wide
FSL127HNY
2.0A 700V
-40°C to +105°C
Tube
© 2010 Fairchild Semiconductor Corporation
FSL127H • Rev. 1.0.2
www.fairchildsemi.com
Application Diagram
HV
Drain
VIN
FB
VDD
GND
Figure 1. Typical Flyback Application
Output Power Table(1)
230VAC ± 15%(2)
85-265VAC
Open Frame(4)
16W
Product
Adapter(3)
Open Frame(4)
Adapter(3)
FSL127H
14W
20W
11W
Notes:
1. The maximum output power can be limited by junction temperature.
2. 230 VAC or 100/115 VAC with doublers.
3. Typical continuous power in a non-ventilated enclosed adapter with sufficient drain pattern as a heat sink,
at TA=50°C ambient.
4. Maximum practical continuous power in an open-frame design with sufficient drain pattern as a heat sink,
at TA=50°C ambient.
Internal Block Diagram
Figure 2. Internal Block Diagram
© 2010 Fairchild Semiconductor Corporation
FSL127H • Rev. 1.0.2
www.fairchildsemi.com
2
Pin Configuration
F – Fairchild Logo
Z – Plant Code
X – 1-Digit Year Code
Y – 1-Digit Week Code
TT – 2-Digit Die Run Code
T – Package Type (N: DIP)
P – Y: Green Package
M – Manufacture Flow Code
Figure 3. Pin Configuration
Pin Definitions
Pin #
Name Description
1
GND
Ground. SenseFET source terminal on primary side and internal control ground.
Power Supply. The internal protection circuit disables PWM output as long as VDD exceeds the
OVP trigger point.
2
3
4
VDD
Feedback. The signal from the external compensation circuit is fed into this pin. The PWM duty
cycle is determined in response to the signal on this pin and the current-sense signal on the
SENSE pin.
FB
Line-Voltage Detection. The line-voltage detection is used for constant output power limit. It is
suggested to add a low pass filter to filter out line ripple on bulk capacitor.
VIN
HV
5
6
7
8
Startup. For startup, this pin is pulled high to the line input or bulk capacitor via resistors.
Drain SenseFET Drain. High-voltage power SenseFET drain connection.
Drain SenseFET Drain. High-voltage power SenseFET drain connection.
Drain SenseFET Dain. High-voltage power SenseFET drain connection.
© 2010 Fairchild Semiconductor Corporation
FSL127H • Rev. 1.0.2
www.fairchildsemi.com
3
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device
reliability. The absolute maximum ratings are stress ratings only.
Symbol
VDRAIN Drain Pin Voltage(5,6)
Parameter
Min.
Max.
700
8
Unit
V
IDM
EAS
VVDD
VFB
VVIN
VHV
PD
Drain Current Pulsed(7)
A
Single Pulsed Avalanche Energy(8)
140
30
mJ
V
DC Supply Voltage
FB Pin Input Voltage
-0.3
-0.3
7.0
V
VIN Pin Input Voltage
7.0
V
HV Pin Input Voltage
700
1.5
V
Power Dissipation (TA＜50°C)
W
θJA
Junction-to-Air Thermal Resistance
Junction-to-Top Thermal Resistance(9)
Operating Junction Temperature
80
°C/W
°C/W
°C
Ψ JT
TJ
35
+150
+150
+260
-55
TSTG
TL
Storage Temperature Range
°C
Lead Temperature (Wave Soldering or IR, 10 Seconds)
°C
Human Body Model:
JESD22-A114
4.5
1.5
Electrostatic Discharge Capability,
All Pins Except HV Pin(10)
ESD
kV
Charged Device Model:
JESD22-C101
Notes:
5. All voltage values, except differential voltages, are given with respect to the network ground terminal.
6. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
7. Non-repetitive rating: pulse width is limited by maximum junction temperature.
8. L = 51mH, starting TJ = 25°C.
9. Measured on the package top surface.
10. All pins including HV pin: HBM=500V, CDM=1250V.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
Min.
Typ.
Max.
Unit
TA
Operating Ambient Temperature
-40
+105
°C
© 2010 Fairchild Semiconductor Corporation
FSL127H • Rev. 1.0.2
www.fairchildsemi.com
4
Electrical Characteristics
VDD=15V and TA=25°C unless otherwise specified.
Symbol
SenseFET Section(11)
Parameter
Conditions
Min.
Typ.
Max.
Unit
V
BVDSS
Drain- Source Breakdown Voltage
Zero-Gate-Voltage Drain Current
VGS = 0V
700
VDS = 700V, VGS = 0V
0.5
50.0
IDSS
μA
VDS = 560V, VGS = 0V,
TA = 125°C
1
200
7.2
RDS(ON)
CISS
COSS
CRSS
Drain-Source On-State Resistance(12) VGS = 10V, ID = 0.5A
6.0
550
Ω
VGS = 0V, VDS = 25V,
Input Capacitance
f = 1MHz
715
pF
VGS = 0V, VDS = 25V,
Output Capacitance
f = 1MHz
38
17
50
26
pF
pF
V
GS = 0V, VDS = 25V,
f = 1MHz
Reverse Transfer Capacitance
td(on)
tr
Turn-On Delay Time
Rise Time
VDS = 350V, ID = 1.0A
VDS = 350V, ID = 1.0A
VDS = 350V, ID = 1.0A
VDS = 350V, ID = 1.0A
20
15
55
25
50
40
ns
ns
ns
ns
td(off)
Turn-Off Delay Time
Fall Time
120
60
tf
VDD Section
VOP
Continuously Operating Voltage
Start Threshold Voltage
Minimum Operating Voltage
Startup Current
22
13
9
V
V
VDD-ON
VDD-OFF
IDD-ST
IDD-OP
11
7
12
8
V
VDD-ON – 0.16V
30
4.0
µA
mA
Operating Supply Current
VDD = 15V, VFB = 3V
3.0
3.5
2
Green-Mode Operating Supply
Current
IDD-BM
VFB = VZDC
mA
IDD-OLP
VTH-OLP
VDD-OVP
Internal Sink Current
IDD-OLP Off Voltage
30
5
60
6
90
7
µA
V
VTH-OLP+0.1V
VDD Over-Voltage Protection
27
28
29
V
VDD Over-Voltage Protection
Debounce Time
tD-VDDOVP
HV Section
IHV
75
130
200
µs
HV 120VDC
,
Maximum Current Drawn from HV Pin
Leakage Current After Startup
1.5
3.5
1
5.0
20
mA
µA
VDD = 0V with 10µF
HV = 700V,
DD = VDD-OFF+1V
IHV-LC
V
Oscillator Section
fOSC
fOSC-G
DMAX
fDV
Frequency in Nominal Mode
94
14
100
18
106
22
kHz
kHz
%
Center Frequency
Green-Mode Frequency
Maximum Duty Cycle
85
Frequency Variation vs. VDD Deviation VDD = 9V to 22V
5
5
%
Frequency Variation vs. Temperature
TA = -40 to +105°C
fDT
%
Deviation(11)
Continued on the following page…
© 2010 Fairchild Semiconductor Corporation
FSL127H • Rev. 1.0.2
www.fairchildsemi.com
5
Electrical Characteristics (Continued)
VDD=15V and TA=25°C unless otherwise specified.
Symbol
VIN Section
VIN-ON
Parameter
Conditions
Min.
Typ.
Max.
Unit
0.98
0.60
4.4
1.03
0.70
4.7
1.08
0.80
5.0
PWM Turn-on Threshold Voltage
Release Latch Voltage
V
V
VIN-RL
VIN-H
Pull HIGH Latch Trigger Level
Pull HIGH Latch Debounce Time
Pull LOW Auto Recovery Trigger Level
V
tIN-H
µs
V
120
0.3
VIN-L
0.2
0.4
Feedback Input Section
AV
FB Voltage to Current-Sense Attenuation
1/4.0
9.5
V/V
kΩ
V
ZFB
Input Impedance
VFB-OPEN
VFB-OLP
Output High Voltage
FB Open-Loop Trigger Level
5
4.4
4.6
56
4.8
59
V
Delay Time of FB Pin Open-loop
Protection
tD-OLP
VFB-N
50
ms
V
Green-Mode Entry FB Voltage
Green-Mode Ending FB Voltage
Zero Duty Cycle FB Voltage
2.3
2.5
2.7
VFB-N
0.1
-
VFB-G
V
VFB-ZDC
1.9
2.1
2.3
V
PWM Frequency
fOSC
fOSC-G
V
FB-ZDC VFB-G
VFB-N
VFB
Figure 4. VFB vs. PWM Frequency
Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
Current-Sense Section
ILIM at VIN = 1.2V Peak Current Limit
ILIM at VIN = 3.6V Peak Current Limit
VIN = 1.2V
VIN = 3.6V
0.51
0.44
4.5
0.61
0.54
5.0
0.71
0.64
5.5
A
A
tSS
Over-Temperature Protection Section (OTP)
TOTP
Protection Junction Temperature(11,13)
Notes:
Period During Soft-Start Time(11)
ms
142
°C
11. These parameters, although guaranteed, are not 100% tested in production.
12. Pulse test: pulse width ≤ 300μs, duty ≤ 2%.
13. When activated, the output is disabled and the latch is turned off.
© 2010 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSL127H • Rev. 1.0.2
6
Typical Characteristics
Figure 5. IDD-ST vs. Temperature
Figure 6. IDD-OP vs. Temperature
Figure 8. VDD-OFF vs. Temperature
Figure 10. VDD-OVP vs. Temperature
Figure 7. VDD-ON vs. Temperature
Figure 9. VTH-OLP vs. Temperature
© 2010 Fairchild Semiconductor Corporation
FSL127H • Rev. 1.0.2
www.fairchildsemi.com
7
Typical Characteristics
Figure 11. IHV vs. Temperature
Figure 12. fOSC vs. Temperature
Figure 14. VIN-ON vs. Temperature
Figure 16. VIN-H vs. Temperature
Figure 13. fOSC-G vs. Temperature
Figure 15. VIN-RL vs. Temperature
© 2010 Fairchild Semiconductor Corporation
FSL127H • Rev. 1.0.2
www.fairchildsemi.com
8
Typical Characteristics
Figure 17. VIN-L vs. Temperature
Figure 18. VFB-N vs. Temperature
Figure 20. tD-OLP vs. Temperature
Figure 22. IDD-BM vs. Temperature
Figure 19. VFB-OLP vs. Temperature
Figure 21. VFB-ZDC vs. Temperature
© 2010 Fairchild Semiconductor Corporation
FSL127H • Rev. 1.0.2
www.fairchildsemi.com
9
Functional Description
Startup Operation
Green-Mode Operation
For startup, the HV pin is connected to the line input or
bulk capacitor through the external resistor RHV, as
shown in Figure 23. Typical startup current drawn from
the HV pin is 3.5mA and it charges the VDD capacitor
through the resistor RHV. The startup current turns off
when the VDD capacitor voltage reaches VDD-ON. The
VDD capacitor maintains VDD until the auxiliary winding
of the transformer provides the operating current.
The FSL127H uses feedback voltage (VFB) as an
indicator of the output load and modulates the PWM
frequency, as shown in Figure 25, such that the
switching frequency decreases as load decreases. In
heavy load conditions, the switching frequency is
100kHz. Once VFB decreases below VFB-N (2.5V), the
PWM frequency starts to linearly decrease from 100kHz
to 18kHz to reduce the switching losses. As VFB
decreases below VFB-G (2.4V), the switching frequency
is fixed at 18kHz and FSL127H enters “deep” green
mode to reduce the standby power consumption. As
VFB decreases below VFB-ZDC (2.1V), FSL127H enters
RHV
CDC
burst-mode operation. When VFB drops below VFB-ZDC
,
FSL127H stops switching and the output voltage starts
to drop, which causes the feedback voltage to rise.
Once VFB rises above VFB-ZDC, switching resumes. Burst
mode alternately enables and disables switching,
thereby reducing switching loss to improve power
saving, as shown in Figure 26.
DDD
HV
VDD
NA
CDD
FSL127H
AC line
Figure 23. Startup Circuit
Slope Compensation
FSL127H is designed for flyback power converter. The
peak-current-mode control is used to optimize system
performance. Slope compensation is added to stabilize
the current loop. The FSL127H inserts a synchronized,
positively sloped ramp at each switching cycle.
Soft Start
Figure 25. PWM Frequency
The FSL127H has internal soft-start circuit that slowly
increases the SenseFET current after startup. The
typical soft-start time is 5ms, during which the VLimit
level is increased in six steps to smoothly establish the
required output voltage, as shown in Figure 24. It also
helps prevent transformer saturation and reduces stress
on the secondary diode during startup.
Figure 24. Soft-Start Function
Figure 26. Burst Mode Operation
© 2010 Fairchild Semiconductor Corporation
FSL127H • Rev. 1.0.2
www.fairchildsemi.com
10
Constant Power Control
To limit the output power of the converter constantly,
high/low line compensation is included. Sensing the
converter input voltage through the VIN pin, the
high/low line compensation function generates
a
relative peak-current-limit threshold voltage for constant
power control, as shown in Figure 27.
Figure 27. Constant Power Control
Protections
The FSL127H provides protection functions to prevent
the power supply and the load from being damaged.
The protection features include:
Figure 29. OLP Operation
VDD Over-Voltage Protection (OVP)
Latch / Auto Recovery Function
VDD over-voltage protection prevents IC damage caused
by over voltage on the VDD pin. The OVP is triggered
when VDD reaches 28V. It has a debounce time (typically
130µs) to prevent false trigger by switching noise.
The FSL127H provides additional protections by the
VIN pin, such as pull-HIGH latch and pull-LOW auto
recovery that depend on the application. As shown in
Figure 28, when VIN level is higher than 4.7V, FSL127H
is latched until the VDD is discharged. FSL127H is in
auto recovery when the VIN level is lower than 0.3V.
Over-Temperature Protection (OTP)
The SenseFET and the control IC are integrated,
making it easier to detect the temperature of the
SenseFET.
When
the
temperature
exceeds
approximately 142°C, thermal shutdown is activated.
Figure 28. VIN Pin Function
Open-Loop / Overload Protection (OLP)
When the upper branch of the voltage divider for the
shunt regulator (KA431 shown) is broken, as shown in
Figure 29, or over-current or output short occurs; there
is no current flowing through the opto-coupler transistor,
which pulls up the feedback voltage to 6V. When the
feedback voltage is above 4.6V for longer than 56ms,
OLP is triggered. This protection is also triggered when
the SMPS output drops below the nominal value longer
than 56ms due to the overload condition.
© 2010 Fairchild Semiconductor Corporation
FSL127H • Rev. 1.0.2
www.fairchildsemi.com
11
Typical Application Circuit
Application
Fairchild Devices
FSL127H
Input Voltage Range
Output
Adapter
90~264VAC
12V/0.85A (10.2W)
Features
High efficiency (>76.74% at full load) meeting Energy Star V2.0 regulation with enough margin
Standby power <100mW at no-load condition
Provides full protection functions, including:
OVP
OTP
OLP
VIN-H
VIN-L
Latch
Latch
Auto Restart
Latch
Auto Restart
Figure 30. Measured Standby Power
Figure 31. Over-Current Protection
Figure 32. Schematic of Typical Application Circuit
© 2010 Fairchild Semiconductor Corporation
FSL127H • Rev. 1.0.2
www.fairchildsemi.com
12
Typical Application Circuit (Continued)
Transformer Specification
Core: EE16
Bobbin: EE16
Figure 33. Transformer Diagram
TERMINAL
NO.
WIRE
Ts
S
5
2
4
8
F
4
1
W1
W2
W3
W4
2UEW 0.3*1
2UEW 0.26*1
13
75
1.2
13
3
COPPER SHIELD
TEX-E 0.35*1
10
CORE ROUNDING TAPE
Primary-Side Inductance=880μH ±5%
Primary-Side Effective Leakage<20μH ±5%
© 2010 Fairchild Semiconductor Corporation
FSL127H • Rev. 1.0.2
www.fairchildsemi.com
13
Physical Dimensions
9.83
9.00
6.67
6.096
8.255
7.61
3.683
3.20
7.62
5.08 MAX
0.33 MIN
3.60
3.00
(0.56)
2.54
0.356
0.20
0.56
0.355
9.957
7.87
1.65
1.27
7.62
NOTES: UNLESS OTHERWISE SPECIFIED
A) THIS PACKAGE CONFORMS TO
JEDEC MS-001 VARIATION BA
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS ARE EXCLUSIVE OF BURRS,
MOLD FLASH, AND TIE BAR EXTRUSIONS.
D) DIMENSIONS AND TOLERANC
ASME Y14.5M-1994
ES PER
E) DRAWING FILENAME AND REVSION: MKT-N08FREV2.
Figure 34. 8-pin Dual In-Line Package (DIP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically
the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2010 Fairchild Semiconductor Corporation
FSL127H • Rev. 1.0.2
www.fairchildsemi.com
14
© 2010 Fairchild Semiconductor Corporation
FSL127H • Rev. 1.0.2
www.fairchildsemi.com
15
相关型号：
©2020 ICPDF网 联系我们和版权申明