FST16211 [FAIRCHILD]
24-Bit Bus Switch; 24位总线开关
| 型号： | FST16211 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | 24-Bit Bus Switch |
| 文件： | 总8页 (文件大小：290K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
July 1997
Revised August 2000
FST16211
24-Bit Bus Switch
General Description
Features
■ 4Ω switch connection between two ports
■ Minimal propagation delay through the switch
■ Low lCC
The Fairchild Switch FST16211 provides 24-bits of high-
speed CMOS TTL-compatible bus switching. The low on
resistance of the switch allows inputs to be connected to
outputs without adding propagation delay or generating
additional ground bounce noise.
■ Zero bounce in flow-through mode
■ Control inputs compatible with TTL level
The device is organized as a 12-bit or 24-bit bus switch.
When OE1 is LOW, the switch is ON and Port 1A is con-
■ Also packaged in plastic Fine Pitch Ball Grid Array
(FBGA)
nected to Port 1B. When OE2 is LOW, Port 2A is connected
to Port 2B. When OE1/2 is HIGH, a high impedance state
exists between the A and B Ports.
Ordering Code:
Order Number
Package Number
Package Description
FST16211GX
(Note 1)
BGA54A
Preliminary
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-195, 5.5mm Wide
[TAPE and REEL]
FST16211MEA
FST16211MTD
MS56A
MTD56
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Note 1: BGA package available in Tape and Reel only.
Logic Diagram
© 2000 Fairchild Semiconductor Corporation
DS500037
www.fairchildsemi.com
Connection Diagrams
Pin Descriptions
Pin Name
Description
Pin Assignment for SSOP and TSSOP
OE1, OE2
1A, 2A
Bus Switch Enables
Bus A
1B, 2B
Bus B
FBGA Pin Assignments
1
2
3
4
5
6
A
B
C
D
E
F
1A2
1A4
1A6
1A10
1A12
2A4
2A6
2A8
2A10
1A1
1A3
1A5
1A9
1A11
2A3
2A5
2A7
2A9
NC
OE2
OE1
1B7
1B8
2B1
2B2
GND
2B11
1B1
1B3
1B5
1B9
1B11
2B3
2B5
2B7
2B9
1B2
1B4
1B6
1B10
1B12
2B4
2B6
2B8
2B10
1A7
GND
1A8
2A1
2A2
VCC
2A11
G
H
J
2A12 2B12
Truth Table
Inputs
OE1
Inputs/Outputs
OE2
1A, 1B
2A, 2B
2A = 2B
Z
L
L
L
H
L
1A = 1B
1A = 1B
H
H
Z
Z
2A = 2B
Z
Pin Assignment for FBGA
H
TOP VIEW
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2
Absolute Maximum Ratings(Note 2)
Recommended Operating
Conditions (Note 5)
Supply Voltage (VCC
)
−0.5V to +7.0V
−0.5V to +7.0V
−0.5V to +7.0V
−50mA
DC Switch Voltage (VS) (Note 3)
DC Input Voltage (VIN) (Note 4)
DC Input Diode Current (lIK) VIN<0V
DC Output (IOUT) Sink Current
Power Supply Operating (VCC)
4.0V to 5.5V
0V to 5.5V
0V to 5.5V
Input Voltage (VIN
)
Output Voltage (VOUT
)
128mA
Input Rise and Fall Time (tr, tf)
Switch Control Input
DC VCC/GND Current (ICC/IGND
)
+/− 100mA
0nS/V to 5nS/V
0nS/V to DC
Storage Temperature Range (TSTG
)
−65°C to +150 °C
Switch I/O
Free Air Operating Temperature (TA)
-40 °C to +85 °C
Note 2: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum rating.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Note 3: VS is the voltage observed/applied at either A or B Ports across the
switch.
Note 4: The input and output negative voltage ratings may be exceeded if
the input and output diode current ratings are observed.
Note 5: Unused control inputs must be held HIGH or LOW. They may not
float.
DC Electrical Characteristics
T
A = −40 °C to +85 °C
VCC
(V)
Symbol
Parameter
Units
Conditions
Min
Typ
Max
(Note 6)
VIK
Clamp Diode Voltage
4.5
4.0–5.5
4.0–5.5
5.5
−1.2
V
V
IIN = −18mA
VIH
VIL
II
HIGH Level Input Voltage
LOW Level Input Voltage
Input Leakage Current
2.0
0.8
±1.0
10
±1.0
7
V
µA
µA
µA
Ω
0 ≤ VIN ≤ 5.5V
IN = 5.5V
0 ≤ A, B ≤ VCC
0
V
IOZ
OFF-STATE Leakage Current
Switch On Resistance
(Note 7)
5.5
RON
4.5
4
4
V
V
V
V
V
IN = 0V, IIN = 64mA
4.5
7
Ω
IN = 0V, IIN = 30mA
4.5
8
12
20
3
Ω
IN = 2.4V, IIN = 15mA
IN = 2.4V, IIN = 15mA
IN = VCC or GND, IOUT = 0
4.0
11
Ω
ICC
Quiescent Supply Current
Increase in ICC per Input
5.5
µA
mA
∆ ICC
5.5
2.5
One input at 3.4V
Other inputs at VCC or GND
Note 6: Typical values are at VCC = 5.0V and TA = +25°C
Note 7: Measured by the voltage drop between A and B pins at the indicated current through the switch. On resistance is determined by the lower of the
voltages on the two (A or B) pins.
3
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AC Electrical Characteristics
T
A = −40 °C to +85 °C,
L = 50pF, RU = RD = 500Ω
CC = 4.5 – 5.5V CC = 4.0V
C
Figure
No.
Symbol
Parameter
Units
Conditions
V
V
Min
Max
Min
Max
t
PHL,tPLH
Prop Delay Bus to Bus (Note 8)
Output Enable Time
0.25
0.25
ns
ns
VI = OPEN
Figures
1, 2
tPZH, tPZL
1.5
1.5
6.0
7.0
6.5
7.2
VI = 7V for tPZL
Figures
1, 2
VI = OPEN for tPZH
VI = 7V for tPLZ
tPHZ, tPLZ
Output Disable Time
ns
Figures
1, 2
VI = OPEN for tPHZ
Note 8: This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the typical On
resistance of the switch and the 50pF load capacitance, when driven by an ideal voltage source (zero output impedance).
Capacitance (Note 9)
Symbol
Parameter
Typ
Max
Units
Conditions
CC = 5.0V
VCC, OE = 5.0V
CIN
Control Pin Input Capacitance
3
pF
V
CI/O
Input/Output Capacitance
6
pF
Note 9: TA = +25°C, f = 1 MHz, Capacitance is characterized but not tested.
AC Loading and Waveforms
Note: Input driven by 50 Ω source terminated in 50 Ω
Note: CL includes load and stray capacitance
Note: Input PRR = 1.0 MHz, tW = 500 ns
FIGURE 1. AC Test Circuit
FIGURE 2. AC Waveforms
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4
Physical Dimensions inches (millimeters) unless otherwise noted
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-195, 5.5mm Wide
Package Number BGA54A
Preliminary
5
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
Package Number MS56A
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6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD56
Technology Description
The Fairchild Switch family derives from and embodies Fairchild’s proven switch technology used for several years in its
74LVX3L384 (FST3384) bus switch product.
7
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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8
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