FST3125QSCX [FAIRCHILD]
4-Bit Bus Switch; 4位总线开关
| 型号： | FST3125QSCX |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | 4-Bit Bus Switch |
| 文件： | 总9页 (文件大小：440K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
March 2008
FST3125 — 4-Bit Bus Switch
Features
Description
Fairchild switch FST3125 provides four high-speed
CMOS TTL-compatible bus switches. The low on
resistance of the switch allows inputs to be connected
to outputs without adding propagation delay or
generating additional ground bounce noise.
4Ω Switch Connection between Two Ports
Minimal Propagation Delay through the Switch
Low ICC
Zero Bounce in Flow-through Mode
Control Inputs Compatible with TTL Level
The device is organized as four one1-bit switches with
separate /OE inputs. When /OE is LOW, the switch is
ON and port A is connected to port B. When /OE is
HIGH, the switch is OPEN and a high-impedance state
exists between the two ports.
Ordering Information
Operating
Part Number Temperature
Range
Packing
Package
Method
14-Lead, Small Outline Integrated Circuit (SOIC) 0.150 inch
Narrow
FST3125M
-40 to 85°C
-40 to 85°C
-40 to 85°C
-40 to 85°C
-40 to 85°C
-40 to 85°C
Tube
Tape and Reel
Tube
14-Lead, Small Outline Integrated Circuit (SOIC) 0.150 inch
Narrow
FST3125MX
FST3125QSC
FST3125QSCX
FST3125MTC
FST3125MTCX
16-Lead, Quarter Size Outline Package (QSOP) MO-137
0.150 inch Wide
16-Lead, Quarter Size Outline Package (QSOP) MO-137
0.150 inch Wide
Tape and Reel
Tube
14-Lead, Thin Shrink Small Outline Package (TSSOP)
MO-153, 4mm Wide
14-Lead, Thin Shrink Small Outline Package (TSSOP)
MO-153, 4mm Wide
Tape and Reel
All packages are lead free per JEDEC: J-STD-020B standard.
The Fairchild switch family derives from and embodies Fairchild’s proven switch technology used for several years in its
74LVX3L384 (FST3384) bus switch product.
Figure 1. Logic Diagram
© 2005 Fairchild Semiconductor Corporation
FST3125 • Rev. 1.0.3
www.fairchildsemi.com
Pin Configurations
1
2
3
4
5
6
7
8
NC
/OE1
1A
VCC
/OE4
4A
16
15
14
13
12
11
10
9
/OE1
1A
1
2
3
4
5
6
7
VCC
/OE4
4A
14
13
12
11
10
9
1B
1B
4B
/OE2
2A
4B
/OE2
2A
/OE3
3A
/OE3
3A
2B
2B
3B
GND
3B
8
GND
NC
Figure 2. SOIC and TSSOP Pin Assignments
Figure 3. QSOP Pin Assignments
Pin Descriptions
Pin Names
/OE1, /OE2, /OE3, /OE4
1A, 2A, 3A, 4A
1B, 2B, 3B, 4B
NC
Description
Bus Switch Enables
Bus A
Bus B
Not Connected
Supply Voltage
Ground
VCC
GND
Truth Table
Inputs
/OE
Inputs/Outputs
A, B
LOW
HIGH
A = B
High Impedance
© 2005 Fairchild Semiconductor Corporation
FST3125 • Rev. 1.0.3
www.fairchildsemi.com
2
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device
reliability. The absolute maximum ratings are stress ratings only.
Symbol
VCC
Parameter
Min.
-0.5
-0.5
-0.5
Max.
7.0
Unit
V
Supply Voltage
VS
DC Switch Voltage
DC Input Voltage(1)
DC Input Current
7.0
V
VIN
7.0
V
IIK
-50
mA
mA
mA
°C
IOUT
DC Output Sink Current
DC VCC / GND Current
128
±100
+150
ICC / IGND
TSTG
Note:
Storage Temperature Range
-65
1. The input and output negative voltage ratings may be exceeded if the input and output diode current ratings are
observed.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
VCC
Parameter
Power Supply Operating
Min.
4.0
0
Max.
5.5
5.5
5.5
5
Unit
V
VIN
Input Voltage
V
VOUT
Output Voltage
0
V
Switch Control Input(2)
Switch I/O
0
tr, tf
Input Rise and Fall Time
ns/V
°C
0
DC
+85
TA
Operating Temperature, Free Air
-40
Note:
2. Unused control inputs must be held HIGH or LOW. They may not float.
© 2005 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FST3125 • Rev. 1.0.3
3
DC Electrical Characteristics
Typical values are at VCC = 5.0V and TA = 25°C.
TA=-40 to +85°C
Symbol
Parameter
Conditions
IIN = -18mA
VCC (V)
Units
Min.
Typ.
Max.
VIK
VIH
VIL
IIN
Clamp Diode Voltage
High-Level Input Voltage
Low-Level Input Voltage
Input Leakage Current
4.5
-1.2
V
V
4.0 to 5.5
4.0 to 5.5
5.5
2.0
0.8
V
±1.0
µA
0 ≤ VIN ≤ 5.5
Off-state Leakage
Current
IOZ
RON
ICC
5.5
±1.0
µA
0 ≤ A, B ≤ VCC
VIN = 0V, IIN = 64mA
VIN = 0V, IIN = 30mA
VIN = 2.4V, IIN = 15mA
VIN = 2.4V, IIN = 15mA
VIN = VCC or GND,
4.5
4.5
4.5
4.0
4
4
7
7
Switch On Resistance(3)
Ω
8
15
20
11
Quiescent Supply Current
Increase in ICC per Input
5.5
5.5
3
µA
I
OUT = 0
One Input at 3.4V, Other
Inputs at VCC or GND
2.5
mA
ΔICC
Note:
3. Measured by the voltage drop between A and B pins at the indicated current through the switch. On resistance
is determined by the lower of the voltages on the A or B pins.
AC Electrical Characteristics
TA = -40 to +85°C, CL = 50pF, and RU = RD = 500Ω.
VCC = 4.5 – 5.5V
VCC = 4.0V
Symbol
Parameter
Conditions
Units
Figure
Min.
Max.
Min.
Max.
Propagation Delay
Bus-to-Bus(4)
Figure 4
Figure 5
tPHL, tPLH
VIN = Open
0.25
0.25
ns
VIN = 7V for tPZL
Figure 4
Figure 5
tPZH ,tPZL
Output Enable Time
Output Disable Time
VIN = Open for
1.0
1.5
5.0
5.3
5.5
5.6
ns
ns
tPZH
VIN = 7V for tPLZ
Figure 4
Figure 5
tPHZ, tPLZ
VIN = Open for
tPHZ
Note:
4. This parameter is guaranteed by design, but is not tested. The bus switch contributes no propagation delay
other than the RC delay of the typical on resistance of the switch and the 50pF load capacitance when driven by
an ideal voltage source (zero output impedance).
Capacitance
TA = +25°C, f = 1MHz. Capacitance is characterized, but not tested.
Symbol
CIN
Parameter
Conditions
VCC = 5.0V
Typ.
Units
pF
Control Pin Input Capacitance
Input/Output Capacitance
3
2
CI/O
VCC, /OE = 5.0V
pF
© 2005 Fairchild Semiconductor Corporation
FST3125 • Rev. 1.0.3
www.fairchildsemi.com
4
AC Loadings and Waveforms
Notes: Input driven by 50Ω source terminated in 50Ω.
CL includes load and stray capacitance.
Input PRR = 1.0MHz, tw = 500ns.
Figure 4. AC Test Circuit
Figure 5. AC Waveforms
© 2005 Fairchild Semiconductor Corporation
FST3125 • Rev. 1.0.3
www.fairchildsemi.com
5
Physical Dimensions
8.75
8.50
0.65
A
7.62
14
8
B
5.60
4.00
3.80
6.00
1.70
1.27
1
7
PIN ONE
INDICATOR
0.51
0.35
1.27
(0.33)
LAND PATTERN RECOMMENDATION
M
0.25
C B A
1.75 MAX
1.50
SEE DETAIL A
1.25
0.25
0.19
0.25
0.10
C
0.10
C
NOTES: UNLESS OTHERWISE SPECIFIED
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AB, ISSUE C,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
0.50
0.25
X 45°
R0.10
R0.10
8°
0°
GAGE PLANE
FLASH OR BURRS.
D) LANDPATTERN STANDARD:
SOIC127P600X145-14M
E) DRAWING CONFORMS TO ASME Y14.5M-1994
F) DRAWING FILE NAME: M14AREV13
0.36
0.90
0.50
SEATING PLANE
(1.04)
DETAIL A
SCALE: 20:1
Figure 6. 14-Lead, Small-Outline Integrated Circuit (SOIC) 0.150-inch Narrow
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically
the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
© 2005 Fairchild Semiconductor Corporation
FST3125 • Rev. 1.0.3
www.fairchildsemi.com
6
Physical Dimensions
LAND PATTERN
TOP VIEW
RECOMMENDATION
END VIEW
SIDE VIEW
DETAIL A
Figure 7. 16-Lead, Quarter-Size Outline Package (QSOP), MO-1370.150-inch Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically
the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
© 2005 Fairchild Semiconductor Corporation
FST3125 • Rev. 1.0.3
www.fairchildsemi.com
7
Physical Dimensions
0.43 TYP
0.65
1.65
6.10
0.45
12.00°TOP & BOTTOM
R0.09 min
A. CONFORMS TO JEDEC REGISTRATION MO-153,
VARIATION AB, REF NOTE 6
B. DIMENSIONS ARE IN MILLIMETERS
R0.09min
1.00
C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH,
AND TIE BAR EXTRUSIONS
D. DIMENSIONING AND TOLERANCES PER ANSI
Y14.5M, 1982
E. LANDPATTERN STANDARD: SOP65P640X110-14M
F. DRAWING FILE NAME: MTC14REV6
Figure 8. 14-Lead, Thin Shrink Small Outline Package (TSSOP) MO-153, 4mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically
the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
© 2005 Fairchild Semiconductor Corporation
FST3125 • Rev. 1.0.3
www.fairchildsemi.com
8
© 2005 Fairchild Semiconductor Corporation
FST3125 • Rev. 1.0.3
www.fairchildsemi.com
9
相关型号：
FST3126M
CBT/FST/QS/5C/B SERIES, QUAD 1-BIT DRIVER, TRUE OUTPUT, PDSO14, 0.150 INCH, MS-012, SOIC-14
ROCHESTER
FST3126MTCX
CBT/FST/QS/5C/B SERIES, QUAD 1-BIT DRIVER, TRUE OUTPUT, PDSO14, 4.40 MM, MO-153AB, TSSOP-14
ROCHESTER
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