FST3345 [FAIRCHILD]
8-Bit Bus Switch; 8位总线开关
| 型号： | FST3345 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | 8-Bit Bus Switch |
| 文件： | 总6页 (文件大小：122K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
June 1997
Revised December 1999
FST3345
8-Bit Bus Switch
General Description
Features
The Fairchild Switch FST3345 provides 8-bits of high-
speed CMOS TTL-compatible bus switching. The low on
resistance of the switch allows inputs to be connected to
outputs without adding propagation delay or generating
additional ground bounce noise.
■ 4Ω switch connection between two ports.
■ Minimal propagation delay through the switch.
■ Low lCC
.
■ Zero bounce in flow-through mode.
■ Control inputs compatible with TTL level.
The device is organized as an 8-bit switch bank with dual
output enable inputs (OE and OE). When OE is LOW or
OE is HIGH, the switch is ON and Port A is connected to
Port B. When OE is HIGH and OE is LOW, the switch is
OPEN and a high-impedance state exists between the two
ports.
Ordering Code:
Order Number
FST3345WM
FST3345QSC
FST3345MTC
Package Number
M20B
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150 Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MQA20
MTC20
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Diagram
Connection Diagram
Pin Descriptions
Truth Table
Pin Name
Description
Inputs
Function
OE, OE
Bus Switch Enables
Bus A
OE
X
OE
L
A
B
Connect
Connect
Bus B
H
X
L
H
Disconnect
© 1999 Fairchild Semiconductor Corporation
DS500019
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Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions (Note 3)
Supply Voltage (VCC
)
−0.5V to +7.0V
−0.5V to +7.0V
−0.5V to +7.0V
−50mA
DC Switch Voltage (VS)
Power Supply Operating (VCC
Input Voltage (VIN
Output Voltage (VOUT
)
4.0V to 5.5V
0V to 5.5V
0V to 5.5V
DC Input Voltage (VIN) (Note 2)
DC Input Diode Current (lIK) VIN<0V
DC Output (IOUT) Sink Current
)
)
128mA
Input Rise and Fall Time (tr, tf)
Switch Control Input
DC VCC/GND Current (ICC/IGND
)
+/− 100mA
0nS/V to 5nS/V
0nS/V to DC
Storage Temperature Range (TSTG
)
−65°C to +150 °C
Switch I/O
Free Air Operating Temperature (TA)
−40 °C to +85 °C
Note 1: The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum rating.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Note 2: The input and output negative voltage ratings may be exceeded if
the input and output diode current ratings are observed.
Note 3: Unused control inputs must be held HIGH or LOW. They may not
float.
DC Electrical Characteristics
T
A = −40 °C to +85 °C
VCC
(V)
Symbol
Parameter
Units
Conditions
Typ
Min
Max
(Note 4)
VIK
Clamp Diode Voltage
HIGH Level Input Voltage
LOW Level Input Voltage
Input Leakage Current
OFF-STATE Leakage Current
Switch On Resistance
(Note 5)
4.5
4.0–5.5
4.0–5.5
5.5
−1.2
V
V
IIN = -18mA
VIH
VIL
II
2.0
0.8
±1.0
±1.0
7
V
µA
µA
Ω
0≤ VIN ≤5.5V
0 ≤A, B ≤VCC
IOZ
RON
5.5
4.5
4
4
V
V
V
V
V
IN = 0V, IIN = 64mA
4.5
7
Ω
IN = 0V, IIN = 30mA
4.5
8
15
20
3
Ω
IN = 2.4V, IIN = 15mA
IN = 2.4V, IIN = 15mA
IN = VCC or GND, IOUT = 0
4.0
11
Ω
ICC
Quiescent Supply Current
Increase in ICC per Input
5.5
µA
mA
∆ ICC
5.5
2.5
One input at 3.4V
Other inputs at VCC or GND
Note 4: Typical values are at VCC = 5.0V and TA = +25°C
Note 5: Measured by the voltage drop between A and B pins at the indicated current through the switch. On resistance is determined by the lower of the
voltages on the two (A or B) pins.
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2
AC Electrical Characteristics
T
A = −40 °C to +85 °C,
CL = 50 pF, RU = RD = 500Ω
Symbol
Parameter
Units
Conditions
Figure No.
V
CC = 4.5 − 5.5V CC = 4.0V
V
Min
Max
Min
Max
t
PHL,tPLH
Prop Delay Bus to Bus (Note 6)
Output Enable Time
0.25
0.25
ns
ns
VI = OPEN
Figure 1
Figure 2
tPZH, tPZL
1.5
1.0
6.5
8.0
7.0
8.2
VI = 7V for tPZL
Figure 1
Figure 2
VI = OPEN for tPZH
VI = 7V for tPLZ
tPHZ, tPLZ
Output Disable Time
ns
Figure 1
Figure 2
VI = OPEN for tPHZ
Note 6: This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the typical On
resistance of the switch and the 50pF load capacitance, when driven by an ideal voltage the source (zero output impedance).
Capacitance (Note 7)
Symbol
CIN
CI/O
Parameter
Control Pin Input Capacitance
Input/Output Capacitance
Typ
4
Max
Units
pF
Conditions
CC = 5.0V
VCC, OE = 5.0V, OE = 0V
V
5
pF
Note 7: TA = +25°C, f = 1 MHz, Capacitance is characterized but not tested.
AC Loading and Waveforms
Note: Input driven by 50 Ω source terminated in 50 Ω
Note: CL includes load and stray capacitance
Note: Input PRR = 1.0 MHz tW = 500 nS
FIGURE 1. AC Test Circuit
FIGURE 2. AC Waveforms
3
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Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M20B
20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150 Wide
Package Number MQA20
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4
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
Technology Description
The Fairchild Switch family derives from and embodies Fairchild’s proven switch technology used for several years in its
74LVX3L384 (FST3384) bus switch product.
5
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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6
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