GTLP6C816AMTC [FAIRCHILD]
LVTTL-to-GTLP Clock Driver; LVTTL至GTLP时钟驱动器
| 型号： | GTLP6C816AMTC |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | LVTTL-to-GTLP Clock Driver |
| 文件： | 总7页 (文件大小：55K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
August 1998
Revised August 1999
GTLP6C816A
LVTTL-to-GTLP Clock Driver
General Description
Features
The GTLP6C816A is a clock driver that provides LVTTL to
GTLP signal level translation (and vice versa). The device
provides a high speed interface between cards operating at
LVTTL logic levels and a backplane operating at GTL(P)
logic levels. High speed backplane operation is a direct
result of GTL(P)’s reduced output swing (<1V), reduced
input threshold levels and output edge rate control. The
edge rate control minimizes bus settling time. GTLP is a
Fairchild Semiconductor derivative of the Gunning Trans-
ceiver logic (GTL) JEDEC standard JESD8-3.
■ Interface between LVTTL and GTLP logic levels
■ Edge Rate Control to minimize noise on the GTLP port
■ Power up/down high impedance for live insertion
■ 1:6 fanout clock driver for LVTTL port
■ 1:2 fanout clock driver for GTLP port
■ LVTTL compatible driver and control inputs
■ Flow through pinout optimizes PCB layout
■ Open drain on GTLP to support wired-or connection
■ A Port source/sink −24/+24 mA
Fairchild’s GTL(P) has internal edge-rate control and is
process, voltage, and temperature (PVT) compensated. Its
function is similar to BTL and GTL but with different output
levels and receiver threshold. GTLP output LOW level is
typically less than 0.5V, the output level HIGH is 1.5V and
the receiver threshold is 1.0V.
■ B Port sink 50 mA
■ −40°C to +85°C temperature capability
■ Low voltage version of GTLP6C816
Ordering Code:
Order Number
Package Number Package Description
GTLP6C816AMTC
MTC24
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pin Descriptions
Connection Diagram
Pin Names
Description
TTLIN, GTLPIN Clock Inputs
(LVTTL and GTLP respectively)
OEB
OEA
Output Enable (Active LOW)
GTLP Port (LVTTL Levels)
Output Enable (Active LOW)
TTL Port (LVTTL Levels)
VCCT.GNDT
VCC
TTL Output Supplies
Internal Circuitry VCC
GNDG
OBn GTLP Output Grounds
Voltage Reference Input
TTL Buffered Clock Outputs
GTLP Buffered Clock Outputs
VREF
OA0–OA5
OB0–OB1
© 1999 Fairchild Semiconductor Corporation
DS500179
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Functional Description
The GTLP6C816A is a clock driver providing LVTTL-to-GTLP clock translation, and GTLP-to-LVTTL clock translation in the
same package. The LVTTL-to-GTLP direction is a 1:2 clock driver path with a single Enable pin (OEB). For the GTLP-to-
LVTTL direction the clock receiver path is a 1:6 buffer with a single Enable control (OEA). Data polarity is inverting for both
directions.
Truth Tables
Inputs
Outputs
TTLIN
OEB
OBn
L
H
L
L
L
H
X
H
High Z
Inputs
Outputs
GTLPIN
OEA
OAn
L
H
L
L
L
H
X
H
High Z
Logic Diagram
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2
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions (Note 3)
Supply Voltage (VCC
)
−0.5V to +4.6V
−0.5V to +4.6V
DC Input Voltage (VI)
DC Output Voltage (VO)
Outputs 3-STATE
Supply Voltage VCC
3.15V to 3.45V
Bus Termination Voltage (VTT
)
−0.5V to +4.6V
−0.5V to +4.6V
GTLP
GTL
1.47V to 1.53V
1.14V to 1.26V
0.98V to 1.02V
Outputs Active (Note 2)
DC Output Sink Current into
OA-Port IOL
VREF
48 mA
−48 mA
100 mA
−50 mA
Input Voltage (VI) on INA-Port
and Control Pins
DC Output Source Current
from OA-Port IOH
0.0V to 3.45V
HIGH Level Output Current (IOH
)
DC Output Sink Current into
OB-Port in the LOW State IOL
OA-Port
−24 mA
LOW Level Output Current (IOL
OA-Port
)
DC Input Diode Current (IIK
)
+24 mA
+50 mA
VI < 0V
OB-Port
DC Output Diode Current (IOK
)
Operating Temperature (TA)
−40°C to +85°C
Note 1: Absolute Maximum continuous ratings are those values beyond
which damage to the device may occur. Exposure to these conditions or
conditions beyond those indicated may adversely affect device reliability.
Functional operation under absolute maximum rated conditions is not
implied.
V
V
O < 0V
−50 mA
+50 mA
O > VCC
ESD Rating
> 2000V
Storage Temperature (TSTG
)
−65°C to +150°C
Note 2: I Absolute Maximum Rating must be observed.
o
Note 3: Unused inputs must be held High or Low.
3
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DC Electrical Characteristics
Over Recommended Operating Free-Air Temperature Range, V
= 1.0V (unless otherwise noted).
REF
Typ
(Note 4)
Symbol
GTLPIN
Test Conditions
Min
+0.05
Max
Units
V
V
V
V
V
V
V
V
V
V
V
IH
REF
TT
Others
GTLPIN
Others
2.0
0.0
V
−0.05
IL
REF
0.8
V
V
V
V
(Note 5) GTLP
1.0
1.5
REF
(Note 5) GTLP
TT
IK
V
V
= 3.15V
= 3.15V
I = −18 mA
−1.2
CC
CC
I
OAn-Port
I
I
I
I
I
I
I
I
I
= −100 µA
= −18 mA
= −24 mA
= 100 µA
= 18 mA
= 24 mA
= 100 µA
= 40 mA
= 50 mA
V
−0.2
CC
OH
OH
OH
OH
OL
OL
OL
OL
OL
OL
2.4
2.2
V
V
V
V
V
OAn-Port
OBn-Port
V
V
= 3.15V
= 3.15V
0.2
0.4
0.5
0.2
0.4
0.55
5
OL
OL
CC
CC
I
I
TTLIN/
V
V
= 3.45V
= 3.45V
V = 3.45V
I
I
CC
CC
µA
µA
Control Pins
GTLPIN
V = 0V
−5
I
V = V
5
I
TT
V = 0
−5
I
TTLIN
V
V
= 0
= 0
V or V = 0V to 3.45V
30
µA
µA
OFF
CC
CC
I
O
GTLPIN
V or V = 0V to V
TT
30
I
O
I
OAn or OBn Ports
V
= 0 to 1.5V
= 3.45V
30
µA
PU/PD
OZH
CC
CC
OE = Don’t Care
I
OAn-Port
OBn-Port
OAn-Port
OAn or
V
V
V
V
=3.45V
= 1.5V
= 0
5
5
O
O
O
µA
µA
I
I
V
V
= 3.45V
= 3.45V
−5
10
10
10
2
OZL
CC
CC
CC
Outputs HIGH
Outputs LOW
5.5
5
OBn Ports
mA
mA
pF
V = V or GND
Outputs Disabled
5.5
I
CC
∆I
TTLIN
V
= 3.45V
V = V −0.6
I CC
CC
CC
C
C
Control Pins/GTLPIN/TTLIN
OAn-Port
V = V or 0
4.5
6.0
8.0
I
I
CC
V = V or 0
O
I
CC
OBn-Port
V = V or 0
I CC
Note 4: All typical values are at V = 3.3V and T = 25°C.
CC
A
Note 5: GTLP V
and V are specified to 2% tolerance since signal integrity and noise margin can be significantly degraded if these supplies are noisy.
TT
REF
In addition, V and R
can be adjusted to accommodate backplane impedances other than 50Ω, within the boundaries of not exceeding the DC Abso-
TERM
TT
lute I ratings. Similarly V
can be adjusted to compensate for changes in V
.
TT
OL
REF
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4
AC Electrical Characteristics
Over recommended range of supply voltage and operating free air temperature. V
= 1.0V (unless otherwise noted).
REF
C = 30 pF for OBn-Port and C = 50 pF for OAn-Port.
L
L
Typ
(Note 6)
Symbol
From (Input)
To (Output)
Min
Max
Units
f
TTLIN
GTLPIN
TTLIN
OBn
OAn
OBn
175
175
TOGGLE
MHz
ns
t
t
1.3
0.9
2.3
2.6
4.0
4.3
PLH
PHL
t
t
t
t
t
t
OEB
OBn
1.5
1.2
2.6
2.5
1.3
1.3
1.2
2.0
4.1
4.1
ns
ns
ns
PLH
PHL
Transition Time, OB Outputs (20% to 80%)
Transition Time, OB outputs (20% to 80%)
Transition Time, OA outputs (10% to 90%)
Transition Time, OA outputs (10% to 90%)
RISE
FALL
RISE
FALL
t
t
t
t
, t
OEA
OAn
0.5
0.5
1.9
2.1
2.9
2.4
3.6
3.5
4.8
4.4
5.7
5.3
ns
ns
PZH PZL
, t
PLZ PHZ
GTLPIN
OAn
PLH
PHL
Note 6: All typical values are at V = 3.3 V and T = 25°C.
CC
A
Extended Electrical Characteristics
Over recommended ranges of supply voltage and operating free-air temperature VREF = 1.0V (unless otherwise noted).
C
L = 30 pF for B Port and C = 50 pF for A Port
L
From
To
Typ
(Note 7)
0.1
Symbol
(Input)
Min
Max
Unit
(Output)
t
(Note 8)
(Note 8)
A
A
A
A
B
B
B
B
B
B
B
B
B
A
A
A
A
A
0.2
0.6
1.0
1.3
0.7
0.4
1.1
1.0
2.4
OSLH
OSHL
ns
t
0.1
t
t
t
t
t
t
t
(Note 9)
0.3
ns
ns
PS
(Note 10)(Note 11)
PV(HL)
(Note 8)
(Note 8)
0.1
0.1
0.2
0.1
OSLH
OSHL
ns
(Note 8)
ns
ns
ns
OST
(Note 9)
PS
PV
(Note 10)
Note 7: All typical values are at V = 3.3 V and T = 25°C.
CC
A
Note 8: t
/t
and t
– Output-to-Output skew is defined as the absolute value of the difference between the actual propagation delay for all outputs
OST
OSHL OSLH
within the same packaged device. The specifications are given for specific worst case V and temperature and apply to any outputs switching in the same
CC
direction dither HIGH-to-LOW (t
) or LOW-to-HIGH (t
) or in opposite directions both HL and LH (t
). This parameter is guaranteed by design and
OST
OSHL
OSLH
statistical process distribution. Actual skew values between the GTLP outputs could vary on the backplane due to the loading and impedance seen by the
device.
Note 9: t – Pin or Transition skew is defined as the difference between the LOW-to-HIGH transition and the HIGH-to-LOW transition on the same pin. The
PS
parameter is measured across all the outputs of the same chip is specified for a specific worst case V and temperature. This parameter is guaranteed by
CC
design and statistical process distribution. Actual skew values between the GTLP outputs could vary on the backplane due to the loading and impedance
seen by the device.
Note 10: t – Part-to-Part skew is defined as the absolute value of the difference between the actual propagation delay for all outputs from device-to-device.
PV
The parameter is specified for a specific worst case V and temperature. This parameter is guaranteed by design and statistical process distribution. Actual
CC
skew values between the GTLP output could vary on the backplane due to the loading and impedance seen by the device.
Note 11: Due to the open drain structure on GTLP outputs t
and t
in the A-to-B direction are not specified. Skew on these paths is dependent on the
OST
PV(LH)
V
and R values on the backplane.
T
TT
5
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Test Circuit and Timing Waveforms
Test Circuit for A Outputs
Test Circuit for B Outputs
Note A: C includes probes and jig capacitance.
Note A: C includes probes and jig capacitance.
L
L
Note B: For B-Port C = 30 pF is used for worst case.
L
Voltage Waveform - Propagation Delay Times
Voltage Waveform - Enable and Disable Times
Output Waveform 1 is for an output with internal conditions such that the
output is LOW except when disabled by the control output
Output Waveforms 2 is for an output with internal conditions such that the
output is HIGH except when disabled by the control output
Input and Measure Conditions
A or LVTTL
Pins
B or GTLP
Pins
VinHIGH
VinLOW
VM
3.0
0.0
1.5
1.5
0.0
1.0
N/A
N/A
VX
V
OL + 0.3V
VY
VOH + 0.3V
All input pulses have the following characteristics: Frequency = 10MHz, t
= t
= 2 ns, Z = 50Ω.
RISE
FALL O
The outputs are measured one at a time with one transition per measurement.
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6
Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC24
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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