HCPL3700S [FAIRCHILD]

AC/DC TO LOGIC INTERFACE OPTOCOUPLER; AC / DC到逻辑接口光电耦合器
HCPL3700S
型号: HCPL3700S
厂家: FAIRCHILD SEMICONDUCTOR    FAIRCHILD SEMICONDUCTOR
描述:

AC/DC TO LOGIC INTERFACE OPTOCOUPLER
AC / DC到逻辑接口光电耦合器

光电 输出元件
文件: 总9页 (文件大小:142K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
AC/DC TO LOGIC INTERFACE  
OPTOCOUPLER  
HCPL-3700  
DESCRIPTION  
The HCPL-3700 voltage/current threshold detection optocoupler consists of  
an AlGaAs LED connected to a threshold sensing input buffer IC which are  
optically coupled to a high gain darlington output. The input buffer chip is  
capable of controlling threshold levels over a wide range of input voltages  
with a single resistor. The output is TTL and CMOS compatible.  
8
1
TRUTH TABLE  
FEATURES  
• AC or DC input  
(Positive Logic)  
• Programmable sense voltage  
• Logic level compatibility  
• Threshold guaranteed over temperature  
(0°C to 70°C)  
• Optoplanar™ construction for high common  
mode immunity  
Input Output  
8
H
L
8
1
L
H
1
• UL recognized (file # E90700)  
µF bypass capacitor  
A 0.1  
must be connected between  
pins 8 and 5.  
APPLICATIONS  
AC  
1
2
3
4
8
V
CC  
• Low voltage detection  
• 5 V to 240 V AC/DC voltage sensing  
• Relay contact monitor  
• Current sensing  
DC+  
DC-  
AC  
7
6
5
NC  
R
X
AC/DC  
POWER  
• Microprocessor Interface  
• Industrial controls  
VO  
LOGIC  
HCPL-3700  
GND  
GND 1  
GND 2  
(No derating required up to 70°C)  
ABSOLUTE MAXIMUM RATINGS  
Parameter  
Symbol  
TSTG  
Value  
-55 to +125  
-40 to +85  
260 for 10 sec  
50 (MAX)  
Units  
°C  
Storage Temperature  
Operating Temperature  
Lead Solder Temperature  
TOPR  
°C  
TSOL  
°C  
EMITTER  
Average  
Surge  
Input Current  
3 ms, 120 Hz Pulse Rate  
10 µs, 120 Hz Pulse Rate  
IIN  
140 (MAX)  
500 (MAX)  
-0.5 (MIN)  
230 (MAX)  
305 (MAX)  
mA  
Transient  
Input Voltage (Pins 2-3)  
Input Power Dissipation  
Total Package Power Dissipation  
DETECTOR  
VIN  
PIN  
PT  
V
(Note 1)  
(Note 2)  
mW  
mW  
Output Current (Average)  
Supply Voltage (Pins 8-5)  
Output Voltage (Pins 6-5)  
Output Power Dissipation  
(Note 3)  
(Note 4)  
IO  
VCC  
VO  
30 (MAX)  
-0.5 to 20  
-0.5 to 20  
210 (MAX)  
mA  
V
V
PO  
mW  
200003A  
AC/DC TO LOGIC INTERFACE  
OPTOCOUPLER  
HCPL-3700  
ELECTRICAL CHARACTERISTICS (TA = 0°C to 70°C Unless otherwise specified)  
Parameter  
Test Conditions  
Symbol  
Min  
Typ  
Max  
Unit  
ITH+  
ITH-  
1.96  
1.00  
2.4  
1.2  
3.11  
1.62  
mA  
mA  
Input Threshold Current  
(VIN = VTH+, VCC = 4.5 V)  
(VO = 0.4 V, IO ! 4.2 mA) (Note 5)  
(VIN = V2 - V3, Pins 1 & 4 Open)  
(VCC = 4.5 V, VO = 0.4 V)  
VTH+  
3.35  
2.01  
3.8  
2.5  
4.05  
2.86  
V
V
DC  
(Note 5) (IO ! 4.2 mA)  
(Pins 2,3)  
(VIN = V2 - V3, Pins 1 & 4 Open)  
(VCC = 4.5 V, VO = 2.4 V)  
VTH-  
Input  
(Note 5) (IO " 100 µA)  
Threshold  
Voltage  
VIN = V1 - V4  
# #  
(Pins 2 & 3 Open)  
(VCC = 4.5 V, VO = 0.4 V)  
(Note 5) (IO ! 4.2 mA)  
VTH+  
4.23  
2.87  
5.0  
3.7  
5.50  
4.20  
V
V
AC  
(Pins 1,4)  
VIN = V1 - V4  
# #  
(Pins 2 & 3 Open)  
(VCC = 4.5 V, VO = 2.4 V)  
(Note 5) (IO " 100 µA)  
(IHYS = ITH+ - ITH-)  
VTH-  
IHYS  
1.2  
1.3  
mA  
V
Hysteresis  
(VHYS = VTH+ - VTH-)  
VHYS  
(VIHC1 = V2 - V3, V3 = GND)  
(IIN = 10 mA, Pins 1 & 4  
Connected to Pin 3)  
VIHC1  
5.4  
6.1  
6.3  
7.0  
6.6  
V
V
(VIHC2 = V - V )  
#
#
1
4
( I = 10 mA)  
VIHC2  
7.3  
#
#
IN  
Input Clamp Voltage  
(Pins 2 & 3 Open)  
(VIHC3 = V2 - V3, V3 = GND)  
(IIN = 15 mA; Pins 1 & 4 Open)  
(VILC = V2 - V3, V3 = GND)  
(IIN = -10 mA)  
VIHC3  
VILC  
IIN  
12.5  
-0.75  
3.7  
13.4  
V
V
(VIN = V2 - V3 = 5.0 V)  
(Pins 1 & 4 Open)  
3.0  
4.4  
mA  
Input Current  
Bridge Diode  
(IIN = 3 mA)  
VD1,2  
VD3,4  
0.65  
0.65  
V
V
Forward Voltage  
(IIN = 3 mA)  
(VCC = 4.5 V; IOL = 4.2 mA)  
(Note 5)  
Logic Low Output Voltage  
Logic High Output Current  
VOL  
IOH  
0.04  
0.4  
100  
4
V
(Note 5) (VOH = VCC = 18 V)  
(V2 - V3 = 5.0 V; VO = Open)  
(VCC = 5 V)  
µA  
mA  
ICCL  
1.0  
Logic Low Supply Current  
Logic High Supply Current  
(VCC = 18 V; VO = Open)  
(f = 1 MHz; VIN = 0V)  
(Pins 2 & 3, Pins 1 & 4 Open)  
ICCH  
CIN  
0.01  
50  
4
µA  
pF  
Input Capacitance  
200003A  
AC/DC TO LOGIC INTERFACE  
OPTOCOUPLER  
HCPL-3700  
RECOMMENDED OPERATING CONDITIONS  
Parameter  
Symbol  
Min  
2
Max  
18  
70  
4
Units  
V
Supply Voltage  
VCC  
TA  
f
Operating Temperature  
Operating Frequency  
0
°C  
0
kHz  
SWITCHING CHARACTERISTICS (TA = 25°C, VCC = 5 V Unless otherwise specified)  
AC Characteristics  
Test Conditions  
(RL = 4.7 $, CL = 30 pF)  
(Note 6)  
Symbol  
Min  
Typ  
Max  
Unit  
Propagation Delay Time  
(to Output Low Level)  
TPHL  
6.0  
15  
µs  
Propagation Delay Time  
(to Output High Level)  
(RL = 4.7 $, CL = 30 pF)  
(Note 6)  
TPLH  
25.0  
40  
µs  
Output Rise Time (10-90%)  
Output Fall Time (90-10%)  
Common Mode Transient Immunity  
(RL = 4.7 $, CL = 30 pF)  
(RL = 4.7 $, CL = 30 pF)  
(IIN = 0 mA,RL = 4.7 $)  
tr  
tf  
45  
µs  
µs  
0.5  
(at Output High Level)  
(VO min = 2.0 V, VCM = 1400 V)  
(Notes 7,8)  
#CMH#  
#CML#  
4000  
600  
V/µs  
V/µs  
Common Mode Transient Immunity (IN = 3.11 mA,RL = 4.7 $)  
(at Output Low Level)  
(VO max = 0.8 V, VCM = 140 V)  
(Notes 7,8)  
PACKAGE CHARACTERISTICS (TA = 0°C to 70°C Unless otherwise specified)  
Characteristics  
Test Conditions  
(Relative humidity < 50%)  
(TA = 25°C, t = 1 min)  
(Notes 9,10)  
Symbol  
Min  
Typ  
Max  
Unit  
Withstand Insulation Voltage  
VISO  
2500  
VRMS  
Resistance (input to output)  
Capacitance (input to output)  
(Note 9) (VIO = 500 Vdc)  
(f = 1 MHZ, VIO = 0 Vdc)  
RI-O  
CI-O  
1012  
0.6  
$
pF  
200003A  
AC/DC TO LOGIC INTERFACE  
OPTOCOUPLER  
HCPL-3700  
NOTES  
1. Derate linearly above 70°C free-air temperature at a rate of 1.8 mW/°C.  
2. Derate linearly above 70°C free-air temperature at a rate of 2.5 mW/°C.  
3. Derate linearly above 70°C free-air temperature at a rate of 0.6 mA/°C.  
4. Derate linearly above 70°C free-air temperature at a rate of 1.9 mW/°C.  
5. Logic low output level at pin 6 occurs when VIN!VTH+ and when VIN%VTH- once VIN exceeds VTH+. Logic high output level at pin 6  
occurs when VIN"VTH- and when VIN&VTH+ once VIN decreases below VTH-.  
6. TPHL propagation delay is measured from the 2.5 V level of the leading edge of a 5.0 V input pulse (1 µs rise time) to the 1.5 V level  
on the leading edge of the output pulse. TPLH propagation delay is measured on the trailing edges of the input and output pulse.  
(Refer to Fig. 9)  
7. Common mode transient immunity in logic high level is the maximum tolerable (positive) dVcm/dt on the leading edge of the  
common mode pulse signal VCM, to assure that the output will remain in a logic high state (i.e., VO%2.0 V). Common mode transient  
immunity in logic low level is the maximum tolerable (negative) dVcm/dt on the trailing edge of the common mode pulse signal, VCM  
,
to assure that the output will remain in a logic low state (i.e., VO&0.8 V). (Refer to Fig.10)  
8. In applications where dVcm/dt may exceed 50,000 V/µs (Such as static discharge), a series resistor, RCC, should be included to  
protect the detector chip from destructive surge currents. The recommended value for RCC is 240 $ per volt of allowable drop in  
VCC (between pin 8 and VCC) with a minimum value of 240 $.  
9. Device is considered a two terminal device: Pins 1, 2, 3 and 4 are shorted together and Pins 5, 6, 7 and 8 are shorted together.  
10. The 2500 VRMS/1 min. capability is validated by 3.0 kVRMS/1 sec. dielectric voltage withstand test.  
11. AC voltage is instantaneous voltage for VTH+ & VTH-  
.
12. All typicals at TA = 25°C, VCC = 5 V unless otherwise specified.  
200003A  
AC/DC TO LOGIC INTERFACE  
OPTOCOUPLER  
HCPL-3700  
Fig. 1 Logic Low Supply Current vs. Operating Supply Voltage  
Fig. 2 Input Current vs. Input Voltage  
4.0  
50  
DC (Pins 1,2 shorted together  
pins 3,4 shorted together)  
45  
40  
35  
30  
25  
20  
15  
10  
5
3.5  
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
0.0  
DC (Pins 1 & 4 Open)  
0
AC (pins 2 & 3 Open)  
-5  
-10  
4
6
8
10  
12  
14  
16  
18  
20  
0
2
4
6
8
10  
12  
14  
V
- OPERATING SUPPLY VOLTAGE (V)  
V
- INPUT VOLTAGE (V)  
CC  
IN  
Fig. 4 Current Threshold/Voltage Threshold  
vs.Temperature  
Fig. 3 Input Current/Low Level Output Voltage  
vs.Temperature  
4.2  
3.2  
4.2  
4.0  
3.8  
3.6  
3.4  
3.2  
3.0  
2.8  
2.6  
2.4  
2.2  
2.0  
1.8  
120  
4.0  
3.8  
3.6  
3.4  
3.2  
3.0  
2.8  
2.6  
2.4  
2.2  
2.0  
1.8  
3.0  
2.8  
2.6  
2.4  
2.2  
2.0  
1.8  
1.6  
1.4  
1.2  
1.0  
0.8  
110  
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
VTH+  
ITH+  
IIN  
VIN = 5.0 V  
(PINS 2 and 3)  
VCC = 5.0 V  
VOL  
VCC = 5.0 V  
IOL = 4.2 mA  
VTH-  
ITH-  
-40  
-20  
0
25  
45  
65  
85  
-40  
-20  
0
25  
45  
65  
85  
T
- TEMPERATURE (˚C)  
T
- TEMPERATURE (˚C)  
A
A
Fig. 5 Propagation Delay vs.Temperature  
Fig. 6 Rise and Fall Time vs.Temperature  
70  
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
0.8  
0.7  
0.6  
0.5  
0.4  
0.3  
0.2  
0.1  
0.0  
60  
50  
40  
30  
20  
10  
0
Tf  
TPLH  
TPHL  
Tr  
-60  
-40  
-20  
0
20  
40  
60  
80  
100  
-40  
-20  
0
25  
45  
65  
85  
T
- TEMPERATURE (˚C)  
T
- TEMPERATURE (˚C)  
A
A
200003A  
AC/DC TO LOGIC INTERFACE  
OPTOCOUPLER  
HCPL-3700  
Fig. 7 Logic High Supply Current  
vs.Temperature  
Fig. 8 External Threshold Characteristics V+/V- vs. Rx  
300  
1000  
100  
10  
V- (AC)  
V
CC = 18 V  
V+ (AC)  
250  
200  
VO = OPEN  
IIN = 0 mA  
V+ (DC)  
150  
100  
V- (DC)  
50  
0
1
-60  
0
40  
80  
120  
160  
200  
240  
-40  
-20  
0
20  
40  
60  
80  
100  
R
X
- EXTERNAL SERIES RESISTOR (K$)  
T
- TEMPERATURE (˚C)  
A
200003A  
AC/DC TO LOGIC INTERFACE  
OPTOCOUPLER  
HCPL-3700  
+5V  
5V  
2.5V  
0V  
1
2
3
4
AC  
VCC  
8
7
6
5
Input  
(VIN  
.1uf  
bypass  
)
Pulse  
RL  
DC+  
DC-  
AC  
Generator  
tr = 5ns  
tPHL  
tPLH  
Output  
(VO  
ZO= 50  
$
VO  
)
VO  
Output  
(VO  
90%  
90%  
GND  
)
1.5 V  
VOL  
10%  
10%  
tf  
tr  
VIN  
Pulse Amplitude = 50 V  
Pulse Width = 1 ms  
f = 100 Hz  
Fig. 9. Switching Test Circuit  
T = Tf = 1.0 ms (10 - 90%)  
r
VCM  
VCM  
H
L
IIN  
RCC*  
+5V  
1
2
3
4
AC  
VCC  
8
7
6
5
A
B
.1uf  
bypass  
RL  
DC+  
DC-  
AC  
VCM  
5V  
5V  
Output  
VO  
(VO  
)
VFF  
GND  
VO  
CMH  
CL**  
Switching Pos. (A)  
IIN = 0 mA  
VO (Min)  
VCM  
+
-
* SEE NOTE 8  
Pulse Gen  
VO (Max)  
** CL IS 30 pF, WHICH INCLUDES PROBE  
AND STRAY WIRING CAPACITANCE  
Switching Pos. (B)  
IIN = 3.11 mA  
VO  
VOL  
CML  
Fig. 10. Test Circuit for Common Mode Transient Immunity and Typical Waveforms  
200003A  
AC/DC TO LOGIC INTERFACE  
OPTOCOUPLER  
HCPL-3700  
Package Dimensions (Through Hole)  
Package Dimensions (Surface Mount)  
0.390 (9.91)  
0.370 (9.40)  
PIN 1  
ID.  
PIN 1  
ID.  
4
3
2
1
4
5
3
6
2
7
1
8
0.270 (6.86)  
0.250 (6.35)  
0.270 (6.86)  
0.250 (6.35)  
0.390 (9.91)  
0.370 (9.40)  
5
6
7
8
0.070 (1.78)  
0.045 (1.14)  
0.300 (7.62)  
TYP  
0.070 (1.78)  
0.045 (1.14)  
0.200 (5.08)  
0.115 (2.92)  
0.020 (0.51)  
MIN  
0.020 (0.51) MIN  
0.016 (0.41)  
0.008 (0.20)  
0.154 (3.90)  
0.120 (3.05)  
0.045 [1.14]  
0.022 (0.56)  
0.016 (0.41)  
0.022 (0.56)  
0.016 (0.41)  
15° MAX  
0.016 (0.40)  
0.008 (0.20)  
0.100 (2.54) TYP  
0.315 (8.00)  
MIN  
0.300 (7.62)  
TYP  
0.100 (2.54)  
TYP  
0.405 (10.30)  
MIN  
Lead Coplanarity : 0.004 (0.10) MAX  
Package Dimensions (0.4”Lead Spacing)  
4
3
2
1
PIN 1  
ID.  
0.270 (6.86)  
0.250 (6.35)  
5
6
7
8
0.390 (9.91)  
0.370 (9.40)  
0.070 (1.78)  
0.045 (1.14)  
0.200 (5.08)  
0.115 (2.92)  
NOTE  
All dimensions are in inches (millimeters)  
0.004 (0.10) MIN  
0.154 (3.90)  
0.120 (3.05)  
0.022 (0.56)  
0.016 (0.41)  
0° to15°  
0.016 (0.40)  
0.008 (0.20)  
0.100 (2.54) TYP  
0.400 (10.16)  
TYP  
200003A  
AC/DC TO LOGIC INTERFACE  
OPTOCOUPLER  
DISCLAIMER  
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO  
ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME  
ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;  
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.  
LIFE SUPPORT POLICY  
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES  
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR  
CORPORATION. As used herein:  
1. Life support devices or systems are devices or systems  
which, (a) are intended for surgical implant into the body,  
or (b) support or sustain life, and (c) whose failure to  
perform when properly used in accordance with  
instructions for use provided in the labeling, can be  
reasonably expected to result in a significant injury of the  
user.  
2. A critical component in any component of a life support  
device or system whose failure to perform can be  
reasonably expected to cause the failure of the life support  
device or system, or to affect its safety or effectiveness.  
www.fairchildsemi.com  
© 2000 Fairchild Semiconductor Corporation  
200003A  

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