HUF76113DK8 [FAIRCHILD]
6A, 30V, 0.032 Ohm, Dual N-Channel, Logic Level UltraFET Power MOSFET; 6A ， 30V ， 0.032欧姆，双N沟道逻辑电平UltraFET功率MOSFET
| 型号： | HUF76113DK8 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | 6A, 30V, 0.032 Ohm, Dual N-Channel, Logic Level UltraFET Power MOSFET |
| 文件： | 总12页 (文件大小：339K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HUF76113DK8
Data Sheet
January 2003
6A, 30V, 0.032 Ohm, Dual N-Channel,
Logic Level UltraFET Power MOSFET
Features
• Logic Level Gate Drive
• 6A, 30V
This N-Channel power MOSFET is
®
manufactured using the innovative
• Ultra Low On-Resistance, r
= 0.032Ω
UltraFET process. This advanced
process technology achieves the
DS(ON)
®
• Temperature Compensating PSPICE Model
lowest possible on-resistance per silicon area, resulting in
outstanding performance. This device is capable of
withstanding high energy in the avalanche mode and the
diode exhibits very low reverse recovery time and stored
charge. It was designed for use in applications where power
efficiency is important, such as switching regulators, switching
converters, motor drivers, relay drivers, low-voltage bus
switches, and power management in portable and battery-
operated products.
™
• Temperature Compensating SABER Model
• Thermal Impedance SPICE Model
• Thermal Impedance SABER Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• Related Literature
- TB334, “Guidelines for Soldering Surface Mount
Components to PC Boards”
Formerly developmental type TA76113.
Ordering Information
Symbol
PART NUMBER
PACKAGE
BRAND
76113DK8
D1(8)
D1(7)
HUF76113DK8
MS-012AA
NOTE: When ordering, use the entire part number. Add the suffix T
to obtain the variant in tape and reel, e.g., HUF76113DK8T.
S1(1)
G1(2)
D2(6)
D2(5)
S2(3)
G2(4)
Packaging
JEDEC MS-012AA
BRANDING DASH
5
1
2
3
4
©2003 Fairchild Semiconductor Corporation
HUF76113DK8 Rev. B1
HUF76113DK8
o
Absolute Maximum Ratings T = 25 C, Unless Otherwise Specified
A
HUF76113DK8
UNITS
Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
30
30
V
V
V
DSS
Drain to Gate Voltage (R
= 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
DGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
±20
GS
Drain Current
o
Continuous (T = 25 C, V
A
= 10V) (Figure 2) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . I
6
1.8
1.7
A
A
A
GS
D
D
o
Continuous (T = 100 C, V
= 5V) (Note 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
= 4.5V) (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
A
GS
o
Continuous (T = 100 C, V
A
GS
D
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I
Figure 4
DM
Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E
Figure 6
AS
Power Dissipation (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
2.5
0.02
W
D
o
o
Derate Above 25 C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
W/ C
o
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T , T
J
-55 to 150
C
STG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
o
300
260
C
C
L
o
pkg
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
o
o
1. T = 25 C to 125 C.
J
2. 50oC/W measured using FR-4 board at 1 second.
o
2
3. 228 C/W measured using FR-4 board with 0.006 in footprint at 1000 seconds.
o
Electrical Specifications T = 25 C, Unless Otherwise Specified
A
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
BV
I
= 250µA, V
= 0V (Figure 12)
30
-
-
-
-
-
-
V
DSS
D
GS
GS
GS
I
V
V
V
= 25V, V
= 25V, V
= ±20V
= 0V
1
µA
µA
nA
DSS
DS
DS
GS
o
= 0V, T = 150 C
-
250
±100
C
Gate to Source Leakage Current
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage
Drain to Source On Resistance
I
-
GSS
V
V
= V , I = 250µA (Figure 11)
DS
1
-
-
3
V
GS(TH)
GS
D
r
I
I
I
= 6A, V
GS
= 10V (Figures 9, 10)
0.026
0.033
0.035
0.032
0.041
0.043
Ω
Ω
Ω
DS(ON)
D
D
D
= 1.8A, V
= 1.7A, V
= 5V (Figure 9)
-
GS
GS
= 4.5V (Figure 9)
-
THERMAL SPECIFICATIONS
2
o
Thermal Resistance Junction to Ambient
R
Pad Area = 0.76 in (Note 2)
-
-
-
-
-
-
50
C/W
θJA
2
o
Pad Area = 0.027 in (See TB377)
191
228
C/W
2
o
Pad Area = 0.006 in (See TB377)
C/W
SWITCHING SPECIFICATIONS (V
Turn-On Time
= 4.5V)
GS
t
V
V
= 15V, I
= 4.5V, R
1.7A, R = 8.8Ω,
-
-
-
-
-
-
-
110
ns
ns
ns
ns
ns
ns
ON
DD
D
L
= 18Ω,
GS
GS
Turn-On Delay Time
Rise Time
t
17
57
32
38
-
-
d(ON)
(Figure 15)
t
-
r
Turn-Off Delay Time
Fall Time
t
-
-
d(OFF)
t
f
Turn-Off Time
t
105
OFF
©2003 Fairchild Semiconductor Corporation
HUF76113DK8 Rev. B1
HUF76113DK8
o
Electrical Specifications T = 25 C, Unless Otherwise Specified
A
PARAMETER
SWITCHING SPECIFICATIONS (V
Turn-On Time
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
= 10V)
GS
t
V
= 15V, I
6A, R = 2.5Ω, V
GS
=
-
-
-
-
-
-
-
60
ns
ns
ns
ns
ns
ns
ON
DD
10V,
D
L
Turn-On Delay Time
Rise Time
t
6.5
33
50
40
-
-
d(ON)
R
= 18Ω
(Figure 16)
GS
t
-
r
Turn-Off Delay Time
Fall Time
t
-
-
d(OFF)
t
f
Turn-Off Time
t
135
OFF
GATE CHARGE SPECIFICATIONS
Total Gate Charge
Q
V
V
V
= 0V to 10V
= 0V to 5V
= 0V to 1V
V
R
= 15V, I
D
= 8.3Ω
1.8A,
-
-
-
-
-
16.0
8.4
19.2
10.2
0.66
-
nC
nC
nC
nC
nC
g(TOT)
GS
GS
GS
DD
L
Gate Charge at 5V
Q
g(5)
I
= 1.0mA
g(REF)
(Figure 14)
Threshold Gate Charge
Q
0.55
1.50
3.90
g(TH)
Gate to Source Gate Charge
Gate to Drain “Miller” Charge
CAPACITANCE SPECIFICATIONS
Input Capacitance
Q
Q
gs
gd
-
C
V
= 25V, V = 0V,
GS
-
-
-
605
275
40
-
-
-
pF
pF
pF
ISS
DS
f = 1MHz
(Figure 13)
Output Capacitance
C
OSS
RSS
Reverse Transfer Capacitance
C
Source to Drain Diode Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
1.25
1.00
40
UNITS
Source to Drain Diode Voltage
V
I
I
I
I
= 6A
-
-
V
V
SD
SD
SD
SD
SD
= 1.8A
Reverse Recovery Time
t
= 1.8A, dI /dt = 100A/µs
SD
-
-
-
-
ns
nC
rr
Reverse Recovered Charge
Q
= 1.8A, dI /dt = 100A/µs
42
RR
SD
Typical Performance Curves
1.2
1.0
0.8
0.6
0.4
0.2
0
7
6
5
4
3
2
o
V
= 10V, R
= 50 C/W
JA
GS
θ
o
V
= 4.5V, R
= 228 C/W
JA
GS
θ
1
0
25
50
75
100
125
150
0
25
50
75
100
125
150
o
o
T , AMBIENT TEMPERATURE ( C)
T , AMBIENT TEMPERATURE ( C)
A
A
FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
AMBIENT TEMPERATURE
©2003 Fairchild Semiconductor Corporation
HUF76113DK8 Rev. B1
HUF76113DK8
Typical Performance Curves (Continued)
2
DUTY CYCLE - DESCENDING ORDER
1
0.5
0.2
o
R
= 228 C/W
JA
θ
0.1
0.05
0.02
0.01
0.1
P
DM
t
1
0.01
0.001
t
2
NOTES:
DUTY FACTOR: D = t /t
SINGLE PULSE
1
2
PEAK T = P
J
x Z
x R
+ T
JA A
DM
JA
θ
θ
-5
-4
10
-3
-2
10
-1
10
0
1
2
3
10
10
10
t, RECTANGULAR PULSE DURATION (s)
10
10
10
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
500
o
o
= 25 C
R
= 228 C/W
T
JA
θ
C
FOR TEMPERATURES
o
ABOVE 25 C DERATE PEAK
CURRENT AS FOLLOWS:
V
= 10V
GS
100
10
1
150 - T
A
I = I
25
125
V
= 5V
GS
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
-5
-4
-3
10
-2
10
-1
0
1
2
3
10
10
10
t, PULSE WIDTH (s)
10
10
10
10
FIGURE 4. PEAK CURRENT CAPABILITY
50
If R = 0
= (L)(I )/(1.3*RATED BV
500
100
t
- V )
DD
T
T
= MAX RATED
AV
If R ≠ 0
AS
DSS
J
o
= 25 C
A
t
= (L/R)ln[(I *R)/(1.3*RATED BV
- V ) +1]
DSS DD
AV
AS
100µs
o
STARTING T = 25 C
J
10
1ms
OPERATION IN THIS
AREA MAY BE
o
10
STARTING T = 150 C
J
LIMITED BY r
DS(ON)
10ms
V
= 30V
1
DSS(MAX)
10
0.1
1
10
100
1
1
100
t
, TIME IN AVALANCHE (ms)
AV
V
, DRAIN TO SOURCE VOLTAGE (V)
DS
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
CAPABILITY
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
©2003 Fairchild Semiconductor Corporation
HUF76113DK8 Rev. B1
HUF76113DK8
Typical Performance Curves (Continued)
30
30
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
V
= 4V
GS
V
= 15V
DD
25
20
15
10
5
25
20
15
10
5
V
= 10V
= 5V
= 4.5V
GS
V
V
GS
GS
V
= 3.5V
= 3V
GS
V
GS
o
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
150 C
o
o
25 C
o
T
= 25 C
A
-55 C
0
0
0
1
2
3
4
5
0
1
2
3
4
5
V
, GATE TO SOURCE VOLTAGE (V)
V
, DRAIN TO SOURCE VOLTAGE (V)
GS
DS
FIGURE 7. TRANSFER CHARACTERISTICS
FIGURE 8. SATURATION CHARACTERISTICS
200
150
100
50
1.6
1.4
1.2
1.0
0.8
0.6
PULSE DURATION = 80µs
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
I
= 6A
DUTY CYCLE = 0.5% MAX
D
V
= 10V, I = 6A
D
GS
I
= 1.8A
D
0
-80
-40
0
40
80
120
160
0
2
4
6
8
10
o
V
, GATE TO SOURCE VOLTAGE (V)
T , JUNCTION TEMPERATURE ( C)
GS
J
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
FIGURE 10. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
1.2
1.2
1.1
1.0
0.9
I
= 250µA
V
= V , I = 250µA
D
GS
DS
D
1.1
1.0
0.9
0.8
0.7
0.6
-80
-40
0
40
80
120
160
-80
-40
0
40
80
120
160
o
o
T , JUNCTION TEMPERATURE ( C)
T , JUNCTION TEMPERATURE ( C)
J
J
FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
©2003 Fairchild Semiconductor Corporation
HUF76113DK8 Rev. B1
HUF76113DK8
Typical Performance Curves (Continued)
10
1000
V
= 0V, f = 1MHz
GS
ISS
V
= 15V
DD
C
C
C
= C
+ C
GS
GD
= C
= C
RSS
OSS
GD
DS
8
6
4
2
0
800
600
400
200
0
+ C
GD
C
ISS
C
C
OSS
RSS
WAVEFORMS IN
DESCENDING ORDER:
I
I
= 6A
= 1.8A
D
D
0
5
10
15
20
25
30
0
5
10
Q , GATE CHARGE (nC)
15
20
V
, DRAIN TO SOURCE VOLTAGE (V)
g
DS
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 14. GATE CHARGE WAVEFORMS FOR CONSTANT
GATE CURRENT
FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
120
150
V
= 4.5V, V = 15V, I = 1.7A, R = 8.8Ω
DD D L
V
= 10V, V
= 15V, I = 6A, R = 2.5Ω
t
GS
GS
DD
D
L
r
120
90
60
30
0
90
60
30
0
t
t
d(OFF)
f
t
f
t
d(OFF)
t
r
t
d(ON)
t
d(ON)
0
10
20
30
40
50
0
10
20
30
40
50
R
, GATE TO SOURCE RESISTANCE (Ω)
R
, GATE TO SOURCE RESISTANCE (Ω)
GS
GS
FIGURE 15. SWITCHING TIME vs GATE RESISTANCE
FIGURE 16. SWITCHING TIME vs GATE RESISTANCE
Test Circuits and Waveforms
V
DS
BV
DSS
L
t
P
V
DS
I
VARY t TO OBTAIN
P
AS
+
-
V
DD
R
REQUIRED PEAK I
G
AS
V
DD
V
GS
DUT
t
P
I
AS
0V
0
0.01Ω
t
AV
FIGURE 17. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 18. UNCLAMPED ENERGY WAVEFORMS
©2003 Fairchild Semiconductor Corporation
HUF76113DK8 Rev. B1
HUF76113DK8
Test Circuits and Waveforms (Continued)
V
DS
V
Q
DD
R
g(TOT)
L
V
DS
V
= 10
GS
V
Q
GS
g(5)
+
-
V
DD
V
= 5V
V
GS
GS
DUT
V
= 1V
GS
I
0
g(REF)
Q
g(TH)
I
g(REF)
0
FIGURE 19. GATE CHARGE TEST CIRCUIT
FIGURE 20. GATE CHARGE WAVEFORMS
V
t
t
DS
ON
OFF
t
d(OFF)
t
d(ON)
t
t
f
R
L
r
V
DS
90%
90%
+
V
GS
V
DD
10%
10%
0
-
DUT
90%
50%
R
GS
V
GS
50%
PULSE WIDTH
10%
V
GS
0
FIGURE 21. SWITCHING TIME TEST CIRCUIT
FIGURE 22. SWITCHING TIME WAVEFORM
3. The use of external heat sinks.
4. The use of thermal vias.
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, T , and the ther-
JM
5. Air flow and board orientation.
mal resistance of the heat dissipating path determines the
maximum allowable device power dissipation, P , in an
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
DM
application. Therefore the application’s ambient tempera-
o
o
ture, T ( C), and thermal resistance R
( C/W) must be
A
θJA
reviewed to ensure that T is never exceeded. Equation 1
mathematically represents the relationship and serves as
the basis for establishing the rating of the part.
Fairchild provides thermal information to assist the
designer’s preliminary application evaluation. Figure 23
JM
defines the R
for the device as a function of the top
θJA
copper (component side) area. This is for a horizontally
positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse applications
can be evaluated using the Fairchild device Spice thermal
model or manually utilizing the normalized maximum
transient thermal impedance curve.
(T
– T )
JM
Z
A
(EQ. 1)
P
= ------------------------------
DM
θJA
In using surface mount devices such as the SOP-8 package,
the environment in which it is applied will have a significant
influence on the part’s current and maximum power dissipa-
tion ratings. Precise determination of P
influenced by many factors:
is complex and
DM
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
Displayed on the curve are R
θJA
Specifications table. The points were chosen to depict the
compromise between the copper board area, the thermal
values listed in the Electrical
2. The number of copper layers and the thickness of the
board.
resistance and ultimately the power dissipation, P
DM
.
©2003 Fairchild Semiconductor Corporation
HUF76113DK8 Rev. B1
HUF76113DK8
o
Thermal resistances corresponding to other copper areas can
be obtained from Figure 23 or by calculation using Equation 2.
Rθβ1 = Rθβ2 = 97 C/W
T
and T define the junction temerature of the respective
die. Similarly, P and P define the power dissipated in each
die. The steady state junction temperature can be calculated
using Equation 4 for die 1and Equation 5 for die 2.
J1
J2
R
is defined as the natural log of the area times a cofficient
θJA
1
2
added to a constant. The area, in square inches is the top
copper area including the gate and source pads.
R
= 103.2 – 24.3 × ln(Area)
(EQ. 2)
θ JA
Example: To calculate the junction temperature of each die
when die 2 is dissipating 0.5 Watts and die 1 is dissipating 0
Watts. The ambient temperature is 70°C and the package is
mounted to a top copper area of 0.1 square inches per die.
300
R
= 103.2 - 24.3 * ln(AREA)
θJA
250
o
2
Use Equation 4 to calulate T and and Equation 5 to
228 C/W - 0.006in
J1
calulate T ..
J2
o
2
200
150
100
50
191 C/W - 0.027in
T
= P R
+ P Rθ β + T
θJA 2 A
(EQ. 4)
J1
1
T
T
T
= (0 Watts)(159°C/W) + (0.5 Watts)(97°C/W) + 70°C
= 119°C
J1
J1
= P R
+ P Rθ β + T
(EQ. 5)
Rθβ = 46.4 - 21.7 * ln(AREA)
J2
2
θJA
1
A
0
o
o
o
0.001
0.01
0.1
2
1
T
T
= (0.5 Watts)(159 C/W) + (0 Watts)(97 C/W) + 70 C
J2
J2
AREA, TOP COPPER AREA (in ) PER DIE
o
= 150 C
FIGURE 23. THERMAL RESISTANCE vs MOUNTING PAD AREA
While Equation 2 describes the thermal resistance of a
single die, several of the new UltraFETs are offered with two
die in the SOP-8 package. The dual die SOP-8 package
introduces an additional thermal component, thermal
coupling resistance, Rθβ. Equation 3 describes Rθβ as a
function of the top copper mounting pad area.
The transient thermal impedance (Z
) is also effected by
θJA
varied top copper board area. Figure 24 shows the effect of
copper pad area on single pulse transient thermal
impedance. Each trace represents a copper pad area in
square inches corresponding to the descending list in the
graph. Spice and SABER thermal models are provided for
each of the listed pad areas.
Rθβ = 46.4 – 21.7 × ln(Area)
(EQ. 3)
Copper pad area has no perceivable effect on transient
thermal impedance for pulse widths less than 100ms. For
pulse widths less than 100ms the transient thermal
The thermal coupling resistance vs. copper area is also
graphically depicted in Figure 23. It is important to note the
thermal resistance (R
(Rθβ) are equivalent for both die. For example at 0.1 square
inches of copper:
) and thermal coupling resistance
impedance is determined by the die and package. Therefore,
CTHERM1 through CTHERM5 and RTHERM1 through
RTHERM5 remain constant for each of the thermal models. A
listing of the model component values is available in Table 1.
θJA
o
R
= R
= 159 C/W
θJA1
θJA2
160
COPPER BOARD AREA - DESCENDING ORDER
2
0.020 in
2
0.140 in
0.257 in
2
120
80
40
0
2
0.380 in
2
0.493 in
-1
10
0
1
2
3
10
10
t, RECTANGULAR PULSE DURATION (s)
FIGURE 24. THERMAL RESISTANCE vs MOUNTING PAD AREA
10
10
©2003 Fairchild Semiconductor Corporation
HUF76113DK8 Rev. B1
HUF76113DK8
PSPICE Electrical Model
.SUBCKT HUF76113 2 1 3 ;
REV July 1998
CA 12 8 8.50e-10
CB 15 14 8.05e-10
CIN 6 8 5.71e-10
LDRAIN
DPLCAP
10
DRAIN
2
5
RLDRAIN
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
RSLC1
51
DBREAK
+
RSLC2
5
ESLC
11
51
-
50
EBREAK 11 7 17 18 38.7
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
+
-
17
18
-
DBODY
RDRAIN
6
ESG
8
EBREAK
EVTHRES
+
16
21
+
-
EVTEMP 20 6 18 22 1
19
MWEAK
LGATE
EVTEMP
+
8
RGATE
GATE
1
6
-
18
22
MMED
IT 8 17 1
9
20
MSTRO
8
RLGATE
LDRAIN 2 5 1e-9
LGATE 1 9 9.67e-10
LSOURCE 3 7 3.27e-10
LSOURCE
CIN
SOURCE
3
7
RSOURCE
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
RLSOURCE
S1A
S2A
S2B
RBREAK
12
15
13
8
14
13
17
18
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 3.04e-3
RGATE 9 20 2.65
RLDRAIN 2 5 10
RLGATE 1 9 9.67
RLSOURCE 3 7 3.27
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 25.0e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
RVTEMP
19
S1B
13
CB
CA
IT
14
-
+
+
VBAT
6
8
5
8
EGS
EDS
+
-
-
8
22
RVTHRES
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*256),2))}
.MODEL DBODYMOD D (IS = 8.35e-13 RS = 1.39e-2 TRS1 = 1.03e-3 TRS2 = 6.85e-6 CJO = 9.11e-10 TT = 2.14e-8 M = 0.42)
.MODEL DBREAKMOD D (RS = 8.21e-2 TRS1 = 2.25e-3 TRS2 = 4.14e-5)
.MODEL DPLCAPMOD D (CJO = 3.76e-10 IS = 1e-30 N = 10 M = 0.68)
.MODEL MMEDMOD NMOS (VTO = 2.03 KP = 3.75 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 2.65)
.MODEL MSTROMOD NMOS (VTO = 2.36 KP = 50 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 1.77 KP = 0.10 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 26.5 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 1e-3 TC2 = 1e-7)
.MODEL RDRAINMOD RES (TC1 = 3.67e-2 TC2 = 4.11e-5)
.MODEL RSLCMOD RES (TC1 = 2.26e-3 TC2 = 1.23e-6)
.MODEL RSOURCEMOD RES (TC1 = 0 TC2 = 0)
.MODEL RVTHRESMOD RES (TC = -2.97e-3 TC2 = -5.91e-6)
.MODEL RVTEMPMOD RES (TC1 = -7.41e-4 TC2 = 9.41e-7)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -6.05 VOFF= -2.00)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.00 VOFF= -6.05)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.00 VOFF= 0.60)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.60 VOFF= 0.00)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
©2003 Fairchild Semiconductor Corporation
HUF76113DK8 Rev. B1
HUF76113DK8
SABER Electrical Model
REV July 1998
template huf76113 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
d..model dbodymod = (is = 8.35e-13, cjo = 9.11e-10, tt = 2.14e-8, m = 0.42)
d..model dbreakmod = ()
d..model dplcapmod = (cjo = 3.76e-10, is = 1e-30, n = 10, m = 0.68)
m..model mmedmod = (type=_n, vto = 2.03, kp = 3.75, is = 1e-30, tox = 1)
m..model mstrongmod = (type=_n, vto = 2.36, kp = 50, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 1.77, kp = 0.1, is = 1e-30, tox = 1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -6.05, voff = -2)
sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -2, voff = -6.05)
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = 0, voff = 0.6)
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.6, voff = 0)
LDRAIN
RLDRAIN
RDBODY
DPLCAP
DRAIN
2
5
10
RSLC1
51
RDBREAK
72
DBREAK
11
c.ca n12 n8 = 8.5e-10
c.cb n15 n14 = 8.05e-10
c.cin n6 n8 = 5.71e-10
RSLC2
ISCL
50
d.dbody n7 n71 = model=dbodymod
d.dbreak n72 n11 = model=dbreakmod
d.dplcap n10 n5 = model=dplcapmod
-
71
RDRAIN
6
8
ESG
EVTHRES
+
16
21
+
-
i.it n8 n17 = 1
19
8
MWEAK
LGATE
EVTEMP
DBODY
RGATE
GATE
1
6
+
-
l.ldrain n2 n5 = 1e-9
l.lgate n1 n9 = 9.67e-10
l.lsource n3 n7 = 3.27e-10
18
22
EBREAK
+
MMED
9
20
MSTRO
8
17
18
-
RLGATE
LSOURCE
CIN
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
SOURCE
3
7
RSOURCE
RLSOURCE
S1A
12
S2A
14
res.rbreak n17 n18 = 1, tc1 = 1e-3, tc2 = 1e-7
res.rdbody n71 n5 = 1.39e-2, tc1 = 1.03e-3, tc2 = 6.85e-6
res.rdbreak n72 n5 = 8.21e-2, tc1 = 2.25e-3, tc2 = 4.14e-5
res.rdrain n50 n16 = 3.04e-3, tc1 = 3.67e-2, tc2 = 4.11e-5
res.rgate n9 n20 = 2.65
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 9.67
res.rlsource n3 n7 = 3.27
res.rslc1 n5 n51 = 1e-6, tc1 = 2.26e-3, tc2 = 1.23e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 25e-3, tc1 = 0, tc2 = 0
res.rvtemp n18 n19 = 1, tc1 = -7.41e-4, tc2 = 9.41e-7
res.rvthres n22 n8 = 1, tc1 = -2.97e-3, tc2 = -5.91e-6
RBREAK
15
13
8
17
18
13
RVTEMP
19
-
S1B
S2B
13
CB
CA
IT
14
+
+
VBAT
6
8
5
8
EGS
EDS
+
-
-
8
22
RVTHRES
spe.ebreak n11 n7 n17 n18 = 38.7
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/256))** 2))
}
}
©2003 Fairchild Semiconductor Corporation
HUF76113DK8 Rev. B1
HUF76113DK8
SPICE Thermal Model
JUNCTION
th
REV June 1998
HUF76113DK8
2
Copper Area = 0.02 in
CTHERM1 th 8 8.5e-4
CTHERM2 8 7 1.8e-3
CTHERM3 7 6 5.0e-3
CTHERM4 6 5 1.3e-2
CTHERM5 5 4 4.0e-2
CTHERM6 4 3 9.0e-2
CTHERM7 3 2 4.0e-1
CTHERM8 2 tl 1.4
RTHERM1
CTHERM1
8
7
RTHERM2
RTHERM3
RTHERM4
RTHERM5
RTHERM6
RTHERM7
RTHERM8
CTHERM2
CTHERM3
CTHERM4
CTHERM5
CTHERM6
CTHERM7
CTHERM8
RTHERM1 th 8 3.5e-2
RTHERM2 8 7 6.0e-1
RTHERM3 7 6 2
RTHERM4 6 5 8
6
5
RTHERM5 5 4 18
RTHERM6 4 3 39
RTHERM7 3 2 42
RTHERM8 2 tl 48
SABER Thermal Model
2
Copper Area = 0.02 in
4
3
2
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 8 = 8.5e-4
ctherm.ctherm2 8 7 = 1.8e-3
ctherm.ctherm3 7 6 = 5.0e-3
ctherm.ctherm4 6 5 = 1.3e-2
ctherm.ctherm5 5 4 = 4.0e-2
ctherm.ctherm6 4 3 = 9.0e-2
ctherm.ctherm7 3 2 = 4.0e-1
ctherm.ctherm8 2 tl = 1.4
rtherm.rtherm1 th 8 = 3.0e-2
rtherm.rtherm2 8 7 = 6.0e-1
rtherm.rtherm3 7 6 = 3.8
rtherm.rtherm4 6 5 = 9.5
rtherm.rtherm5 5 4 = 25
rtherm.rtherm6 4 3 = 38
rtherm.rtherm7 3 2 = 25
rtherm.rtherm8 2 tl = 38
}
tl
CASE
TABLE 1. Thermal Models
2
2
2
2
2
COMPONANT
CTHERM6
CTHERM7
CTHERM8
RTHERM6
RTHERM7
RTHERM8
0.02 in
0.14 in
1.3e-1
6.0e-1
2.5
0.25 in
1.5e-1
0.38 in
0.50 in
9.0e-2
4.0e-1
1.4
1.5e-1
6.5e-1
3
1.5e-1
7.5e-1
3
4.5e-1
2.2
20
39
26
20
20
42
32
31
29
23
48
35
38
31
25
©2003 Fairchild Semiconductor Corporation
HUF76113DK8 Rev. B1
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Advance Information
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Rev. I2
相关型号：
HUF76121D3ST_NL
Power Field-Effect Transistor, 20A I(D), 30V, 0.033ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-252AA, TO-252AA, 3 PIN
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