HUF76407DK8 [FAIRCHILD]
3.5A, 60V, 0.105 Ohm, Dual N-Channel, Logic Level UltraFET Power MOSFET; 3.5A ， 60V ， 0.105欧姆，双N沟道逻辑电平UltraFET功率MOSFET
| 型号： | HUF76407DK8 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | 3.5A, 60V, 0.105 Ohm, Dual N-Channel, Logic Level UltraFET Power MOSFET |
| 文件： | 总12页 (文件大小：262K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HUF76407DK8
Data Sheet
December 2001
3.5A, 60V, 0.105 Ohm, Dual N-Channel,
Logic Level UltraFET® Power MOSFET
Packaging
Features
JEDEC MS-012AA
• Ultra Low On-Resistance
BRANDING DASH
- r
- r
= 0.090Ω, VGS = 10V
= 0.105Ω, VGS = 5V
DS(ON)
DS(ON)
• Simulation Models
5
- Temperature Compensated PSPICE® and SABER™
Electrical Models
- SPICE and SABER Thermal Impedance Models
- www.fairchildsemi.com
1
2
3
4
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
Symbol
• Transient Thermal Impedance Curve vs Board Mounting
Area
SOURCE1 (1)
GATE1 (2)
DRAIN 1 (8)
DRAIN 1 (7)
• Switching Time vs R
Curves
GS
Ordering Information
SOURCE2 (3)
GATE2 (4)
DRAIN 2 (6)
DRAIN 2 (5)
PART NUMBER
PACKAGE
MS-012AA
BRAND
76407DK8
HUF76407DK8
NOTE: When ordering, use the entire part number. Add the suffix T
to obtain the variant in tape and reel, e.g., HUF76407DK8T.
o
Absolute Maximum Ratings T = 25 C, Unless Otherwise Specified
A
HUF76407DK8
UNITS
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
60
60
V
V
V
DSS
DGR
Drain to Gate Voltage (R
= 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
±16
GS
Drain Current
o
Continuous (T = 25 C, V
A
= 5V) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
= 10V) (Figure 2) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
3.5
3.8
1.0
A
A
A
A
GS
GS
D
D
o
Continuous (T = 25 C, V
A
o
Continuous (T = 100 C, V
= 5V) (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
= 4.5V) (Figure 2) (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
A
GS
D
o
Continuous (T = 100 C, V
1.0
A
GS
D
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
Figure 4
DM
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UIS
Power Dissipation (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
Derate Above 25 C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figures 6, 17, 18
2.5
20
W
D
o
o
mW/ C
o
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T , T
J
-55 to 150
C
STG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
Package Body for 10s, See Techbrief TB334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
o
300
260
C
C
L
o
pkg
NOTES:
o
o
1. T = 25 C to 125 C.
J
o
2
2
2. 50 C/W measured using FR-4 board with 0.76 in (490.3 mm ) copper pad at 1 second.
o
2
2
3. 228 C/W measured using FR-4 board with 0.006 in (3.87 mm ) copper pad at 1000 seconds.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Product reliability information can be found at http://www.fairchildsemi.com/products/discrete/reliability/index.html
For severe environments, see our Automotive HUFA series.
All Fairchild semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification.
©2001 Fairchild Semiconductor Corporation
HUF76407DK8 Rev. B
HUF76407DK8
o
Electrical Specifications
PARAMETER
T = 25 C, Unless Otherwise Specified
A
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage
BV
I
I
= 250µA, V
= 250µA, V
= 0V (Figure 12)
o
60
55
-
-
-
-
-
-
-
-
V
DSS
D
D
GS
GS
GS
GS
= 0V , T = -40 C (Figure 12)
A
V
Zero Gate Voltage Drain Current
I
V
V
V
= 55V, V
= 50V, V
= ±16V
= 0V
= 0V, T = 150 C
1
µA
µA
nA
DSS
DS
DS
GS
o
-
250
±100
A
Gate to Source Leakage Current
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage
Drain to Source On Resistance
I
-
GSS
V
V
= V , I = 250µA (Figure 11)
1
-
-
3
V
Ω
Ω
Ω
GS(TH)
GS
DS
D
r
I
I
I
= 3.8A, V
= 1.0A, V
= 1.0A, V
= 10V (Figures 9, 10)
= 5V (Figure 9)
0.075
0.088
0.092
0.090
0.105
0.110
DS(ON)
D
D
D
GS
GS
GS
-
= 4.5V (Figure 9)
-
THERMAL SPECIFICATIONS
2
2
o
Thermal Resistance Junction to
Ambient
R
Pad Area = 0.76 in (490.3 mm ) (Note 2)
-
-
-
-
-
-
50
C/W
θJA
2
2
o
Pad Area = 0.027 in (17.4 mm ) (Figure 23)
191
228
C/W
2
2
o
Pad Area = 0.006 in (3.87 mm ) (Figure 23)
C/W
SWITCHING SPECIFICATIONS (V
Turn-On Time
= 4.5V)
GS
t
V
V
= 30V, I = 1.0A
-
-
-
-
-
-
-
57
-
ns
ns
ns
ns
ns
ns
ON
DD
GS
D
= 4.5V, R
= 27Ω
GS
Turn-On Delay Time
Rise Time
t
8
d(ON)
(Figures 15, 21, 22)
t
30
25
25
-
-
r
Turn-Off Delay Time
Fall Time
t
-
d(OFF)
t
-
f
Turn-Off Time
t
75
OFF
SWITCHING SPECIFICATIONS (V
Turn-On Time
= 10V)
t
GS
V
V
R
= 30V, I = 3.8A
D
= 10V,
= 30Ω
-
-
-
-
-
-
-
24
ns
ns
ns
ns
ns
ns
ON
DD
GS
Turn-On Delay Time
Rise Time
t
5
-
d(ON)
GS
t
11
46
31
-
-
r
(Figures 16, 21, 22)
Turn-Off Delay Time
Fall Time
t
-
-
d(OFF)
t
f
Turn-Off Time
t
116
OFF
GATE CHARGE SPECIFICATIONS
Total Gate Charge
Q
V
V
V
= 0V to 10V
= 0V to 5V
= 0V to 1V
V
= 30V,
-
-
-
-
-
9.4
5.3
11.2
6.4
0.5
-
nC
nC
nC
nC
nC
g(TOT)
GS
GS
GS
DD
= 1.0A,
I
I
D
Gate Charge at 5V
Q
g(5)
= 1.0mA
g(REF)
Threshold Gate Charge
Q
0.42
1.05
2.4
g(TH)
(Figures 14, 19, 20)
Gate to Source Gate Charge
Gate to Drain “Miller” Charge
CAPACITANCE SPECIFICATIONS
Input Capacitance
Q
gs
gd
Q
-
C
V
= 25V, V
GS
= 0V,
-
-
-
330
100
18
-
-
-
pF
pF
pF
ISS
DS
f = 1MHz
(Figure 13)
Output Capacitance
C
C
OSS
RSS
Reverse Transfer Capacitance
Source to Drain Diode Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
1.25
1.00
48
UNITS
Source to Drain Diode Voltage
V
I
I
I
I
= 3.8A
= 1.0A
-
-
-
-
-
-
-
-
V
V
SD
SD
SD
SD
SD
Reverse Recovery Time
t
= 1.0A, dI /dt = 100A/µs
SD
ns
nC
rr
Reverse Recovered Charge
Q
= 1.0A, dI /dt = 100A/µs
SD
89
RR
©2001 Fairchild Semiconductor Corporation
HUF76407DK8 Rev. B
HUF76407DK8
Typical Performance Curves
1.2
1.0
0.8
0.6
0.4
0.2
0
4
3
2
1
o
V
= 10V, R
= 50 C/W
GS
θJA
o
V
= 4.5V, R
50
= 228 C/W
GS
θJA
0
0
25
50
75
100
125
150
25
75
100
125
150
o
o
T , AMBIENT TEMPERATURE ( C)
T , AMBIENT TEMPERATURE ( C)
A
A
FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
AMBIENT TEMPERATURE
2
DUTY CYCLE - DESCENDING ORDER
1
0.5
0.2
o
R
= 228 C/W
0.1
θJA
0.05
0.02
0.01
0.1
P
DM
t
1
0.01
t
2
NOTES:
DUTY FACTOR: D = t /t
1
2
PEAK T = P
x Z
x R + T
SINGLE PULSE
-3
J
DM
θJA
θJA A
0.001
-5
-4
-2
-1
10
0
1
2
3
10
10
10
10
10
10
10
10
t, RECTANGULAR PULSE DURATION (s)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
200
o
o
= 25 C
R
= 228 C/W
θJA
T
C
100
FOR TEMPERATURES
o
ABOVE 25 C DERATE PEAK
CURRENT AS FOLLOWS:
150 - T
A
I = I
25
V
= 5V
125
GS
10
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
1
10
-5
-4
10
-3
-2
10
-1
0
1
2
3
10
10
t, PULSE WIDTH (s)
10
10
10
10
FIGURE 4. PEAK CURRENT CAPABILITY
©2001 Fairchild Semiconductor Corporation
HUF76407DK8 Rev. B
HUF76407DK8
Typical Performance Curves (Continued)
50
500
SINGLE PULSE
= MAX RATED
o
If R = 0
= (L)(I )/(1.3*RATED BV
R
= 228 C/W
θJA
T
J
t
- V
)
DD
AV
If R
AS
DSS
o
T
= 25 C
A
≠
0
100
t
= (L/R)ln[(I *R)/(1.3*RATED BV
AS DSS
- V ) +1]
DD
AV
10
100µs
10
1
o
STARTING T = 25 C
J
OPERATION IN THIS
AREA MAY BE
1ms
o
LIMITED BY r
DS(ON)
STARTING T = 150 C
J
10ms
1
0.1
0.01
0.1
1
10
1
10
, DRAIN TO SOURCE VOLTAGE (V)
100
200
t
, TIME IN AVALANCHE (ms)
AV
V
DS
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
CAPABILITY
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
20
20
PULSE DURATION = 80
DUTY CYCLE = 0.5% MAX
= 15V
µs
V
V
= 10V
= 5V
GS
V
= 4.5V
V
GS
GS
DD
o
T
= 25 C
J
15
10
5
15
10
o
T
= -55 C
J
V
= 4V
GS
o
T
= 150 C
J
V
= 3.5V
GS
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
5
0
o
T
= 25 C
V
= 3V
A
GS
0
0
1
2
3
4
2.0
2.5
3.0
3.5
4.5
5.0
4.0
V
, GATE TO SOURCE VOLTAGE (V)
V
, DRAIN TO SOURCE VOLTAGE (V)
GS
DS
FIGURE 7. TRANSFER CHARACTERISTICS
FIGURE 8. SATURATION CHARACTERISTICS
150
120
2.0
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
V
= 10V, I = 3.8A
D
PULSE DURATION = 80
DUTY CYCLE = 0.5% MAX
µs
GS
I
= 3.8A
D
1.5
1.0
0.5
I
= 1A
D
90
60
2
3
4
5
6
7
8
9
10
-80
-40
0
40
80
120
o
160
V
, GATE TO SOURCE VOLTAGE (V)
T , JUNCTION TEMPERATURE ( C)
J
GS
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
FIGURE 10. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
©2001 Fairchild Semiconductor Corporation
HUF76407DK8 Rev. B
HUF76407DK8
Typical Performance Curves (Continued)
1.2
1.2
1.1
V
= V , I = 250
µA
I
= 250µA
GS
DS
D
D
1.0
0.8
0.6
1.0
0.9
-80
-40
0
40
80
120
160
-80
-40
0
40
80
120
160
o
o
T , JUNCTION TEMPERATURE ( C)
T , JUNCTION TEMPERATURE ( C)
J
J
FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
10
V
= 30V
1000
DD
C
=
C
+ C
GS GD
ISS
8
6
4
2
0
100
C
C
+ C
DS GD
OSS
WAVEFORMS IN
DESCENDING ORDER:
I
I
= 3.8A
= 1.0A
D
D
C
= C
GD
RSS
10
5
V
= 0V, f = 1MHz
GS
0
2
4
6
8
10
0.1
1.0
10
60
Q , GATE CHARGE (nC)
g
V
, DRAIN TO SOURCE VOLTAGE (V)
DS
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 14. GATE CHARGE WAVEFORMS FOR CONSTANT
GATE CURRENT
FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
50
80
V
= 10V, V = 30V, I = 3.8A
DD D
t
V
= 4.5V, V
DD
= 30V, I = 1.0A
D
GS
d(OFF)
GS
t
r
40
30
20
60
40
20
0
t
f
t
t
f
d(OFF)
t
d(ON)
t
r
10
0
t
d(ON)
0
10
20
30
40
50
0
10
20
30
40
50
R
, GATE TO SOURCE RESISTANCE (
Ω)
R
, GATE TO SOURCE RESISTANCE (Ω)
GS
GS
FIGURE 15. SWITCHING TIME vs GATE RESISTANCE
FIGURE 16. SWITCHING TIME vs GATE RESISTANCE
©2001 Fairchild Semiconductor Corporation
HUF76407DK8 Rev. B
HUF76407DK8
Test Circuits and Waveforms
V
DS
BV
DSS
L
t
P
V
DS
I
VARY t TO OBTAIN
P
AS
+
V
DD
R
REQUIRED PEAK I
AS
G
V
DD
-
V
GS
DUT
t
P
I
0V
AS
0
0.01Ω
t
AV
FIGURE 17. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 18. UNCLAMPED ENERGY WAVEFORMS
V
DS
V
Q
DD
R
g(TOT)
L
V
DS
V
= 10V
GS
V
Q
GS
g(5)
+
-
V
DD
V
= 5V
V
GS
GS
DUT
V
= 1V
GS
I
0
g(REF)
Q
g(TH)
Q
Q
gd
gs
I
g(REF)
0
FIGURE 19. GATE CHARGE TEST CIRCUIT
FIGURE 20. GATE CHARGE WAVEFORMS
V
t
t
DS
ON
OFF
t
d(OFF)
t
d(ON)
t
t
f
R
L
r
V
DS
90%
90%
+
V
GS
V
DD
10%
10%
0
-
DUT
90%
50%
R
GS
V
GS
50%
PULSE WIDTH
10%
V
GS
0
FIGURE 21. SWITCHING TIME TEST CIRCUIT
FIGURE 22. SWITCHING TIME WAVEFORM
©2001 Fairchild Semiconductor Corporation
HUF76407DK8 Rev. B
HUF76407DK8
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, T , and the
thermal resistance of the heat dissipating path determines
JM
300
250
200
150
100
50
R
= 103.2 - 24.3 * ln(AREA)
θJA
the maximum allowable device power dissipation, P , in an
DM
o
2
228 C/W - 0.006in
application. Therefore the application’s ambient
o
o
o
2
temperature, T ( C), and thermal resistance R
( C/W)
191 C/W - 0.027in
A
θJA
is never exceeded.
must be reviewed to ensure that T
JM
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.
(T
– T )
JM
R
A
(EQ. 1)
P
= ------------------------------
DM
θJA
Rθβ = 46.4 - 21.7 * ln(AREA)
0
In using surface mount devices such as the SOP-8 package,
the environment in which it is applied will have a significant
influence on the part’s current and maximum power
0.001
0.01
0.1
2
1
AREA, TOP COPPER AREA (in ) PER DIE
FIGURE 23. THERMAL RESISTANCE vs MOUNTING PAD AREA
dissipation ratings. Precise determination of P
and influenced by many factors:
is complex
DM
While Equation 2 describes the thermal resistance of a
single die, several of the new UltraFETs are offered with two
die in the SOP-8 package. The dual die SOP-8 package
introduces an additional thermal component, thermal
coupling resistance, Rθβ. Equation 3 describes Rθβ as a
function of the top copper mounting pad area.
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
2. The number of copper layers and the thickness of the
board.
Rθβ = 46.4 – 21.7 × ln(Area)
(EQ. 3)
3. The use of external heat sinks.
4. The use of thermal vias.
The thermal coupling resistance vs. copper area is also
graphically depicted in Figure 23. It is important to note the
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
thermal resistance (R
) and thermal coupling resistance
θJA
(Rθβ) are equivalent for both die. For example at 0.1 square
inches of copper:
Fairchild provides thermal information to assist the
designer’s preliminary application evaluation. Figure 23
o
R
= R
= 159 C/W
o
θJA1
θJA2
defines the R
for the device as a function of the top
θJA
Rθβ1 = Rθβ2 = 97 C/W
copper (component side) area. This is for a horizontally
positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse applications
can be evaluated using the Fairchild device Spice thermal
model or manually utilizing the normalized maximum
transient thermal impedance curve.
T
and T define the junction temerature of the respective
J2
J1
die. Similarly, P and P define the power dissipated in each
1
2
die. The steady state junction temperature can be calculated
using Equation 4 for die 1and Equation 5 for die 2.
Example: To calculate the junction temperature of each die
when die 2 is dissipating 0.5 Watts and die 1 is dissipating 0
Watts. The ambient temperature is 70 C and the package is
o
mounted to a top copper area of 0.1 square inches per die.
Displayed on the curve are R
θJA
values listed in the
Use Equation 4 to calulate T and and Equation 5 to
J1
Electrical Specifications table. The points were chosen to
depict the compromise between the copper board area, the
thermal resistance and ultimately the power dissipation,
calulate T
.
J2
.
P
.
T
T
T
= P R
+ P Rθβ + T
(EQ. 4)
o
DM
J1
J1
J1
1
θJA
2
A
o
o
= (0 Watts)(159 C/W) + (0.5 Watts)(97 C/W) + 70 C
Thermal resistances corresponding to other copper areas
can be obtained from Figure 23 or by calculation using
Equation 2. R
o
= 119 C
is defined as the natural log of the area
θJA
times a cofficient added to a constant. The area, in square
inches is the top copper area including the gate and source
pads.
T
T
T
= P R
+ P Rθβ + T
(EQ. 5)
J2
J2
2
θJA
1
A
o
o
= (0.5 Watts)(159 C/W) + (0 Watts)(97 C/W) + 70°C
R
= 103.2 – 24.3 × ln(Area)
(EQ. 2)
o
θJA
= 150 C
J2
©2001 Fairchild Semiconductor Corporation
HUF76407DK8 Rev. B
HUF76407DK8
The transient thermal impedance (Z
θJA
) is also effected by
Copper pad area has no perceivable effect on transient
thermal impedance for pulse widths less than 100ms. For
pulse widths less than 100ms the transient thermal
impedance is determined by the die and package. Therefore,
CTHERM1 through CTHERM5 and RTHERM1 through
RTHERM5 remain constant for each of the thermal models. A
listing of the model component values is available in Table 1.
varied top copper board area. Figure 24 shows the effect of
copper pad area on single pulse transient thermal
impedance. Each trace represents a copper pad area in
square inches corresponding to the descending list in the
graph. Spice and SABER thermal models are provided for
each of the listed pad areas.
160
COPPER BOARD AREA - DESCENDING ORDER
2
0.020 in
2
0.140 in
2
0.257 in
120
2
0.380 in
2
0.493 in
80
40
0
-1
10
0
1
2
3
10
10
t, RECTANGULAR PULSE DURATION (s)
FIGURE 24. THERMAL RESISTANCE vs MOUNTING PAD AREA
10
10
©2001 Fairchild Semiconductor Corporation
HUF76407DK8 Rev. B
HUF76407DK8
PSPICE Electrical Model
.SUBCKT HUF76407DK8 2 1 3 ;
REV 28 May 1999
CA 12 8 4.55e-10
CB 15 14 5.20e-10
CIN 6 8 3.11e-10
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
LDRAIN
DPLCAP
10
DRAIN
2
5
RLDRAIN
RSLC1
51
EBREAK 11 7 17 18 67.8
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
DBREAK
+
RSLC2
5
ESLC
11
51
-
50
+
EVTEMP 20 6 18 22 1
-
17
DBODY
RDRAIN
6
ESG
8
EBREAK 18
IT 8 17 1
-
EVTHRES
+
+
16
21
-
19
8
MWEAK
LDRAIN 2 5 1.0e-9
LGATE 1 9 1.5e-9
LSOURCE 3 7 4.86e-10
LGATE
EVTEMP
+
RGATE
GATE
1
6
-
18
22
MMED
9
20
MSTRO
8
RLGATE
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
LSOURCE
CIN
SOURCE
3
7
RSOURCE
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 3.00e-2
RGATE 9 20 3.37
RLDRAIN 2 5 10
RLGATE 1 9 15
RLSOURCE
S1A
S2A
RBREAK
12
15
13
8
14
13
17
18
RLSOURCE 3 7 4.86
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 3.80e-2
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
RVTEMP
19
-
S1B
S2B
13
CB
CA
IT
14
+
+
VBAT
6
8
5
8
EGS
EDS
+
-
-
8
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
22
RVTHRES
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*105),2))}
.MODEL DBODYMOD D (IS = 3.17e-13 RS = 2.21e-2 TRS1 = 6.25e-4 TRS2 = -1.11e-6 CJO = 6.82e-10 TT = 7.98e-8 M = 0.65)
.MODEL DBREAKMOD D (RS = 3.36e- 1TRS1 = 1.25e- 4TRS2 = 1.34e-6)
.MODEL DPLCAPMOD D (CJO = 2.91e-1 0IS = 1e-3 0M = 0.85)
.MODEL MMEDMOD NMOS (VTO = 2.00 KP = 1 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 3.37)
.MODEL MSTROMOD NMOS (VTO = 2.33 KP = 19 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 1.71 KP = 0.02 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 33.7 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 1.06e- 3TC2 = 0)
.MODEL RDRAINMOD RES (TC1 = 1.23e-2 TC2 = 2.58e-5)
.MODEL RSLCMOD RES (TC1 = 1.0e-3 TC2 = 1.0e-6)
.MODEL RSOURCEMOD RES (TC1 = 0 TC2 = 0)
.MODEL RVTHRESMOD RES (TC1 = -2.19e-3 TC2 = -4.97e-6)
.MODEL RVTEMPMOD RES (TC1 = -1.11e- 3TC2 = 0)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -7.0 VOFF= -2.5)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.5 VOFF= -7.0)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1.0 VOFF= 0)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0 VOFF= -1.0)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
©2001 Fairchild Semiconductor Corporation
HUF76407DK8 Rev. B
HUF76407DK8
SABER Electrical Model
REV 28May 1999
template huf76407dk8 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
d..model dbodymod = (is = 3.17e-13, cjo = 6.82e-10, tt = 7.98e-8, m = 0.65)
d..model dbreakmod = ()
d..model dplcapmod = (cjo = 2.91e-10, is = 1e-30, m = 0.85)
m..model mmedmod = (type=_n, vto = 2.00, kp = 1, is = 1e-30, tox = 1)
m..model mstrongmod = (type=_n, vto = 2.33, kp = 19, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 1.71, kp = 0.02, is = 1e-30, tox = 1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -7, voff = -2.5)
sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -2.5, voff = -7)
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -1.0, voff = 0)
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0, voff = -1)
LDRAIN
RLDRAIN
RDBODY
DPLCAP
DRAIN
2
5
10
RSLC1
51
RDBREAK
72
DBREAK
11
c.ca n12 n8 = 4.55e-10
c.cb n15 n14 = 5.20e-10
c.cin n6 n8 = 3.11e-10
RSLC2
ISCL
50
-
d.dbody n7 n71 = model=dbodymod
d.dbreak n72 n11 = model=dbreakmod
d.dplcap n10 n5 = model=dplcapmod
71
RDRAIN
6
8
ESG
EVTHRES
+
+
16
21
-
19
8
MWEAK
i.it n8 n17 = 1
LGATE
EVTEMP
+
DBODY
RGATE
GATE
1
6
-
18
22
EBREAK
+
l.ldrain n2 n5 = 1e-9
l.lgate n1 n9 = 1.5e-9
l.lsource n3 n7 = 4.86e-10
MMED
9
20
MSTRO
8
17
18
-
RLGATE
LSOURCE
CIN
SOURCE
3
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
7
RSOURCE
RLSOURCE
S1A
S2A
res.rbreak n17 n18 = 1, tc1 = 1.06e-3, tc2 = 0
res.rdbody n71 n5 = 2.21e-2, tc1 = -6.25e-4, tc2 = -1.11e-6
res.rdbreak n72 n5 = 3.36e-1, tc1 = 1.25e-4, tc2 = 1.34e-6
res.rdrain n50 n16 = 3.00e-2, tc1 = 1.23e-2, tc2 = 2.58e-5
res.rgate n9 n20 = 3.37
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 15
res.rlsource n3 n7 = 4.86
res.rslc1 n5 n51 = 1e-6, tc1 = 1e-3, tc2 = 1e-6
res.rslc2 n5 n50 = 1e3
RBREAK
12
15
13
14
13
17
18
8
RVTEMP
19
S1B
S2B
13
CB
CA
IT
14
-
+
+
VBAT
6
8
5
8
EGS
EDS
+
-
-
8
22
res.rsource n8 n7 = 3.80e-2, tc1 = 0, tc2 = 0
res.rvtemp n18 n19 = 1, tc1 = -1.11e-3, tc2 = 0
res.rvthres n22 n8 = 1, tc1 = -2.19e-3, tc2 = -4.97e-6
RVTHRES
spe.ebreak n11 n7 n17 n18 = 67.8
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/105))** 2))
}
}
©2001 Fairchild Semiconductor Corporation
HUF76407DK8 Rev. B
HUF76407DK8
SPICE Thermal Model
JUNCTION
th
REV 1June 1999
HUF76407DK8
2
Copper Area = 0.02 in
RTHERM1
CTHERM1
CTHERM1 th 8 8.5e-4
CTHERM2 8 7 1.8e-3
CTHERM3 7 6 5.0e-3
CTHERM4 6 5 1.3e-2
CTHERM5 5 4 4.0e-2
CTHERM6 4 3 9.0e-2
CTHERM7 3 2 4.0e-1
CTHERM8 2 tl 1.4
8
7
RTHERM2
RTHERM3
RTHERM4
RTHERM5
RTHERM6
RTHERM7
RTHERM8
CTHERM2
CTHERM3
CTHERM4
CTHERM5
CTHERM6
CTHERM7
CTHERM8
RTHERM1 th 8 3.5e-2
RTHERM2 8 7 6.0e-1
RTHERM3 7 6 2
6
5
RTHERM4 6 5 8
RTHERM5 5 4 18
RTHERM6 4 3 39
RTHERM7 3 2 42
RTHERM8 2 tl 48
SABER Thermal Model
2
Copper Area = 0.02 in
4
3
2
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 8 = 8.5e-4
ctherm.ctherm2 8 7 = 1.8e-3
ctherm.ctherm3 7 6 = 5.0e-3
ctherm.ctherm4 6 5 = 1.3e-2
ctherm.ctherm5 5 4 = 4.0e-2
ctherm.ctherm6 4 3 = 9.0e-2
ctherm.ctherm7 3 2 = 4.0e-1
ctherm.ctherm8 2 tl = 1.4
rtherm.rtherm1 th 8 = 3.5e-2
rtherm.rtherm2 8 7 = 6.0e-1
rtherm.rtherm3 7 6 = 2
rtherm.rtherm4 6 5 = 8
rtherm.rtherm5 5 4 = 18
rtherm.rtherm6 4 3 = 39
rtherm.rtherm7 3 2 = 42
rtherm.rtherm8 2 tl = 48
}
tl
AMBIENT
TABLE 1. THERMAL MODELS
2
2
2
2
2
COMPONENT
CTHERM6
0.02 in
0.14 in
1.3e-1
6.0e-1
2.5
0.257 in
0.38 in
1.5e-1
6.5e-1
3
0.493 in
1.5e-1
7.5e-1
3
9.0e-2
4.0e-1
1.4
1.5e-1
4.5e-1
2.2
CTHERM7
CTHERM8
RTHERM6
39
26
20
20
20
RTHERM7
42
32
31
29
23
RTHERM8
48
35
38
31
25
©2001 Fairchild Semiconductor Corporation
HUF76407DK8 Rev. B
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
â
SMART START™
STAR*POWER™
Stealth™
VCX™
FAST
ACEx™
Bottomless™
CoolFET™
OPTOLOGIC™
OPTOPLANAR™
PACMAN™
FASTr™
FRFET™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SyncFET™
GlobalOptoisolator™
GTO™
HiSeC™
ISOPLANAR™
LittleFET™
MicroFET™
MicroPak™
MICROWIRE™
CROSSVOLT™
DenseTrench™
DOME™
POP™
Power247™
PowerTrenchâ
QFET™
EcoSPARK™
E2CMOSTM
TinyLogic™
QS™
EnSignaTM
TruTranslation™
UHC™
QT Optoelectronics™
Quiet Series™
SILENTSWITCHERâ
FACT™
FACT Quiet Series™
UltraFETâ
STAR*POWER is used under license
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITYARISING OUT OF THE APPLICATION OR USE OFANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICESORSYSTEMSWITHOUTTHEEXPRESSWRITTENAPPROVALOFFAIRCHILDSEMICONDUCTORCORPORATION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or
In Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Obsolete
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. H4
相关型号：
©2020 ICPDF网 联系我们和版权申明