HUFA75617D3 [FAIRCHILD]
16A, 100V, 0.090 Ohm, N-Channel, UltraFET Power MOSFETs; 16A ， 100V ， 0.090 Ohm的N通道， UltraFET功率MOSFET
| 型号： | HUFA75617D3 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | 16A, 100V, 0.090 Ohm, N-Channel, UltraFET Power MOSFETs |
| 文件： | 总10页 (文件大小：198K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HUFA75617D3, HUFA75617D3S
Data Sheet
December 2001
16A, 100V, 0.090 Ohm, N-Channel,
UltraFET® Power MOSFETs
Packaging
JEDEC TO-251AA
JEDEC TO-252AA
Features
• Ultra Low On-Resistance
SOURCE
DRAIN
GATE
DRAIN
(FLANGE)
- r
= 0.090Ω, VGS = 10V
DS(ON)
• Simulation Models
- Temperature Compensated PSPICE® and SABER™
Electrical Models
GATE
SOURCE
DRAIN
- Spice and SABER Thermal Impedance Models
- www.fairchildsemi.com
(FLANGE)
HUFA75617D3S
HUFA75617D3
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
Symbol
Ordering Information
D
S
PART NUMBER
PACKAGE
TO-251AA
TO-252AA
BRAND
75617D
75617D
HUFA75617D3
G
HUFA75617D3S
NOTE: When ordering, use the entire part number. Add the suffix T
to obtain the variant in tape and reel, e.g., HUFA75617D3ST.
o
Absolute Maximum Ratings
T = 25 C, Unless Otherwise Specified
C
HUFA75617D3,
HUFA75617D3S
UNITS
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
100
100
±20
V
V
V
DSS
Drain to Gate Voltage (R
= 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
DGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
Drain Current
o
Continuous (T = 25 C, V
C
= 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
16
11
A
A
GS
D
D
o
Continuous (T = 100 C, V
= 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
C
GS
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
Figure 4
DM
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UIS
Figures 6, 14, 15
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
Derate Above 25 C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
64
0.43
W
W/ C
D
o
o
o
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T , T
J
-55 to 175
C
STG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
Package Body for 10s, See Techbrief TB334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
o
300
260
C
C
L
o
pkg
o
o
NOTE: T = 25 C to 150 C.
J
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. For a copy
of the requirements, see AEC Q101 at: http://www.aecouncil.com/
Reliability data can be found at: http://www.fairchildsemi.com/products/discrete/reliability/index.html.
All Fairchild semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification.
©2001 Fairchild Semiconductor Corporation
HUFA75617D3 Rev. B
HUFA75617D3
o
Electrical Specifications
PARAMETER
T = 25 C, Unless Otherwise Specified
C
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
BV
I
= 250µA, V
= 0V (Figure 11)
100
-
-
-
-
-
V
DSS
D
GS
GS
GS
I
V
V
V
= 95V, V
= 90V, V
= ±20V
= 0V
= 0V, T = 150 C
-
-
-
1
µA
µA
nA
DSS
DS
DS
GS
o
250
±100
C
Gate to Source Leakage Current
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage
Drain to Source On Resistance
THERMAL SPECIFICATIONS
I
GSS
V
V
= V , I = 250µA (Figure 10)
2
-
-
4
V
GS(TH)
GS
DS
D
r
I
= 16A, V
= 10V (Figure 9)
0.080
0.090
¾
DS(ON)
D
GS
o
Thermal Resistance Junction to Case
R
R
TO-251, TO-252
-
-
-
-
2.34
100
C/W
θJC
o
Thermal Resistance Junction to
Ambient
C/W
θJA
SWITCHING SPECIFICATIONS (V
Turn-On Time
= 10V)
t
GS
V
V
R
= 50V, I = 16A
D
= 10V,
= 12Ω
-
-
-
-
-
-
-
60
ns
ns
ns
ns
ns
ns
ON
DD
GS
Turn-On Delay Time
Rise Time
t
6
-
d(ON)
GS
(Figures 18, 19)
t
35
44
28
-
-
r
Turn-Off Delay Time
Fall Time
t
-
-
d(OFF)
t
f
Turn-Off Time
t
108
OFF
GATE CHARGE SPECIFICATIONS
Total Gate Charge
Q
V
V
V
= 0V to 20V
= 0V to 10V
= 0V to 2V
V
= 50V,
-
-
-
-
-
31
18
39
22
1.6
-
nC
nC
nC
nC
nC
g(TOT)
GS
GS
GS
DD
= 16A,
I
I
D
Gate Charge at 10V
Q
g(10)
g(TH)
= 1.0mA
g(REF)
(Figures 13, 16, 17)
Threshold Gate Charge
Q
1.3
2.7
6.4
Gate to Source Gate Charge
Gate to Drain "Miller" Charge
CAPACITANCE SPECIFICATIONS
Input Capacitance
Q
gs
gd
Q
-
C
V
= 25V, V
GS
= 0V,
-
-
-
570
125
20
-
-
-
pF
pF
pF
ISS
DS
f = 1MHz
(Figure 12)
Output Capacitance
C
OSS
RSS
Reverse Transfer Capacitance
C
Source to Drain Diode Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
1.25
1.00
80
UNITS
Source to Drain Diode Voltage
V
I
I
I
I
= 16A
= 7A
-
-
-
-
-
-
-
-
V
V
SD
SD
SD
SD
SD
Reverse Recovery Time
t
= 16A, dI /dt = 100A/µs
SD
ns
nC
rr
Reverse Recovered Charge
Q
= 16A, dI /dt = 100A/µs
SD
170
RR
©2001 Fairchild Semiconductor Corporation
HUFA75617D3 Rev. B
HUFA75617D3
Typical Performance Curves
1.2
1.0
0.8
0.6
0.4
0.2
0
18
15
12
9
V
= 10V
GS
6
3
0
25
50
75
100
125
150
175
0
25
50
75
100
150
175
125
o
o
T , CASE TEMPERATURE ( C)
T
, CASE TEMPERATURE ( C)
C
C
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
2
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
1
0.1
0.05
0.02
0.01
P
DM
0.1
t
1
t
2
NOTES:
DUTY FACTOR: D = t /t
1
2
PEAK T = P
x Z
x R
+ T
JC C
SINGLE PULSE
J
DM
θJC
θ
0.01
-5
-4
-3
-2
-1
0
1
10
10
10
10
t, RECTANGULAR PULSE DURATION (s)
10
10
10
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
300
o
= 25 C
T
C
200
FOR TEMPERATURES
o
ABOVE 25 C DERATE PEAK
CURRENT AS FOLLOWS:
100
175 - T
150
C
I = I
25
V
= 10V
GS
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
10
-5
-4
10
-3
-2
-1
0
1
10
10
10
t, PULSE WIDTH (s)
10
10
10
FIGURE 4. PEAK CURRENT CAPABILITY
©2001 Fairchild Semiconductor Corporation
HUFA75617D3 Rev. B
HUFA75617D3
Typical Performance Curves (Continued)
100
200
If R = 0
= (L)(I )/(1.3*RATED BV
DSS
SINGLE PULSE
100
t
- V )
DD
AV
If R ≠ 0
= (L/R)ln[(I *R)/(1.3*RATED BV - V ) +1]
DSS DD
T
= MAX RATED
AS
J
o
T
= 25 C
C
t
AV
AS
10
1
100
1ms
10ms
µ
s
o
10
STARTING T = 25 C
J
OPERATION IN THIS
AREA MAY BE
o
STARTING T = 150 C
J
LIMITED BY r
DS(ON)
1
0.001
0.1
0.01
0.1
1
10
1
10
, DRAIN TO SOURCE VOLTAGE (V)
100
200
t
, TIME IN AVALANCHE (ms)
AV
V
DS
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
CAPABILITY
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
30
25
20
30
PULSE DURATION = 80
DUTY CYCLE = 0.5% MAX
= 15V
µs
V
= 10V
GS
V
DD
25
20
V
= 6V
GS
V
= 5V
GS
15
10
15
10
o
o
T
= 175 C
T
= -55 C
J
J
PULSE DURATION = 80µs
5
0
5
0
DUTY CYCLE = 0.5% MAX
o
T
= 25 C
o
J
T
= 25 C
C
2
3
4
5
6
0
1
2
3
4
V
, GATE TO SOURCE VOLTAGE (V)
GS
V
, DRAIN TO SOURCE VOLTAGE (V)
DS
FIGURE 7. TRANSFER CHARACTERISTICS
FIGURE 8. SATURATION CHARACTERISTICS
1.2
1.0
0.8
0.6
3.0
V
= V , I = 250µA
DS
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
GS
D
2.5
2.0
1.5
1.0
0.5
V
= 10V, I = 16A
D
GS
-80
-40
0
40
80
120
160
200
-80
-40
0
40
80
120
160
200
o
T , JUNCTION TEMPERATURE ( C)
o
J
T , JUNCTION TEMPERATURE ( C)
J
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
©2001 Fairchild Semiconductor Corporation
HUFA75617D3 Rev. B
HUFA75617D3
Typical Performance Curves (Continued)
1.2
2000
V
= 0V, f = 1MHz
GS
I
= 250µA
D
1000
C
= C
+ C
GS GD
ISS
1.1
1.0
0.9
C
C
+ C
DS GD
OSS
100
C
= C
GD
RSS
10
0.1
-80
-40
0
40
80
120
160
200
1.0
10
100
o
T , JUNCTION TEMPERATURE ( C)
J
V
, DRAIN TO SOURCE VOLTAGE (V)
DS
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
10
V
= 50V
DD
8
6
4
2
0
WAVEFORMS IN
DESCENDING ORDER:
I
I
I
= 16A
= 10A
= 4A
D
D
D
0
5
10
Q , GATE CHARGE (nC)
15
20
g
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT
©2001 Fairchild Semiconductor Corporation
HUFA75617D3 Rev. B
HUFA75617D3
Test Circuits and Waveforms
V
DS
BV
DSS
L
t
P
V
DS
I
VARY t TO OBTAIN
P
AS
+
V
DD
R
REQUIRED PEAK I
G
AS
V
DD
-
V
GS
DUT
t
P
I
AS
0V
0
0.01Ω
t
AV
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
V
DS
V
Q
DD
R
g(TOT)
L
V
DS
V
= 20V
GS
V
Q
GS
g(10)
+
-
V
DD
V
= 10V
V
GS
GS
DUT
V
= 2V
GS
I
0
g(REF)
Q
g(TH)
Q
Q
gd
gs
I
g(REF)
0
FIGURE 16. GATE CHARGE TEST CIRCUIT
FIGURE 17. GATE CHARGE WAVEFORMS
V
t
t
DS
ON
OFF
t
d(OFF)
t
d(ON)
t
t
f
R
L
r
V
DS
90%
90%
+
V
GS
V
DD
10%
10%
0
-
DUT
90%
50%
R
GS
V
GS
50%
PULSE WIDTH
10%
V
GS
0
FIGURE 18. SWITCHING TIME TEST CIRCUIT
FIGURE 19. SWITCHING TIME WAVEFORM
©2001 Fairchild Semiconductor Corporation
HUFA75617D3 Rev. B
HUFA75617D3
PSPICE Electrical Model
.SUBCKT HUFA75617d3 2 1 3 ;
rev 24May 2000
CA 12 8 9.9e-10
CB 15 14 1.0e-9
CIN 6 8 5.4e-10
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
LDRAIN
DPLCAP
10
DRAIN
2
5
RLDRAIN
RSLC1
51
EBREAK 11 7 17 18 117.8
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
DBREAK
+
RSLC2
5
ESLC
11
51
-
+
50
-
17
18
-
DBODY
RDRAIN
6
ESG
8
EBREAK
IT 8 17 1
EVTHRES
+
16
21
+
-
19
8
MWEAK
LDRAIN 2 5 1.0e-9
LGATE 1 9 5.24e-9
LSOURCE 3 7 4.25e-9
LGATE
RGATE
EVTEMP
GATE
1
+
6
-
18
22
MMED
9
20
MSTRO
8
RLGATE
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
LSOURCE
CIN
SOURCE
3
7
RSOURCE
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 3.9e-2
RGATE 9 20 2.45
RLDRAIN 2 5 10
RLGATE 1 9 52.4
RLSOURCE
S1A
S2A
RBREAK
12
15
13
8
14
13
17
18
RLSOURCE 3 7 42.5
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 3.2e-2
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
RVTEMP
19
S1B
S2B
13
CB
CA
IT
14
-
+
+
VBAT
6
8
5
8
EGS
EDS
+
-
-
8
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
22
RVTHRES
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*32),3.5))}
.MODEL DBODYMOD D (IS = 6.0e-13 RS = 11.0e-3 XTI = 4.5 TRS1 = 1.1e-3 TRS2 = 7.1e-6 CJO = 6.5e-10 TT = 4.1e-8 M = 0.54)
.MODEL DBREAKMOD D (RS = 5.6e- 1TRS1 = 8.0e- 4TRS2 = 3.0e-6)
.MODEL DPLCAPMOD D (CJO = 7.0e-1 0IS = 1e-3 0M = 0.89 N = 10)
.MODEL MMEDMOD NMOS (VTO = 3.10 KP = 3 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 2.45)
.MODEL MSTROMOD NMOS (VTO = 3.64 KP = 42 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 2.68 KP = 0.02 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 24.5)
.MODEL RBREAKMOD RES (TC1 = 1.05e- 3TC2 = -5.0e-7)
.MODEL RDRAINMOD RES (TC1 = 1.20e-2 TC2 = 3.00e-5)
.MODEL RSLCMOD RES (TC1 = 3.2e-3 TC2 = 1.0e-6)
.MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6)
.MODEL RVTHRESMOD RES (TC1 = -2.2e-3 TC2 = -9.0e-6)
.MODEL RVTEMPMOD RES (TC1 = -2.4e- 3TC2 = -1.8e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -5.9 VOFF= -3.1)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3.1 VOFF= -5.9)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.6 VOFF= 0.5)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.5 VOFF= -0.6)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
©2001 Fairchild Semiconductor Corporation
HUFA75617D3 Rev. B
HUFA75617D3
SABER Electrical Model
REV 24 May 2000
template HUFA75617d3 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl = 6.0e-13, rs = 11.0e-3, xti = 4.5, trs1 = 1.1e-3, trs2 = 7.1e-6, cjo = 6.5e-10, tt = 4.1e-8, m = 0.54)
dp..model dbreakmod = (rs = 5.6e-1, trs1 = 8.0e-4, trs2 = 3.0e-6)
dp..model dplcapmod = (cjo = 7.0e-10, isl = 10e-30, m = 0.89, nl = 10)
m..model mmedmod = (type=_n, vto = 3.10, kp = 3, is = 1e-30, tox = 1)
m..model mstrongmod = (type=_n, vto = 3.64, kp = 42, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 2.68, kp = 0.02, is = 1e-30, tox = 1)
LDRAIN
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -5.9, voff = -3.1)
sw_vcsp..model s1bmod = (ron = 1e-5, roff = 0.1, von = -3.1, voff = -5.9)
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.6, voff = 0.5)
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.5, voff = -0.6)
DPLCAP
DRAIN
2
5
10
RLDRAIN
RSLC1
51
c.ca n12 n8 = 9.9e-10
c.cb n15 n14 = 1.0e-9
c.cin n6 n8 = 5.4e-10
RSLC2
ISCL
DBREAK
11
50
-
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
RDRAIN
6
8
ESG
EVTHRES
+
16
21
+
-
19
8
MWEAK
i.it n8 n17 = 1
LGATE
EVTEMP
DBODY
RGATE
GATE
1
6
+
-
18
22
EBREAK
+
l.ldrain n2 n5 = 1.0e-9
l.lgate n1 n9 = 5.24e-9
l.lsource n3 n7 = 4.25e-9
MMED
9
20
MSTRO
8
17
18
-
RLGATE
LSOURCE
CIN
SOURCE
3
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
7
RSOURCE
RLSOURCE
S1A
S2A
res.rbreak n17 n18 = 1, tc1 = 1.05e-3, tc2 = -5.0e-7
res.rdrain n50 n16 = 3.9e-2, tc1 = 1.20e-2, tc2 = 3.00e-5
res.rgate n9 n20 = 2.45
RBREAK
12
15
13
14
13
17
18
8
RVTEMP
19
S1B
S2B
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 52.4
res.rlsource n3 n7 = 42.5
res.rslc1 n5 n51 = 1e-6, tc1 = 3.2e-3, tc2 = 1.0e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 3.2e-2, tc1 = 1e-3, tc2 = 1e-6
res.rvtemp n18 n19 = 1, tc1 = -2.4e-3, tc2 = 1.8e-6
res.rvthres n22 n8 = 1, tc1 = -2.2e-3, tc2 = -9.0e-6
13
CB
CA
IT
14
-
+
+
VBAT
6
8
5
8
EGS
EDS
+
-
-
8
22
RVTHRES
spe.ebreak n11 n7 n17 n18 = 117.8
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/32))** 3.5))
}
}
©2001 Fairchild Semiconductor Corporation
HUFA75617D3 Rev. B
HUFA75617D3
SPICE Thermal Model
REV 24 May 2000
JUNCTION
th
HUFA75617D
CTHERM1 th 6 1.00e-3
CTHERM2 6 5 4.00e-3
CTHERM3 5 4 4.00e-3
CTHERM4 4 3 3.60e-3
CTHERM5 3 2 7.00e-3
CTHERM6 2 tl 5.00e-2
RTHERM1
RTHERM2
RTHERM3
RTHERM4
RTHERM5
RTHERM6
CTHERM1
6
RTHERM1 th 6 1.59e-2
RTHERM2 6 5 3.96e-2
RTHERM3 5 4 1.12e-1
RTHERM4 4 3 4.27e-1
RTHERM5 3 2 6.45e-1
RTHERM6 2 tl 7.00e-1
CTHERM2
CTHERM3
CTHERM4
CTHERM5
CTHERM6
5
SABER Thermal Model
SABER thermal model HUFA75617D
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 = 1.00e-3
ctherm.ctherm2 6 5 = 4.00e-3
ctherm.ctherm3 5 4 = 4.00e-3
ctherm.ctherm4 4 3 = 3.60e-3
ctherm.ctherm5 3 2 = 7.00e-3
ctherm.ctherm6 2 tl = 5.00e-2
4
3
2
rtherm.rtherm1 th 6 = 1.59e-2
rtherm.rtherm2 6 5 = 3.96e-2
rtherm.rtherm3 5 4 = 1.12e-1
rtherm.rtherm4 4 3 = 4.27e-1
rtherm.rtherm5 3 2 = 6.45e-1
rtherm.rtherm6 2 tl = 7.00e-1
}
tl
CASE
©2001 Fairchild Semiconductor Corporation
HUFA75617D3 Rev. B
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Rev. H4
相关型号：
HUFA75623S3S
Power Field-Effect Transistor, 22A I(D), 100V, 0.064ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-263AB
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