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HUFA76645S3ST-NL [FAIRCHILD]

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HUFA76645S3ST-NL
型号： HUFA76645S3ST-NL
厂家： FAIRCHILD SEMICONDUCTOR    FAIRCHILD SEMICONDUCTOR
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晶体 晶体管 开关
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HUFA76645P3, HUFA76645S3S  
Data Sheet  
January 2002  
75A, 100V, 0.015 Ohm, N-Channel, Logic  
Level UltraFET® Power MOSFET  
Packaging  
Features  
JEDEC TO-220AB  
JEDEC TO-263AB  
• Ultra Low On-Resistance  
SOURCE  
DRAIN  
(FLANGE)  
- r  
- r  
= 0.014Ω, VGS = 10V  
= 0.015Ω, VGS = 5V  
DS(ON)  
DS(ON)  
DRAIN  
GATE  
• Simulation Models  
GATE  
- Temperature Compensated PSPICE® and SABER™  
Electrical Models  
SOURCE  
- Spice and SABER Thermal Impedance Models  
- www.fairchildsemi.com  
DRAIN  
(FLANGE)  
HUFA76645P3  
HUFA76645S3S  
• Peak Current vs Pulse Width Curve  
• UIS Rating Curve  
• Switching Time vs R  
Curves  
Symbol  
GS  
D
S
Ordering Information  
PART NUMBER  
HUFA76645P3  
PACKAGE  
BRAND  
76645P  
76645S  
G
TO-220AB  
TO-263AB  
HUFA76645S3S  
NOTE: When ordering, use the entire part number. Add the suffix T  
to obtain the variant in tape and reel, e.g., HUFA76645S3ST.  
o
Absolute Maximum Ratings  
T
= 25 C, Unless Otherwise Specified  
C
HUFA76645P3,  
HUFA76645S3S  
UNITS  
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V  
100  
100  
±16  
V
V
V
DSS  
Drain to Gate Voltage (R  
= 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V  
GS  
DGR  
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V  
GS  
Drain Current  
o
Continuous (T = 25 C, V  
= 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I  
= 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I  
75  
75  
63  
A
A
A
A
C
GS  
GS  
D
D
o
Continuous (T = 25 C, V  
C
o
Continuous (T = 100 C, V  
= 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I  
= 4.5V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I  
C
GS  
GS  
D
o
Continuous (T = 100 C, V  
62  
C
D
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I  
Figure 4  
DM  
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UIS  
Figures 6, 17, 18  
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P  
Derate Above 25 C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
310  
2.07  
W
W/ C  
D
o
o
o
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T , T  
J
-55 to 175  
C
STG  
Maximum Temperature for Soldering  
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T  
Package Body for 10s, See Techbrief TB334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T  
o
300  
260  
C
C
L
o
pkg  
NOTES:  
1. T = 25 C to 150 C.  
o
o
J
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the  
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.  
This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. For a copy  
of the requirements, see AEC Q101 at: http://www.aecouncil.com/  
Reliability data can be found at: http://www.fairchildsemi.com/products/discrete/reliability/index.html.  
All Fairchild semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification.  
©2002 Fairchild Semiconductor Corporation  
HUFA76645P3, HUFA76645S3S Rev. B  
HUFA76645P3, HUFA76645S3S  
o
Electrical Specifications  
T = 25 C, Unless Otherwise Specified  
C
PARAMETER  
SYMBOL  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
OFF STATE SPECIFICATIONS  
Drain to Source Breakdown Voltage  
BV  
I
I
= 250µA, V  
= 250µA, V  
= 0V (Figure 12)  
o
100  
-
-
-
-
-
-
-
V
DSS  
D
D
GS  
GS  
GS  
GS  
= 0V , T = -40 C (Figure 12)  
C
90  
-
V
Zero Gate Voltage Drain Current  
I
V
V
V
= 95V, V  
= 90V, V  
= ±16V  
= 0V  
= 0V, T = 150 C  
1
µA  
µA  
nA  
DSS  
DS  
DS  
GS  
o
-
250  
±100  
C
Gate to Source Leakage Current  
ON STATE SPECIFICATIONS  
Gate to Source Threshold Voltage  
Drain to Source On Resistance  
I
-
GSS  
V
V
= V , I = 250µA (Figure 11)  
1
-
-
3
V
Ω
Ω
Ω
GS(TH)  
GS  
DS  
D
GS  
GS  
GS  
r
I
I
I
= 75A, V  
= 63A, V  
= 62A, V  
= 10V (Figures 9, 10)  
= 5V (Figure 9)  
0.012  
0.013  
0.014  
0.015  
DS(ON)  
D
D
D
-
= 4.5V (Figure 9)  
-
0.0135 0.0155  
THERMAL SPECIFICATIONS  
o
Thermal Resistance Junction to Case  
R
R
TO-220 and TO-263  
-
-
-
-
0.48  
62  
C/W  
θJC  
o
Thermal Resistance Junction to  
Ambient  
C/W  
θJA  
SWITCHING SPECIFICATIONS (V  
Turn-On Time  
= 4.5V)  
GS  
t
V
V
= 50V, I = 62A  
-
-
-
-
-
-
-
490  
ns  
ns  
ns  
ns  
ns  
ns  
ON  
DD  
GS  
D
= 4.5V, R  
= 2.4Ω  
GS  
Turn-On Delay Time  
Rise Time  
t
17  
310  
46  
155  
-
-
d(ON)  
(Figures 15, 21, 22)  
t
-
r
Turn-Off Delay Time  
Fall Time  
t
-
-
d(OFF)  
t
f
Turn-Off Time  
t
300  
OFF  
SWITCHING SPECIFICATIONS (V  
Turn-On Time  
= 10V)  
t
GS  
V
V
R
= 50V, I = 75A  
D
= 10V,  
= 2.4Ω  
-
-
-
-
-
-
-
175  
ns  
ns  
ns  
ns  
ns  
ns  
ON  
DD  
GS  
Turn-On Delay Time  
Rise Time  
t
11  
106  
69  
175  
-
-
d(ON)  
GS  
t
-
r
(Figures 16, 21, 22)  
Turn-Off Delay Time  
Fall Time  
t
-
-
d(OFF)  
t
f
Turn-Off Time  
t
365  
OFF  
GATE CHARGE SPECIFICATIONS  
Total Gate Charge  
Q
V
V
V
= 0V to 10V  
= 0V to 5V  
= 0V to 1V  
V
= 50V,  
-
-
-
-
-
127  
70  
153  
84  
4.6  
-
nC  
nC  
nC  
nC  
nC  
g(TOT)  
GS  
GS  
GS  
DD  
= 63A,  
I
I
D
Gate Charge at 5V  
Q
g(5)  
= 1.0mA  
g(REF)  
Threshold Gate Charge  
Q
3.8  
10  
g(TH)  
(Figures 14, 19, 20)  
Gate to Source Gate Charge  
Gate to Drain “Miller” Charge  
CAPACITANCE SPECIFICATIONS  
Input Capacitance  
Q
gs  
gd  
Q
34  
-
C
V
= 25V, V  
GS  
= 0V,  
-
-
-
4400  
900  
-
-
-
pF  
pF  
pF  
ISS  
DS  
f = 1MHz  
(Figure 13)  
Output Capacitance  
C
C
OSS  
Reverse Transfer Capacitance  
280  
RSS  
Source to Drain Diode Specifications  
PARAMETER  
SYMBOL  
TEST CONDITIONS  
MIN  
TYP  
MAX  
1.25  
1.0  
UNITS  
Source to Drain Diode Voltage  
V
I
I
I
I
= 63A  
= 30A  
-
-
-
-
-
-
-
-
V
V
SD  
SD  
SD  
SD  
SD  
Reverse Recovery Time  
t
= 63A, dI /dt = 100A/µs  
SD  
128  
520  
ns  
nC  
rr  
Reverse Recovered Charge  
Q
= 63A, dI /dt = 100A/µs  
SD  
RR  
©2002 Fairchild Semiconductor Corporation  
HUFA76645P3, HUFA76645S3S Rev. B  
HUFA76645P3, HUFA76645S3S  
Typical Performance Curves  
1.2  
1.0  
0.8  
0.6  
0.4  
0.2  
0
80  
60  
40  
20  
0
V
= 10V  
GS  
V
= 4.5V  
GS  
0
25  
50  
75  
100  
150  
175  
25  
50  
75  
100  
125  
150  
175  
125  
o
o
T
, CASE TEMPERATURE ( C)  
T , CASE TEMPERATURE ( C)  
C
C
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE  
TEMPERATURE  
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs  
CASE TEMPERATURE  
2
DUTY CYCLE - DESCENDING ORDER  
0.5  
1
0.2  
0.1  
0.05  
0.02  
0.01  
P
DM  
0.1  
t
1
t
2
NOTES:  
DUTY FACTOR: D = t /t  
1
2
SINGLE PULSE  
PEAK T = P  
x Z  
x R + T  
J
DM  
θJC  
θJC C  
0.01  
-5  
-4  
10  
-3  
-2  
10  
-1  
0
1
10  
10  
10  
10  
10  
t, RECTANGULAR PULSE DURATION (s)  
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE  
2000  
1000  
o
= 25 C  
T
C
FOR TEMPERATURES  
ABOVE 25 C DERATE PEAK  
o
CURRENT AS FOLLOWS:  
175 - T  
150  
C
I = I  
25  
V
= 10V  
GS  
V
= 5V  
GS  
100  
50  
TRANSCONDUCTANCE  
MAY LIMIT CURRENT  
IN THIS REGION  
-5  
10  
-4  
10  
-3  
10  
-2  
10  
-1  
10  
0
1
10  
10  
t, PULSE WIDTH (s)  
FIGURE 4. PEAK CURRENT CAPABILITY  
©2002 Fairchild Semiconductor Corporation  
HUFA76645P3, HUFA76645S3S Rev. B  
HUFA76645P3, HUFA76645S3S  
Typical Performance Curves (Continued)  
500  
500  
If R = 0  
= (L)(I )/(1.3*RATED BV  
t
- V )  
DD  
AV  
If R ≠ 0  
= (L/R)ln[(I *R)/(1.3*RATED BV - V ) +1]  
DSS DD  
AS  
DSS  
t
AV  
AS  
100  
100µs  
100  
o
STARTING T = 25 C  
J
OPERATION IN THIS  
AREA MAY BE  
10  
1
1ms  
o
LIMITED BY r  
DS(ON)  
STARTING T = 150 C  
J
10ms  
SINGLE PULSE  
T
= MAX RATED  
J
o
T
= 25 C  
C
1
0.001  
0.01  
t
0.1  
1
10  
1
10  
100  
300  
, TIME IN AVALANCHE (ms)  
V
, DRAIN TO SOURCE VOLTAGE (V)  
AV  
DS  
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.  
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING  
CAPABILITY  
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA  
150  
150  
PULSE DURATION = 80µs  
DUTY CYCLE = 0.5% MAX  
DD  
V
= 10V  
= 5V  
GS  
V
= 3.5V  
GS  
V
GS  
125  
100  
75  
50  
25  
0
V
= 15V  
125  
100  
75  
50  
25  
0
V
= 4V  
GS  
V
= 3V  
GS  
o
T
= 175 C  
J
PULSE DURATION = 80µs  
o
DUTY CYCLE = 0.5% MAX  
T
= 25 C  
J
o
o
T
= -55 C  
T
= 25 C  
J
C
1.5  
2.0  
2.5  
3.0  
3.5  
4.0  
0
1
2
3
4
V
, GATE TO SOURCE VOLTAGE (V)  
V
, DRAIN TO SOURCE VOLTAGE (V)  
DS  
GS  
FIGURE 7. TRANSFER CHARACTERISTICS  
FIGURE 8. SATURATION CHARACTERISTICS  
25  
3.0  
PULSE DURATION = 80µs  
DUTY CYCLE = 0.5% MAX  
V
= 10V, I = 75A  
D
PULSE DURATION = 80µs  
GS  
I
= 75A  
D
DUTY CYCLE = 0.5% MAX  
o
T
= 25 C  
2.5  
C
20  
15  
10  
2.0  
1.5  
1.0  
0.5  
I
= 50A  
D
I
= 20A  
D
-80  
-40  
0
40  
80  
120  
160  
200  
2
4
6
8
10  
o
V
, GATE TO SOURCE VOLTAGE (V)  
T , JUNCTION TEMPERATURE ( C)  
GS  
J
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE  
VOLTAGE AND DRAIN CURRENT  
FIGURE 10. NORMALIZED DRAIN TO SOURCE ON  
RESISTANCE vs JUNCTION TEMPERATURE  
©2002 Fairchild Semiconductor Corporation  
HUFA76645P3, HUFA76645S3S Rev. B  
HUFA76645P3, HUFA76645S3S  
Typical Performance Curves (Continued)  
1.2  
1.0  
0.8  
0.6  
0.4  
1.2  
1.1  
1.0  
0.9  
V
= V , I = 250µA  
DS  
I
= 250µA  
GS  
D
D
-80  
-40  
0
40  
80  
120  
160  
200  
-80  
-40  
0
40  
80  
120  
160  
200  
o
o
T , JUNCTION TEMPERATURE ( C)  
T , JUNCTION TEMPERATURE ( C)  
J
J
FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGE vs  
JUNCTION TEMPERATURE  
FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN  
VOLTAGE vs JUNCTION TEMPERATURE  
10  
10000  
V
= 50V  
C
= C  
+ C  
GS GD  
DD  
ISS  
8
6
4
2
0
C
C
+ C  
OSS  
DS GD  
1000  
WAVEFORMS IN  
DESCENDING ORDER:  
I
I
I
= 75A  
= 50A  
= 20A  
C
= C  
D
D
D
RSS  
10  
GD  
100  
70  
V
= 0V, f = 1MHz  
1
GS  
0
30  
60  
90  
120  
150  
0.1  
100  
Q , GATE CHARGE (nC)  
V
, DRAIN TO SOURCE VOLTAGE (V)  
g
DS  
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.  
FIGURE 14. GATE CHARGE WAVEFORMS FOR CONSTANT  
GATE CURRENT  
FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE  
1200  
1200  
V = 10V, V  
GS DD  
= 50V, I = 75A  
D
V
= 4.5V, V  
DD  
= 50V, I = 62A  
GS  
D
1000  
800  
600  
400  
200  
0
1000  
800  
600  
400  
200  
0
t
t
r
d(OFF)  
t
f
t
f
t
r
t
d(OFF)  
t
d(ON)  
t
d(ON)  
0
10  
20  
30  
40  
50  
0
10  
20  
30  
40  
50  
R
, GATE TO SOURCE RESISTANCE (Ω)  
R
, GATE TO SOURCE RESISTANCE (Ω)  
GS  
GS  
FIGURE 15. SWITCHING TIME vs GATE RESISTANCE  
FIGURE 16. SWITCHING TIME vs GATE RESISTANCE  
©2002 Fairchild Semiconductor Corporation  
HUFA76645P3, HUFA76645S3S Rev. B  
HUFA76645P3, HUFA76645S3S  
Test Circuits and Waveforms  
V
DS  
BV  
DSS  
L
t
P
V
DS  
I
VARY t TO OBTAIN  
P
AS  
+
V
DD  
R
REQUIRED PEAK I  
AS  
G
V
DD  
-
V
GS  
DUT  
t
P
I
0V  
AS  
0
0.01Ω  
t
AV  
FIGURE 17. UNCLAMPED ENERGY TEST CIRCUIT  
FIGURE 18. UNCLAMPED ENERGY WAVEFORMS  
V
DS  
V
Q
DD  
R
g(TOT)  
L
V
DS  
V
= 10V  
GS  
V
Q
GS  
g(5)  
+
-
V
DD  
V
= 5V  
V
GS  
GS  
DUT  
V
= 1V  
GS  
I
0
g(REF)  
Q
g(TH)  
Q
Q
gd  
gs  
I
g(REF)  
0
FIGURE 19. GATE CHARGE TEST CIRCUIT  
FIGURE 20. GATE CHARGE WAVEFORMS  
V
t
t
DS  
ON  
OFF  
t
d(OFF)  
t
d(ON)  
t
t
f
R
L
r
V
DS  
90%  
90%  
+
V
GS  
V
DD  
10%  
10%  
0
-
DUT  
90%  
50%  
R
GS  
V
GS  
50%  
PULSE WIDTH  
10%  
V
GS  
0
FIGURE 21. SWITCHING TIME TEST CIRCUIT  
FIGURE 22. SWITCHING TIME WAVEFORM  
©2002 Fairchild Semiconductor Corporation  
HUFA76645P3, HUFA76645S3S Rev. B  
HUFA76645P3, HUFA76645S3S  
PSPICE Electrical Model  
.SUBCKT HUFA76645 2 1 3 ;  
rev 7 June 1999  
CA 12 8 7.4e-9  
CB 15 14 7.4e-9  
CIN 6 8 4.13e-9  
DBODY 7 5 DBODYMOD  
DBREAK 5 11 DBREAKMOD  
DPLCAP 10 5 DPLCAPMOD  
LDRAIN  
DPLCAP  
5
DRAIN  
2
10  
RLDRAIN  
RSLC1  
51  
+
EBREAK 11 7 17 18 121  
EDS 14 8 5 8 1  
EGS 13 8 6 8 1  
ESG 6 10 6 8 1  
EVTHRES 6 21 19 8 1  
EVTEMP 20 6 18 22 1  
DBREAK  
RSLC2  
5
51  
ESLC  
11  
-
50  
+
-
17  
18  
-
DBODY  
RDRAIN  
6
8
EBREAK  
ESG  
IT 8 17 1  
EVTHRES  
+
+
16  
21  
-
19  
8
MWEAK  
LDRAIN 2 5 1e-9  
LGATE 1 9 5.1e-9  
LSOURCE 3 7 4.4e-9  
LGATE  
EVTEMP  
+
RGATE  
GATE  
1
6
-
18  
22  
MMED  
9
20  
MSTRO  
8
RLGATE  
MMED 16 6 8 8 MMEDMOD  
MSTRO 16 6 8 8 MSTROMOD  
MWEAK 16 21 8 8 MWEAKMOD  
LSOURCE  
CIN  
SOURCE  
3
7
RSOURCE  
RBREAK 17 18 RBREAKMOD 1  
RDRAIN 50 16 RDRAINMOD 8.3e-3  
RGATE 9 20 0.96  
RLDRAIN 2 5 10  
RLGATE 1 9 51  
RLSOURCE  
S1A  
S2A  
RBREAK  
12  
15  
13  
8
14  
13  
17  
18  
RLSOURCE 3 7 44  
RSLC1 5 51 RSLCMOD 1e-6  
RSLC2 5 50 1e3  
RSOURCE 8 7 RSOURCEMOD 2.5e-3  
RVTHRES 22 8 RVTHRESMOD 1  
RVTEMP 18 19 RVTEMPMOD 1  
RVTEMP  
19  
-
S1B  
S2B  
13  
CB  
CA  
IT  
14  
+
+
VBAT  
6
8
5
8
EGS  
EDS  
+
-
-
8
S1A 6 12 13 8 S1AMOD  
S1B 13 12 13 8 S1BMOD  
S2A 6 15 14 13 S2AMOD  
S2B 13 15 14 13 S2BMOD  
22  
RVTHRES  
VBAT 22 19 DC 1  
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*200),3.2))}  
.MODEL DBODYMOD D (IS = 3.6e-12 RS = 2.24e-3 TRS1 = 2e-3 TRS2 = 1.03e-6 CJO = 4.5e-9 TT = 5.1e-8 M = 0.60)  
.MODEL DBREAKMOD D (RS = 2.5e- 1TRS1 = 1e- 4TRS2 = 1e-7)  
.MODEL DPLCAPMOD D (CJO = 5.4e- 9IS = 1e-3 0Vj = 1.0 M = 0.9)  
.MODEL MMEDMOD NMOS (VTO = 1.77 KP = 7 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 0.96)  
.MODEL MSTROMOD NMOS (VTO = 2.11 KP = 200 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)  
.MODEL MWEAKMOD NMOS (VTO = 1.5 KP = 0.12 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 9.6 RS = 0.1)  
.MODEL RBREAKMOD RES (TC1 = 1.05e- 3TC2 = -5e-7)  
.MODEL RDRAINMOD RES (TC1 = 8.8e-3 TC2 = 1.7e-5)  
.MODEL RSLCMOD RES (TC1 = 4e-3 TC2 = 1.5e-5)  
.MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 2e-6)  
.MODEL RVTHRESMOD RES (TC1 = -1.9e-3 TC2 = -8e-6)  
.MODEL RVTEMPMOD RES (TC1 = -1.7e- 3TC2 = 1e-7)  
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -4.5 VOFF= -2.0)  
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.0 VOFF= -4.5)  
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1.0 VOFF= 0.5)  
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.5 VOFF= -1.0)  
.ENDS  
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global  
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.  
©2002 Fairchild Semiconductor Corporation  
HUFA76645P3, HUFA76645S3S Rev. B  
HUFA76645P3, HUFA76645S3S  
SABER Electrical Model  
REV 7 June 1999  
template hufa76645 n2,n1,n3  
electrical n2,n1,n3  
{
var i iscl  
d..model dbodymod = (is = 3.6e-12, cjo = 4.5e-9, tt = 5.1e-8, m = 0.60)  
d..model dbreakmod = ()  
d..model dplcapmod = (cjo = 5.4e-9, is = 1e-30, vj=1.0, m = 0.9 )  
m..model mmedmod = (type=_n, vto = 1.77, kp = 7, is = 1e-30, tox = 1)  
m..model mstrongmod = (type=_n, vto = 2.11, kp = 200, is = 1e-30, tox = 1)  
m..model mweakmod = (type=_n, vto = 1.5, kp = 0.12, is = 1e-30, tox = 1)  
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -4.5, voff = -2.0)  
sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -2.0, voff = -4.5)  
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -1.0, voff = 0.5)  
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.5, voff = -1.0)  
LDRAIN  
RLDRAIN  
RDBODY  
DPLCAP  
DRAIN  
2
5
10  
RSLC1  
51  
RDBREAK  
72  
DBREAK  
11  
c.ca n12 n8 = 7.4e-9  
c.cb n15 n14 = 7.4e-9  
c.cin n6 n8 = 4.13e-9  
RSLC2  
ISCL  
50  
-
d.dbody n7 n71 = model=dbodymod  
d.dbreak n72 n11 = model=dbreakmod  
d.dplcap n10 n5 = model=dplcapmod  
71  
RDRAIN  
6
8
ESG  
EVTHRES  
+
+
16  
21  
-
19  
8
MWEAK  
i.it n8 n17 = 1  
LGATE  
EVTEMP  
+
DBODY  
RGATE  
GATE  
1
6
-
18  
22  
EBREAK  
+
l.ldrain n2 n5 = 1e-9  
l.lgate n1 n9 = 5.1e-9  
l.lsource n3 n7 = 4.4e-9  
MMED  
9
20  
MSTRO  
8
17  
18  
-
RLGATE  
LSOURCE  
CIN  
SOURCE  
3
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u  
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u  
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u  
7
RSOURCE  
RLSOURCE  
S1A  
S2A  
res.rbreak n17 n18 = 1, tc1 = 1.05e-3, tc2 = -5e-7  
res.rdbody n71 n5 = 2.24e-3, tc1 = 2e-3, tc2 = 1.03e-6  
res.rdbreak n72 n5 = 2.5e-1, tc1 = 1e-4, tc2 = 1e-7  
res.rdrain n50 n16 = 8.3e-3, tc1 = 8.8e-3, tc2 = 1.7e-5  
res.rgate n9 n20 = 0.96  
res.rldrain n2 n5 = 10  
res.rlgate n1 n9 = 51  
res.rlsource n3 n7 = 44  
res.rslc1 n5 n51 = 1e-6, tc1 = 4e-3, tc2 = 1.5e-5  
res.rslc2 n5 n50 = 1e3  
RBREAK  
12  
15  
13  
14  
13  
17  
18  
8
RVTEMP  
19  
S1B  
S2B  
13  
CB  
CA  
IT  
14  
-
+
+
VBAT  
6
8
5
8
EGS  
EDS  
+
-
-
8
22  
res.rsource n8 n7 = 2.5e-3, tc1 = 1e-3, tc2 = 2e-6  
res.rvtemp n18 n19 = 1, tc1 = -1.7e-3, tc2 = 1e-7  
res.rvthres n22 n8 = 1, tc1 = -1.9e-3, tc2 = -8e-6  
RVTHRES  
spe.ebreak n11 n7 n17 n18 = 121  
spe.eds n14 n8 n5 n8 = 1  
spe.egs n13 n8 n6 n8 = 1  
spe.esg n6 n10 n6 n8 = 1  
spe.evtemp n20 n6 n18 n22 = 1  
spe.evthres n6 n21 n19 n8 = 1  
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod  
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod  
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod  
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod  
v.vbat n22 n19 = dc=1  
equations {  
i (n51->n50) +=iscl  
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/200))** 3.2))  
}
}
©2002 Fairchild Semiconductor Corporation  
HUFA76645P3, HUFA76645S3S Rev. B  
HUFA76645P3, HUFA76645S3S  
JUNCTION  
SPICE Thermal Model  
th  
REV 7 June 1999  
HUFA76645T  
RTHERM1  
RTHERM2  
RTHERM3  
RTHERM4  
RTHERM5  
RTHERM6  
CTHERM1  
CTHERM1 th 6 6.4e-3  
CTHERM2 6 5 3.0e-2  
CTHERM3 5 4 1.4e-2  
CTHERM4 4 3 1.6e-2  
CTHERM5 3 2 5.5e-2  
CTHERM6 2 tl 1.5  
6
CTHERM2  
CTHERM3  
CTHERM4  
CTHERM5  
CTHERM6  
RTHERM1 th 6 3.4e-3  
RTHERM2 6 5 8.6e-3  
RTHERM3 5 4 2.3e-2  
RTHERM4 4 3 1.3e-1  
RTHERM5 3 2 1.8e-1  
RTHERM6 2 tl 3.9e-2  
5
SABER Thermal Model  
SABER thermal model HUFA76645T  
4
3
2
template thermal_model th tl  
thermal_c th, tl  
{
ctherm.ctherm1 th 6 = 6.4e-3  
ctherm.ctherm2 6 5 = 3.0e-2  
ctherm.ctherm3 5 4 = 1.4e-2  
ctherm.ctherm4 4 3 = 1.6e-2  
ctherm.ctherm5 3 2 = 5.5e-2  
ctherm.ctherm6 2 tl = 1.5  
rtherm.rtherm1 th 6 = 3.4e-3  
rtherm.rtherm2 6 5 = 8.6e-3  
rtherm.rtherm3 5 4 = 2.3e-2  
rtherm.rtherm4 4 3 = 1.3e-1  
rtherm.rtherm5 3 2 = 1.8e-1  
rtherm.rtherm6 2 tl = 3.9e-2  
}
tl  
CASE  
©2002 Fairchild Semiconductor Corporation  
HUFA76645P3, HUFA76645S3S Rev. B  
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As used herein:  
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Definition of Terms  
Datasheet Identification  
Product Status  
Definition  
Advance Information  
Formative or  
In Design  
This datasheet contains the design specifications for  
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This datasheet contains preliminary data, and  
supplementary data will be published at a later date.  
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Rev. H4  

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