IRFR110TF [FAIRCHILD]
Power Field-Effect Transistor, N-Channel, Metal-oxide Semiconductor FET;
| 型号： | IRFR110TF |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Power Field-Effect Transistor, N-Channel, Metal-oxide Semiconductor FET |
| 文件： | 总7页 (文件大小：97K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IRFR110, IRFU110
Data Sheet
January 2002
4.7A, 100V, 0.540 Ohm, N-Channel Power
MOSFETs
Features
• 4.7A, 100V
These are N-Channel enhancement mode silicon gate
power field effect transistors designed, tested, and
guaranteed to withstand a specified level of energy in the
breakdown avalanche mode of operation. These advanced
power MOSFETs are designed for use in applications such
as switching regulators, switching converters, motor drivers,
relay drivers and drivers for high-power bipolar switching
transistors requiring high speed and low gate-drive power.
These transistors can be operated directly from integrated
circuits.
• r = 0.540Ω
DS(ON)
• Single Pulse Avalanche Energy Rated
• SOA is Power Dissipation Limited
• Nanosecond Switching Speeds
• Linear Transfer Characteristics
• High Input Impedance
o
• 175 C Operating Temperature
• Related Literature
Formerly developmental type TA17441.
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Ordering Information
PART NUMBER
IRFU110
IRFR110
PACKAGE
TO-251AA
TO-252AA
BRAND
IFU110
IFR110
Symbol
D
NOTE: When ordering, use the entire part number.
G
S
Packaging
JEDEC TO-251AA
JEDEC TO-252AA
SOURCE
DRAIN
GATE
GATE
SOURCE
DRAIN (FLANGE)
DRAIN (FLANGE)
©2002 Fairchild Semiconductor Corporation
IRFR110, IRFU110 Rev. B
IRFR110, IRFU110
o
Absolute Maximum Ratings T = 25 C, Unless Otherwise Specified
C
IRFR110, IRFU110
UNITS
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
100
100
4.7
3.3
17
20
30
0.2
V
V
A
A
A
V
W
DS
Drain to Gate Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
DGR
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I
D
D
o
T
= 100 C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I
C
Pulsed Drain Current (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
DM
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D
o
W/ C
Single Pulse Avalanche Rating (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E
19
mj
C
AS
o
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T , T
-55 to 175
J
STG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T
o
o
300
260
C
C
L
pkg
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
o
o
1. T = 25 C to 150 C.
J
o
Electrical Specifications
T = 25 C, Unless Otherwise Specified
C
PARAMETER
SYMBOL
BV
TEST CONDITIONS
= 250µA, V = 0V (Figure 10)
MIN
TYP
MAX
-
UNITS
V
Drain to Source Breakdown Voltage
Gate to Threshold Voltage
I
100
-
-
-
-
DSS
D
GS
V
V
V
V
= V , I = 250µA
DS
2
-
4
V
GS(TH)
GS
DS
DS
D
Zero Gate Voltage Drain Current
I
= Rated BV
, V
= 0V
25
250
µA
µA
DSS
DSS GS
= 0.8 x Rated BV , V
= 0V,
-
DSS GS
o
T = 150 C
J
On-State Drain Current
I
V
V
> I
=
x r
, V
= 10V
4.7
-
-
-
A
nA
Ω
D(ON)
DS
GS
D(ON)
20V
DS(ON)MAX GS
Gate to Source Leakage Current
I
-
-
100
GSS
Drain to Source On Resistance
(Note 4)
r
I
= 3.3A, V
= 10V (Figures 8, 9)
= 3.3A (Figure 12)
0.41
0.540
DS(ON)
D GS
Forward Transconductance (Note 4)
Turn-On Delay Time
Rise Time
g
V
V
= 50V, I
DS
1.3
2.0
7.6
24
-
11
36
21
21
7.7
-
S
fs
DS
t
= 50V, I ≈ 5.6A, R
= 10V
= 24Ω, R = 9.1Ω,
-
-
-
-
-
-
-
ns
ns
ns
ns
nC
nC
nC
d(ON)
DD
D
GS
L
V
GS
t
r
MOSFET Switching Times are Essentially Indepen-
dent of Operating Temperature
Turn-Off Delay Time
Fall Time
t
14
d(OFF)
t
14
f
Total Gate Charge
Q
V
= 10V, I ≈ 5.6A, V = 0.8 x Rated BV
,
5.2
1.5
2.2
g(TOT)
GS
R = 14Ω, I
D
DS
DSS
= 1.5mA (Figure 14)
L
G(REF)
Gate to Source Charge
Gate to Drain “Miller” Charge
Q
gs
gd
Gate Charge is Essentially Independent of Operat-
ing Temperature
Q
-
Input Capacitance
C
V
= 0V, V = 25V, f = 1.0MHz
DS
-
-
-
-
180
82
-
-
-
-
pF
pF
pF
nH
ISS
GS
(Figure 11)
Output Capacitance
C
OSS
RSS
Reverse Transfer Capacitance
Internal Drain Inductance
C
15
L
Measured from the
Drain Lead, 6mm
(0.25in) from Package Internal Devices
Modified MOSFET
Symbol Showing the
4.5
D
S
to Center of Die
Inductances
D
Internal Source Inductance
L
Measured from The
Source Lead, 6mm
(0.25in) from Header to
Source Bonding Pad
-
7.5
-
nH
L
D
G
L
S
S
o
Junction to Case
R
R
-
-
-
-
5.0
C/W
θJC
o
Junction to Ambient
Free Air Operation
110
C/W
θJA
©2002 Fairchild Semiconductor Corporation
IRFR110, IRFU110 Rev. B
IRFR110, IRFU110
Source to Drain Diode Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
4.7
UNITS
D
S
Continuous Source to Drain Current
Pulse Source to Drain Current (Note 2)
I
Modified MOSFET
Symbol Showing the
Integral Reverse
-
-
-
-
A
A
SD
I
17
SDM
P-N Junction Diode
G
o
Source to Drain Diode Voltage (Note 4)
Reverse Recovery Time
Reverse Recovery Charge
NOTES:
V
T = 25 C, I
J
= 4.7A, V
GS
= 0V (Figure 13)
-
-
2.5
200
0.83
V
SD
SD
SD
SD
o
t
T = 25 C, I
J
= 5.6A, dI /dt = 100A/µs
SD
46
96
ns
µC
rr
o
Q
T = 25 C, I
= 5.6A, dI /dt = 100A/µs
SD
0.17
0.38
RR
J
2. Repetitive rating: pulse width limited by maximum junction temperature. See Transient Thermal Impedance curve (Figure 3).
o
3. V
DD
= 25V, starting T = 25 C, L = 1.3mH, R = 25Ω, peak I = 4.7A.
J G AS
4. Pulse test: pulse width ≤ 300µs, duty cycle ≤ 2%.
Typical Performance Curves Unless Otherwise Specified
1.2
1.0
0.8
0.6
0.4
0.2
0
5
4
3
2
1
0
0
25
50
75
100
125
o
150
175
25
50
75
100
125
150
175
o
T
, CASE TEMPERATURE ( C)
T
, CASE TEMPERATURE ( C)
C
C
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
10
0.5
0.2
1
0.1
0.1
P
DM
0.05
0.02
0.01
t
1
t
2
SINGLE PULSE
NOTES:
DUTY FACTOR: D = t /t
1
2
PEAK T = P
x Z
+ T
J
DM
JC C
θ
0.01
-5
10
-4
10
-3
10
-2
10
-1
10
1
10
t , RECTANGULAR PULSE DURATION (s)
1
FIGURE 3. MAXIMUM TRANSIENT THERMAL IMPEDANCE
©2002 Fairchild Semiconductor Corporation
IRFR110, IRFU110 Rev. B
IRFR110, IRFU110
Typical Performance Curves Unless Otherwise Specified (Continued)
2
10
8
10
o
V
= 10V
= 8V
T
T
= 25 C
GS
C
= MAX RATED
SINGLE PULSE
10µs
J
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
V
GS
10
100µs
6
V
= 7V
= 6V
GS
1ms
4
V
1.0
0.1
GS
10ms
OPERATION IN THIS
AREA LIMITED
2
DC
V
= 5V
= 4V
GS
BY r
DS(ON)
V
GS
40
, DRAIN TO SOURCE VOLTAGE (V)
0
2
3
1
10
10
10
0
10
V
DS
20
30
50
V
, DRAIN TO SOURCE VOLTAGE (V)
DS
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
FIGURE 5. OUTPUT CHARACTERISTICS
10
10
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
PULSE DURATION = 80µs
V
10V
GS
DUTY CYCLE = 0.5% MAX
V
≥ 50V
DS
8
6
4
2
0
V
8V
7V
GS
1
o
T
= 25 C
J
o
V
T = 175 C
J
GS
0.1
-2
V
= 6V
GS
V
5V
4V
GS
V
GS
10
0
2
4
6
8
10
0
2
4
6
8
10
V
, DRAIN TO SOURCE VOLTAGE (V)
V
, GATE TO SOURCE VOLTAGE (V)
DS
GS
FIGURE 6. SATURATION CHARACTERISTICS
FIGURE 7. TRANSFER CHARACTERISTICS
5
4
3
2
1
0
3.0
2.4
1.8
1.2
0.5
0
PULSE DURATION = 80µs
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
DUTY CYCLE = 0.5% MAX
V
= 10V
GS
I
= 3.3A
D
V
= 20V
V
GS
= 10V
GS
-60 -40 -20
0
20 40 60 80 100 120 140 160 180
o
0
4
8
12
16
20
I
, DRAIN CURRENT (A)
T , JUNCTION TEMPERATURE ( C)
J
D
FIGURE 8. DRAINTO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
FIGURE 9. NORMALIZED DRAINTO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
©2002 Fairchild Semiconductor Corporation
IRFR110, IRFU110 Rev. B
IRFR110, IRFU110
Typical Performance Curves Unless Otherwise Specified (Continued)
1.25
1.15
1.05
0.95
0.85
0.75
500
400
300
200
100
0
V
= 0V, f = 1MHz
= CGS + CGD
I
= 250µA
GS
ISS
D
C
C
C
= CGD
≈ CDS + CGS
RSS
OSS
C
ISS
C
OSS
C
RSS
2
-60 -40 -20
0
20 40 60 80 100 120 140 160 180
o
1
10
, DRAIN TO SOURCE VOLTAGE (V)
10
T , JUNCTION TEMPERATURE ( C)
V
DS
J
FIGURE 10. DRAINTO SOURCE BREAKDOWNVOLTAGE vs
JUNCTION TEMPERATURE
FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
2
2.5
10
PULSE DURATION = 80µs
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
DUTY CYCLE = 0.5% MAX
V
≥ 50V
DS
2.0
1.5
1.0
0.5
0
o
T
= 25 C
J
10
o
T
= 175 C
J
o
= 175 C
T
J
1.0
0.1
o
T
= 25 C
J
0
0.4
0.8
1.2
1.6
2.0
0
2
4
6
8
10
I
, DRAIN CURRENT (A)
V
, SOURCE TO DRAIN VOLTAGE (V)
D
SD
FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT
FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE
20
I
= 5.6A
D
V
V
V
= 80V
= 50V
= 20V
DS
DS
DS
16
12
8
4
0
0
2
4
6
8
10
Q , GATE CHARGE (nC)
g
FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE
©2002 Fairchild Semiconductor Corporation
IRFR110, IRFU110 Rev. B
IRFR110, IRFU110
Test Circuits and Waveforms
V
DS
BV
DSS
L
t
P
V
DS
I
VARY t TO OBTAIN
P
AS
+
V
DD
R
REQUIRED PEAK I
AS
G
V
DD
-
V
GS
DUT
t
P
I
AS
0V
0
0.01Ω
t
AV
FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 16. UNCLAMPED ENERGY WAVEFORMS
t
t
ON
OFF
t
d(OFF)
t
d(ON)
t
t
f
r
R
L
V
DS
90%
90%
+
V
DD
10%
10%
R
G
0
0
-
DUT
90%
50%
V
GS
50%
PULSE WIDTH
10%
V
GS
FIGURE 17. SWITCHING TIME TEST CIRCUIT
FIGURE 18. RESISTIVE SWITCHING WAVEFORMS
V
DS
(ISOLATED
SUPPLY)
CURRENT
REGULATOR
V
DD
Q
SAME TYPE
AS DUT
g(TOT)
V
GS
12V
BATTERY
0.2µF
Q
gd
50kΩ
0.3µF
Q
gs
D
S
V
DS
G
DUT
0
0
I
G(REF)
0
V
I
DS
G(REF)
I
CURRENT
SAMPLING
RESISTOR
I
CURRENT
SAMPLING
RESISTOR
G
D
FIGURE 19. GATE CHARGE TEST CIRCUIT
FIGURE 20. GATE CHARGE WAVEFORMS
©2002 Fairchild Semiconductor Corporation
IRFR110, IRFU110 Rev. B
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
â
SMART START™
STAR*POWER™
Stealth™
VCX™
FAST
ACEx™
Bottomless™
CoolFET™
OPTOLOGIC™
OPTOPLANAR™
PACMAN™
FASTr™
FRFET™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SyncFET™
GlobalOptoisolator™
GTO™
HiSeC™
ISOPLANAR™
LittleFET™
MicroFET™
MicroPak™
MICROWIRE™
CROSSVOLT™
DenseTrench™
DOME™
POP™
Power247™
PowerTrenchâ
QFET™
EcoSPARK™
E2CMOSTM
TinyLogic™
QS™
EnSignaTM
TruTranslation™
UHC™
QT Optoelectronics™
Quiet Series™
SILENTSWITCHERâ
FACT™
FACT Quiet Series™
UltraFETâ
STAR*POWER is used under license
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITYARISING OUT OF THE APPLICATION OR USE OFANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICESORSYSTEMSWITHOUTTHEEXPRESSWRITTENAPPROVALOFFAIRCHILDSEMICONDUCTORCORPORATION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or
In Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Obsolete
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. H4
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