ISL9N306AD3 [FAIRCHILD]
N-Channel Logic Level PWM Optimized UltraFET Trench Power MOSFETs 30V, 50A, 6mз; N沟道逻辑电平PWM优化UltraFET沟道功率MOSFET 30V ， 50A ， 6mз
| 型号： | ISL9N306AD3 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | N-Channel Logic Level PWM Optimized UltraFET Trench Power MOSFETs 30V, 50A, 6mз |
| 文件： | 总11页 (文件大小：248K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
June 2003
ISL9N306AD3 / ISL9N306AD3ST
N-Channel Logic Level PWM Optimized UltraFET® Trench Power MOSFETs
30V, 50A, 6mΩ
General Description
Features
This device employs a new advanced trench MOSFET
technology and features low gate charge while maintaining
low on-resistance.
•
•
•
•
•
•
Fast switching
r
r
DS(ON) = 0.0052Ω(Typ), VGS = 10V
DS(ON) = 0.0085Ω(Typ), VGS = 4.5V
Optimized for switching applications, this device improves
the overall efficiency of DC/DC converters and allows
operation to higher switching frequencies.
Qg (Typ) = 30nC, VGS = 5V
gd (Typ) = 11nC
ISS (Typ) = 3400pF
Q
Applications
•
DC/DC converters
C
SOURCE
DRAIN
GATE
DRAIN (FLANGE)
D
S
DRAIN
(FLANGE)
GATE
G
SOURCE
TO-252
TO-251
MOSFET Maximum Ratings TA = 25°C unless otherwise noted
Symbol
VDSS
VGS
Parameter
Ratings
30
Units
Drain to Source Voltage
Gate to Source Voltage
Drain Current
V
V
±20
Continuous (TC = 25oC, VGS = 10V)
Continuous (TC = 100oC, VGS = 4.5V)
Continuous (TC = 25oC, VGS = V, RθJC = 52oC/W)
Pulsed
50
50
A
A
A
A
ID
16
Figure 4
Power dissipation
Derate above 25oC
125
0.83
W
PD
W/oC
TJ, TSTG
Operating and Storage Temperature
-55 to 175
oC
Thermal Characteristics
RθJC
RθJA
RθJA
Thermal Resistance Junction to Case TO-251, TO-252
1.2
100
52
oC/W
oC/W
oC/W
Thermal Resistance Junction to Ambient TO-251, TO-252
Thermal Resistance Junction to Ambient TO-252, 1in2 copper pad area
Package Marking and Ordering Information
Device Marking
N306AD
Device
Package
TO-252AA
TO-251AA
Reel Size
330mm
Tube
Tape Width
Quantity
ISL9N306AD3ST
ISL9N306AD3
16mm
N/A
2500 units
75 units
N306AD
©2003 Fairchild Semiconductor Corporation
ISL9N306AD3 / ISL9N306AD3ST Rev. B2
Electrical Characteristics TA = 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
BVDSS
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
ID = 250µA, VGS = 0V
30
-
-
-
-
-
-
V
VDS = 25V
1
IDSS
µA
nA
VGS = 0V
TC = 150o
-
250
±100
IGSS
VGS = ±20V
-
On Characteristics
VGS(TH)
Gate to Source Threshold Voltage
VGS = VDS, ID = 250µA
ID = 50A, VGS = 10V
ID = 50A, VGS = 4.5V
1
-
-
3
V
0.0052 0.0060
0.0085 0.0095
rDS(ON)
Drain to Source On Resistance
Ω
-
Dynamic Characteristics
CISS
Input Capacitance
-
-
-
-
-
-
-
-
3400
650
300
60
-
-
pF
pF
pF
nC
nC
nC
nC
nC
VDS = 15V, VGS = 0V,
f = 1MHz
COSS
CRSS
Qg(TOT)
Qg(5)
Qg(TH)
Qgs
Output Capacitance
Reverse Transfer Capacitance
Total Gate Charge at 10V
Total Gate Charge at 5V
Threshold Gate Charge
Gate to Source Gate Charge
Gate to Drain “Miller” Charge
-
VGS = 0V to 10V
90
45
4.5
-
VGS = 0V to 5V
30
VDD = 15V
VGS = 0V to 1V ID = 50A
Ig = 1.0mA
3.0
10
Qgd
11
-
Switching Characteristics (VGS = 4.5V)
tON
td(ON)
tr
Turn-On Time
Turn-On Delay Time
Rise Time
-
-
-
-
-
-
-
131
ns
ns
ns
ns
ns
ns
16
70
34
30
-
-
-
V
DD = 15V, ID = 16A
VGS = 4.5V, RGS = 4.3Ω
td(OFF)
tf
Turn-Off Delay Time
Fall Time
-
-
tOFF
Turn-Off Time
97
Switching Characteristics (VGS = 10V)
tON
td(ON)
tr
Turn-On Time
Turn-On Delay Time
Rise Time
-
-
-
-
-
-
-
80
ns
ns
ns
ns
ns
ns
10
43
62
29
-
-
-
V
DD = 15V, ID = 16A
VGS = 10V, RGS = 4.3Ω
td(OFF)
tf
Turn-Off Delay Time
Fall Time
-
-
tOFF
Turn-Off Time
137
Unclamped Inductive Switching
tAV
Avalanche Time
ID = 30A, L = 200µH
428
-
-
µs
Drain-Source Diode Characteristics
I
SD = 50A
-
-
-
-
-
-
-
-
1.25
1.0
35
V
V
VSD
Source to Drain Diode Voltage
ISD = 25A
trr
Reverse Recovery Time
ISD = 50A, dISD/dt = 100A/µs
ISD = 50A, dISD/dt = 100A/µs
ns
nC
QRR
Reverse Recovered Charge
30
©2003 Fairchild Semiconductor Corporation
ISL9N306AD3 / ISL9N306AD3ST Rev. B2
Typical Characteristic
1.2
1.0
0.8
0.6
0.4
0.2
0
60
50
40
30
20
10
0
V
= 10V
= 4.5V
GS
V
GS
25
50
75
100
125
150
175
150
0
25
50
75
100
175
125
o
o
T
, CASE TEMPERATURE ( C)
T , CASE TEMPERATURE ( C)
C
C
Figure 1. Normalized Power Dissipation vs
Ambient Temperature
Figure 2. Maximum Continuous Drain Current vs
Case Temperature
2
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
1
0.1
0.05
0.02
0.01
P
DM
0.1
t
1
t
2
SINGLE PULSE
NOTES:
DUTY FACTOR: D = t /t
1
2
PEAK T = P
x Z
x R
+ T
J
DM
θJC
θJC C
0.01
-5
-4
-3
-2
-1
0
1
10
10
10
10
t, RECTANGULAR PULSE DURATION (s)
10
10
10
Figure 3. Normalized Maximum transient Thermal Impedance
2000
o
T
= 25 C
C
FOR TEMPERATURES
o
1000
ABOVE 25 C DERATE PEAK
CURRENT AS FOLLOWS:
175 – T
150
C
I = I
25
V
= 10V
GS
V
= 5V
GS
100
40
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
-5
-4
-3
-2
-1
0
1
10
10
10
10
t, PULSE WIDTH (s)
10
10
10
Figure 4. Peak Current Capability
©2003 Fairchild Semiconductor Corporation
ISL9N306AD3 / ISL9N306AD3ST Rev. B2
Typical Characteristic (Continued)
100
100
75
50
25
0
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
V = 4.5V
GS
V
= 10V
V
= 3.5V
V
= 15V
GS
GS
DD
75
50
25
0
V
= 3V
GS
o
T
= 175 C
J
o
T
= 25 C
o
C
T
= 25 C
J
o
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
T
= -55 C
J
0
0.5
V , DRAIN TO SOURCE VOLTAGE (V)
DS
1.0
1.5
2.0
1
2
3
4
5
V
, GATE TO SOURCE VOLTAGE (V)
GS
Figure 5. Transfer Characteristics
Figure 6. Saturation Characteristics
25
2.0
PULSE DURATION = 80µs
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
DUTY CYCLE = 0.5% MAX
o
T
= 25 C
C
I
= 25A
D
20
15
10
5
1.5
1.0
0.5
I = 50A
D
I
=5A
D
V
= 10V, I = 50A
D
GS
-80
-40
0
40
80
120
160
200
2
4
6
8
10
o
V
, GATE TO SOURCE VOLTAGE (V)
T , JUNCTION TEMPERATURE ( C)
GS
J
Figure 7. Drain to Source On Resistance vs Gate
Voltage and Drain Current
Figure 8. Normalized Drain to Source On
Resistance vs Junction Temperature
1.4
1.2
I
= 250µA
V
= V , I = 250µA
DS D
D
GS
1.0
0.6
0.2
1.1
1.0
0.9
-80
-40
0
40
80
120
160
200
-80
-40
0
40
80
120
160
200
o
o
T , JUNCTION TEMPERATURE ( C)
T , JUNCTION TEMPERATURE ( C)
J
J
Figure 9. Normalized Gate Threshold Voltage vs
Junction Temperature
Figure 10. Normalized Drain to Source
Breakdown Voltage vs Junction Temperature
©2003 Fairchild Semiconductor Corporation
ISL9N306AD3 / ISL9N306AD3ST Rev. B2
Typical Characteristic (Continued)
5000
10
8
V
= 15V
DD
C
= C + C
GS GD
ISS
C
C
+ C
OSS
DS GD
6
1000
C
= C
GD
RSS
4
WAVEFORMS IN
DESCENDING ORDER:
2
I
I
I
= 50A
= 25A
= 5A
D
D
D
V
= 0V, f = 1MHz
GS
0
100
0
10
20
30
40
50
60
30
0.1
1
10
V
, DRAIN TO SOURCE VOLTAGE (V)
Q , GATE CHARGE (nC)
DS
g
Figure 11. Capacitance vs Drain to Source
Voltage
Figure 12. Gate Charge Waveforms for Constant
Gate Currents
300
500
V
= 4.5V, V = 15V, I = 16A
V
= 10V, V = 15V, I = 16A
GS
DD
D
GS DD D
250
200
150
100
50
400
300
200
100
0
t
f
t
r
t
d(OFF)
t
f
t
d(OFF)
t
r
t
d(ON)
t
d(ON)
0
0
10
20
30
40
50
0
10
R , GATE TO SOURCE RESISTANCE (Ω)
GS
20
30
40
50
R
, GATE TO SOURCE RESISTANCE (Ω)
GS
Figure 13. Switching Time vs Gate Resistance
Figure 14. Switching Time vs Gate Resistance
Test Circuits and Waveforms
V
BV
DSS
DS
t
P
V
DS
L
I
AS
V
DD
VARY t TO OBTAIN
P
+
-
R
REQUIRED PEAK I
G
AS
V
DD
V
GS
DUT
t
P
I
0V
AS
0
0.01Ω
t
AV
Figure 15. Unclamped Energy Test Circuit
Figure 16. Unclamped Energy Waveforms
©2003 Fairchild Semiconductor Corporation
ISL9N306AD3 / ISL9N306AD3ST Rev. B2
Test Circuits and Waveforms (Continued)
V
DS
V
Q
DD
g(TOT)
R
L
V
DS
V
= 10V
GS
Q
g(5)
V
GS
+
-
V
V
= 5V
DD
V
GS
GS
V
= 1V
DUT
GS
0
I
g(REF)
Q
g(TH)
Q
Q
gd
gs
I
g(REF)
0
Figure 17. Gate Charge Test Circuit
Figure 18. Gate Charge Waveforms
V
t
t
DS
ON
OFF
t
d(OFF)
t
d(ON)
t
t
f
R
L
r
V
DS
90%
90%
+
V
GS
V
DD
10%
10%
0
-
DUT
90%
50%
R
GS
V
GS
50%
PULSE WIDTH
10%
V
GS
0
Figure 19. Switching Time Test Circuit
Figure 20. Switching Time Waveforms
©2003 Fairchild Semiconductor Corporation
ISL9N306AD3 / ISL9N306AD3ST Rev. B2
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, TJM, and the
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, PDM, in an
125
100
75
R
= 33.32 + 23.84/(0.268+Area)
θJA
application.
Therefore the application’s ambient
temperature, TA (oC), and thermal resistance RθJA (oC/W)
must be reviewed to ensure that TJM is never exceeded.
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.
(T
– T )
JM
Z
A
(EQ. 1)
P
= -----------------------------
DM
50
θJA
In using surface mount devices such as the TO-252
package, the environment in which it is applied will have a
significant influence on the part’s current and maximum
power dissipation ratings. Precise determination of PDM is
complex and influenced by many factors:
25
0.01
0.1
1
2
10
AREA, TOP COPPER AREA (in )
Figure 21. Thermal Resistance vs Mounting
Pad Area
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
2. The number of copper layers and the thickness of the
board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
Fairchild provides thermal information to assist the
designer’s preliminary application evaluation. Figure 21
defines the RθJA for the device as a function of the top
copper (component side) area. This is for a horizontally
positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Fairchild device
Spice thermal model or manually utilizing the normalized
maximum transient thermal impedance curve.
Displayed on the curve are RθJA values listed in the
Electrical Specifications table. The points were chosen to
depict the compromise between the copper board area, the
thermal resistance and ultimately the power dissipation,
PDM
.
Thermal resistances corresponding to other copper areas
can be obtained from Figure 21 or by calculation using
Equation 2. RθJA is defined as the natural log of the area
times a coefficient added to a constant. The area, in square
inches is the top copper area including the gate and source
pads.
23.84
(0.268 + Area)
R
= 33.32 + ------------------------------------
(EQ. 2)
θ JA
©2003 Fairchild Semiconductor Corporation
ISL9N306AD3 / ISL9N306AD3ST Rev. B2
PSPICE Electrical Model
.SUBCKT ISL9N306A 2 1 3 ;
rev May 2001
CA 12 8 2.0e-9
CB 15 14 2.3e-9
CIN 6 8 3e-9
LDRAIN
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
DPLCAP
DRAIN
2
5
10
RLDRAIN
RSLC1
51
EBREAK 11 7 17 18 35.8
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
DBREAK
+
RSLC2
5
51
ESLC
11
-
50
+
-
17
DBODY
RDRAIN
6
8
EBREAK 18
-
ESG
EVTHRES
+
16
IT 8 17 1
21
+
-
19
8
MWEAK
LGATE
EVTEMP
LDRAIN 2 5 1.0e-9
LGATE 1 9 4.58e-9
LSOURCE 3 7 1.47e-9
RGATE
GATE
1
6
+
-
18
22
MMED
9
20
MSTRO
RLGATE
LSOURCE
CIN
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
SOURCE
3
8
7
RSOURCE
RLSOURCE
S1A
S2A
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 1e-3
RGATE 9 20 2.69
RLDRAIN 2 5 10
RLGATE 1 9 45.8
RBREAK
12
15
13
14
13
17
18
8
RVTEMP
19
S1B
S2B
13
CB
CA
IT
14
-
RLSOURCE 3 7 14.7
+
+
VBAT
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 3.5e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
6
8
5
8
EGS
EDS
+
-
-
8
22
RVTHRES
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*275),5))}
.MODEL DBODYMOD D (IS = 3.6e-11 N=1.075 RS = 3.5e-3 TRS1 = 1e-3 TRS2 = 1e-6 XTI=1.0 CJO = 1.45e-9 TT = 8e-11 M =
0.51)
.MODEL DBREAKMOD D (RS = 1.7e-1 TRS1 = 1e-3 TRS2 = -8.9e-6)
.MODEL DPLCAPMOD D (CJO = 11.5e-10 IS = 1e-30 N = 10 M = 0.46)
.MODEL MMEDMOD NMOS (VTO = 1.7 KP = 9 IS=1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 2.69)
.MODEL MSTROMOD NMOS (VTO = 2.1 KP = 100 IS = 1e-30 N= 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 1.36 KP = 0.05 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 26.9 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 1e-3 TC2 = -7e-7)
.MODEL RDRAINMOD RES (TC1 = 1.2e-2 TC2 = 3.0e-5)
.MODEL RSLCMOD RES (TC1 = 1e-3 TC2 = 1e-6)
.MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6)
.MODEL RVTHRESMOD RES (TC1 = -2.6e-3 TC2 = -7.5e-6)
.MODEL RVTEMPMOD RES (TC1 = -1.8e-3 TC2 = 1e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -4.0 VOFF= -0.8)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.8 VOFF= -4.0)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.3 VOFF= 0.2)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.2 VOFF= -0.3)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
©2003 Fairchild Semiconductor Corporation
ISL9N306AD3 / ISL9N306AD3ST Rev. B2
SABER Electrical Model
REV May 2001
template ISL9N306A n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl = 3.6e-11, nl=1.075 , rs = 3.5e-3, trs1 = 1e-3, trs2 = 1e-6, xti=1.0, cjo = 1.45e-9, tt = 8e-11, m = 0.51,)
dp..model dbreakmod = (rs =0.17, trs1 = 1e-3, trs2 = -8.9e-6)
dp..model dplcapmod = (cjo = 11.5e-10, isl=10e-30, nl=10, m=0.46)
m..model mmedmod = (type=_n, vto = 1.7, kp=9, is=1e-30, tox=1)
m..model mstrongmod = (type=_n, vto = 2.1, kp = 100, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 1.36, kp = 0.05, is = 1e-30, tox = 1, rs=0.1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -4.0, voff = -0.8)
sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -0.8, voff = -4.0)
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.3, voff = 0.2)
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.2, voff = -0.3)
LDRAIN
DPLCAP
DRAIN
2
5
10
c.ca n12 n8 = 2.0e-9
RLDRAIN
RSLC1
51
c.cb n15 n14 = 2.3e-9
c.cin n6 n8 = 3e-9
RSLC2
ISCL
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
DBREAK
11
50
-
RDRAIN
6
8
ESG
DBODY
i.it n8 n17 = 1
EVTHRES
+
16
21
+
-
19
8
MWEAK
LGATE
EVTEMP
l.ldrain n2 n5 = 1e-9
l.lgate n1 n9 = 4.58e-9
RGATE
GATE
6
+
-
18
22
EBREAK
+
MMED
1
9
l.lsource n3 n7 = 1.47e-9
20
MSTRO
17
18
-
RLGATE
LSOURCE
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
CIN
SOURCE
3
8
7
RSOURCE
RLSOURCE
res.rbreak n17 n18 = 1, tc1 = 1e-3, tc2 = -7e-7
res.rdrain n50 n16 = 1e-3, tc1 = 1.2e-2, tc2 = 3.0e-5
res.rgate n9 n20 = 2.69
S1A
12
S2A
RBREAK
15
13
8
14
13
17
18
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 45.8
res.rlsource n3 n7 = 14.7
res.rslc1 n5 n51= 1e-6, tc1 = 1e-3, tc2 =1e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 3.5e-3, tc1 = 1e-3, tc2 =1e-6
res.rvtemp n18 n19 = 1, tc1 = -1.8e-3, tc2 = 1e-6
res.rvthres n22 n8 = 1, tc1 = -2.6e-3, tc2 = -7.5e-6
RVTEMP
19
S1B
S2B
13
CB
CA
IT
14
-
+
+
VBAT
6
8
5
8
EGS
EDS
+
-
-
8
22
RVTHRES
spe.ebreak n11 n7 n17 n18 = 35.8
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e-6/275))** 5))
}
}
©2003 Fairchild Semiconductor Corporation
ISL9N306AD3 / ISL9N306AD3ST Rev. B2
SPICE Thermal Model
JUNCTION
th
REV May 2001
ISL9N306AT
CTHERM1 th 6 2.7e-4
CTHERM2 6 5 3.9e-3
CTHERM3 5 4 4.2e-3
CTHERM4 4 3 4.8e-3
CTHERM5 3 2 1.9e-2
CTHERM6 2 tl 5.9e-2
RTHERM1
RTHERM2
RTHERM3
RTHERM4
RTHERM5
RTHERM6
CTHERM1
6
RTHERM1 th 6 1.0e-3
RTHERM2 6 5 4.8e-3
RTHERM3 5 4 4.5e-2
RTHERM4 4 3 2.6e-1
RTHERM5 3 2 3.1e-1
RTHERM6 2 tl 3.4e-1
CTHERM2
CTHERM3
CTHERM4
CTHERM5
CTHERM6
5
SABER Thermal Model
SABER thermal model ISL9N306AT
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 = 2.7e-4
ctherm.ctherm2 6 5 = 3.9e-3
ctherm.ctherm3 5 4 = 4.2e-3
ctherm.ctherm4 4 3 = 4.8e-3
ctherm.ctherm5 3 2 = 1.9e-2
ctherm.ctherm6 2 tl = 5.9e-2
4
3
2
rtherm.rtherm1 th 6 = 1.0e-3
rtherm.rtherm2 6 5 = 4.8e-3
rtherm.rtherm3 5 4 = 4.5e-2
rtherm.rtherm4 4 3 = 2.6e-1
rtherm.rtherm5 3 2 = 3.1e-1
rtherm.rtherm6 2 tl = 3.4e-1
}
tl
CASE
©2003 Fairchild Semiconductor Corporation
ISL9N306AD3 / ISL9N306AD3ST Rev. B2
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FACT Quiet Series™ ISOPLANAR™
POP™
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®
FAST
LittleFET™
MicroFET™
MicroPak™
Power247™
PowerTrench
QFET™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
®
FASTr™
CROSSVOLT™ FRFET™
DOME™
GlobalOptoisolator™ MICROWIRE™
QS™
SyncFET™
®
EcoSPARK™
GTO™
MSX™
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RapidConnect™
SILENT SWITCHER VCX™
SMART START™
2
E CMOS™
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®
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As used herein:
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Definition of Terms
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Product Status
Definition
Advance Information
Formative or In
Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
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No Identification Needed
Obsolete
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Rev. I2
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