ML4841 [FAIRCHILD]
Variable Feedforward PFC/PWM Controller Combo; 变量前馈PFC / PWM控制器组合
| 型号： | ML4841 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Variable Feedforward PFC/PWM Controller Combo |
| 文件： | 总15页 (文件大小：130K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
www.fairchildsemi.com
ML4841
Variable Feedforward PFC/PWM Controller Combo
Features
General Description
• Internally synchronized PFC and PWM in one IC
• Low total harmonic distortion
• Reduces ripple current in the storage capacitor between
the PFC and PWM sections
• Average current, continuous mode, boost type, leading
edge PFC
• High efficiency trailing edge PWM can be configured for
current mode or voltage mode operation
• Average line voltage compensation with brown-out
control
The ML4841 is a controller for power factor corrected,
switched mode power supplies. Power Factor Correction
(PFC) allows the use of smaller, lower cost bulk capacitors,
reduces power line loading and stress on the switching FETs,
and results in a power supply that fully complies with
IEC1000-2-3 specifications. The ML4841 includes circuits
for the implementation of a leading edge, average current,
“boost” type power factor correction, and a trailing edge,
pulse width modulator (PWM).
The PFC frequency of the ML4841 is automatically set at
half that of the PWM frequency generated by the internal
oscillator. This technique allows the user to design with
smaller output components while maintaining the optimum
operating frequency for the PFC. An over-voltage compara-
tor shuts down the PFC section in the event of a sudden
decrease in load. The PFC section also includes peak current
limiting and input voltage brown-out protection.
• PFC overvoltage comparator eliminates output
“runaway” due to load removal
• Current fed multiplier for improved noise immunity
• Overvoltage protection, UVLO, and soft start
Block Diagram
16
1
13
POWER FACTOR CORRECTOR
V
CC
IEAO
VEAO
V
CCZ
13.5V
OVP
+
V
V
REF
VEA
FB
7.5V
REFERENCE
IEA
14
12
3.5kΩ
15
-
-
2.7V
-1V
-
+
-
2.5V
AC
+
+
S
Q
I
2
4
3
8
+
-
8V
GAIN
MODULATOR
V
R
S
Q
Q
RMS
PFC OUT
3.5kΩ
PFC I
I
LIMIT
SENSE
RAMP 1
R
Q
R C
T
T
OSCILLATOR
÷2
7
9
RAMP 2
DUTY CYCLE
LIMIT
8V
-
V
1.25V
DC
6
5
+
PWM OUT
V
S
R
Q
Q
CC
11
-
V
OK
IN
V
-
50µA
FB
SS
+
+
-
2.5V
+
1V
DC I
LIMIT
V
8V
UVLO
CCZ
PULSE WIDTH MODULATOR
REV. 1.0.3 6/13/01
ML4841
PRODUCT SPECIFICATION
Pin Configuration
ML4841
16-Pin PDIP (P16)
IEAO
1
2
3
4
5
6
7
8
16 VEAO
I
15
14
13
V
V
V
AC
FB
I
SENSE
REF
CC
V
RMS
SS
12 PFC OUT
11 PWM OUT
10 GND
V
DC
R /C
T
T
RAMP 1
9
RAMP 2
TOP VIEW
Pin Description
PIN
1
NAME
FUNCTION
IEAO
PFC transconductance current error amplifier output
PFC gain control reference input
2
I
AC
3
I
Current sense input to the PFC current limit comparator
Input for PFC RMS line voltage compensation
Connection point for the PWM soft start capacitor
PWM voltage feedback input
SENSE
4
V
RMS
5
SS
6
V
DC
7
R C
Connection for oscillator frequency setting components
PFC ramp input
T T
8
RAMP 1
RAMP 2
GND
9
PWM ramp current sense input
10
11
12
13
14
15
16
Ground
PWM OUT
PFC OUT
PWM driver output
PFC driver output
V
Positive supply (connected to an internal shunt regulator).
Buffered output for the internal 7.5V reference
PFC transconductance voltage error amplifier input
PFC transconductance voltage error amplifier output
CC
V
REF
V
FB
VEAO
2
REV. 1.0.3 6/13/01
PRODUCT SPECIFICATION
ML4841
Absolute Maximum Ratings
Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum
ratings are stress ratings only and functional device operation is not implied.
Parameter
Min.
Max.
55
Units
mA
V
V
Shunt Regulator Current
CC
I
Voltage
-3
5
SENSE
Voltage on Any Other Pin
GND - 0.3
V
CCZ
+ 0.3
V
I
I
20
mA
mA
mA
mA
mJ
°C
REF
Input Current
10
AC
Peak PFC OUT Current, Source or Sink
Peak PWM OUT Current, Source or Sink
PFC OUT, PWM OUT Energy Per Cycle
Junction Temperature
500
500
1.5
150
150
260
Storage Temperature Range
–65
°C
Lead Temperature (Soldering, 10 sec)
°C
Thermal Resistance (θ
)
JA
Plastic DIP
80
°C/W
Operating Conditions
Temperature Range
Parameter
Min.
Max.
Units
ML4841CP
0
70
°C
Electrical Characteristics
Unless otherwise specified, I
= 25mA, R = 23kΩ, R
= 28.7kΩ, C = 400pF, C
RAMP1
= 270pF, T =
CC
T
RAMP1
T
A
Operating Temperature Range (Note 1)
Symbol Parameter
Voltage Error Amplifier
Input Voltage Range
Conditions
Min.
Typ. Max. Units
0
7
V
Ω
Transconductance
Feedback Reference Voltage
Input Bias Current
Output High Voltage
Output Low Voltage
Source Current
V
= V , VEAO = 3.75V
INV
40
2.4
70
2.5
-0.5
6.7
0.65
-90
90
100
2.6
-1.0
µ
NON INV
V
Note 2
µA
V
6.0
1.0
V
∆V = 0.5V, V
IN
= 6V
-40
40
60
60
µA
µA
dB
dB
OUT
Sink Current
∆V = 0.5V, V
IN
= 1.5V
OUT
Open Loop Gain
PSRR
75
V
- 3V < V
CC
< V
CCZ
- 0.5V
75
CCZ
Current Error Amplifier
Input Voltage Range
Transconductance
Input Offset Voltage
-1.5
130
2
V
µ
Ω
V
= V , VEAO = 3.75V
INV
195
3
310
15
NON INV
mV
REV. 1.0.3 6/13/01
3
ML4841
PRODUCT SPECIFICATION
Electrical Characteristics (continued)
Unless otherwise specified, I
= 25mA, R = 23kΩ, R
= 28.7kΩ, C = 400pF, C
RAMP1
= 270pF, T =
A
CC
T
RAMP1
T
Operating Temperature Range (Note 1)
Symbol
Parameter
Input Bias Current
Output High Voltage
Output Low Voltage
Source Current
Sink Current
Conditions
Min.
Typ. Max. Units
-0.5
6.7
0.65
-90
90
-1.0
µA
V
6.0
1.0
V
∆V = 0.5V, V
IN
= 6V
-40
40
60
60
µA
µA
dB
dB
OUT
∆V = 0.5V, V
IN
= 1.5V
OUT
Open Loop Gain
PSRR
75
V
- 3V < V
CC
< V
CCZ
- 0.5V
75
CCZ
OVP Comparator
Threshold Voltage
Hysteresis
Comparator
2.6
70
2.7
95
2.8
V
125
mV
PFC I
LIMIT
Threshold Voltage
-0.8
100
-1.0
190
-1.15
300
V
∆(PFC I
V
- Gain
mV
LIMIT TH
Modulator Output)
Delay to Output
Comparator
150
ns
DC I
LIMIT
Threshold Voltage
Input Bias Current
Delay to Output
0.9
1.0
0.3
1.1
1
V
µA
ns
150
300
V
OK Comparator
IN
Threshold Voltage
Hysteresis
Gain Modulator
Gain (Note 3)
2.4
0.8
2.5
1.0
2.6
1.2
V
V
I
I
I
I
= 100µA, V
= V = 0V
FB
0.35
1.15
0.52
0.50
1.65
0.74
0.20
10
0.65
2.15
0.96
0.26
AC
AC
AC
AC
RMS
= 50µA, V
= 50µA, V
= 1.2V, V = 0V
FB
RMS
RMS
= 1.8V, V = 0V
FB
= 100µA, V
= 3.3V, V = 0V 0.14
FB
RMS
Bandwidth
IAC = 100µA
MHz
V
Output Voltage
I
= 250µA, V
= 0V
= 1.15V,
0.74
188
0.82
0.90
212
AC
RMS
V
FB
Oscillator
Initial Accuracy
Voltage Stability
T = 25°C
200
1
kHz
%
A
V
- 3V < V
CC
< V - 0.5V
CCZ
CCZ
Temperature Stability
Total Variation
2
%
Line, Temp
PFC Only
182
218
9.5
kHz
V
Ramp Valley to Peak Voltage
Dead Time
2.5
400
7.5
260
4.5
ns
C Discharge Current
T
V = 0V, V
RAMP 2 RAMP 1
= 2.5V
mA
4
REV. 1.0.3 6/13/01
PRODUCT SPECIFICATION
ML4841
Electrical Characteristics (continued)
Unless otherwise specified, I
= 25mA, R = 23kΩ, R
= 28.7kΩ, C = 400pF, C
RAMP1
= 270pF, T =
CC
T
RAMP1
T
A
Operating Temperature Range (Note 1)
Symbol
Parameter
Conditions
Min.
Typ. Max. Units
Reference
Output Voltage
T = 25°C, I(V
) = 1mA
< V - 0.5V
7.4
7.5
2
7.6
10
15
V
mV
mV
%
A
REF
Line Regulation
V
CCZ
- 3V < V
CC CCZ
Load Regulation
Temperature Stability
Total Variation
1mA < I(V ) < 20mA
REF
2
0.4
Line, Load, Temp
T = 125°C, 1000 Hours
7.25
90
7.65
25
V
Long Term Stability
5
mV
J
PFC
Minimum Duty Cycle
Maximum Duty Cycle
Output Low Voltage
V
V
> 6.7V
< 1.2V
0
%
%
V
IEAO
95
0.4
0.7
0.8
10.5
10
IEAO
I
I
I
I
I
= -20mA
= -100mA
= 10mA, V
= 20mA
0.8
2.0
1.5
OUT
OUT
OUT
OUT
OUT
V
= 8V
V
CC
Output High Voltage
Rise/Fall Time
10
V
= 100mA
9.5
V
C = 1000pF
L
50
ns
PWM
DC
Duty Cycle Range
Output Low Voltage
0-44
0-47
0.4
0.7
0.8
10.5
10
0-50
0.8
%
V
V
I
I
I
I
I
= -20mA
= -100mA
= 10mA, V
= 20mA
OL
OUT
OUT
OUT
OUT
OUT
2.0
V
= 8V
1.5
V
CC
V
Output High Voltage
Rise/Fall Time
10
V
OH
= 100mA
9.5
V
C = 1000pF
50
ns
L
Supply
V
Shunt Regulator Voltage
12.8
12.4
13.5
100
14.2
200
14.6
1.0
V
mV
V
CCZ
V
V
Load Regulation
Total Variation
25mA < I < 55mA
CC
CCZ
CCZ
Load, Temp
Start-up Current
V
= 11.2V, C = 0
0.7
17
mA
mA
V
CC
CC
L
Operating Current
V
< V
CCZ
- 0.5V, C = 0
21
L
Undervoltage Lockout
Threshold
V
- V
- V
-
CCZ
1.0
CCZ
0.7
CCZ
0.4
Undervoltage Lockout
Hysteresis
2.7
3.0
3.3
V
Notes
1. Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.
2. Includes all bias currents to other circuits connected to the V pin.
FB
x (VEAO - 1.5V) .
-1
3. Gain = K x 5.3V; K = (I
- I
) x I
AC
GAINMOD OFFSET
REV. 1.0.3 6/13/01
5
ML4841
PRODUCT SPECIFICATION
Typical Performance Characteristics
250
250
200
150
100
50
200
150
100
50
0
0
-500
0
1
2
3
4
5
0
500
V
(V)
IEA Input Voltage (mV)
FB
Voltage Error Amplifier (VEA) Transconductance (g )
m
Current Error Amplifier (IEA)Transconductance (g )
m
400
300
200
100
0
0
1
2
3
4
5
V
(mV)
RMS
Variable Gain Control Transfer Characteristic
16
1
13
V
IEAO
VEAO
VEA
CC
V
CCZ
13.5V
OVP
+
V
V
REF
FB
7.5V
IEA
14
12
3.5kΩ
15
-
REFERENCE
-
2.7V
-1V
-
+
-
2.5V
AC
+
+
S
Q
I
2
4
3
8
7
+
-
8V
GAIN
MODULATOR
V
R
S
Q
RMS
PFC OUT
3.5kΩ
PFC I
I
Q
Q
LIMIT
SENSE
RAMP 1
R
R C
T
T
OSCILLATOR
÷2
V
UVLO
CCZ
Figure 1. PFC Section Block Diagram.
6
REV. 1.0.3 6/13/01
PRODUCT SPECIFICATION
ML4841
the output voltage of the boost converter must be set higher
than the peak value of the line voltage. A commonly used
value is 385VDC, to allow for a high line of 270VAC.
The other condition is that the current which the converter is
allowed to draw from the line at any given instant must be
proportional to the line voltage. The first of these require-
ments is satisfied by establishing a suitable voltage control
loop for the converter, which in turn drives a current error
amplifier and switching output driver. The second require-
ment is met by using the rectified AC line voltage to modu-
late the output of the voltage control loop. Such modulation
causes the current error amplifier to command a power stage
current which varies directly with the input voltage. In order
to prevent ripple which will necessarily appear at the output
of the boost circuit (typically about 10VAC on a 385V DC
level) from introducing distortion back through the voltage
error amplifier, the bandwidth of the voltage loop is deliber-
ately kept low. A final refinement is to adjust the overall gain
of the PFC such to be proportional to 1/VIN2, which linear-
izes the transfer function of the system as the AC input volt-
age varies.
Functional Description
The ML4841 consists of an average current controlled,
continuous boost Power Factor Corrector (PFC) front end
and a synchronized Pulse Width Modulator (PWM) back
end. The PWM section uses current mode control. The PWM
stage uses conventional trailing-edge duty cycle modulation,
while the PFC uses leading-edge modulation. This patented
leading/trailing edge modulation technique results in a
higher useable PFC error amplifier bandwidth, and can
significantly reduce the size of the PFC DC buss capacitor.
The synchronization of the PWM with the PFC simplifies the
PWM compensation due to the controlled ripple on the PFC
output capacitor (the PWM input capacitor). The PWM
section of the ML4841 runs at twice the frequency of the
PFC, which allows the use of smaller PWM output magnet-
ics and filter capacitors while holding down the losses in the
PFC stage power components.
In addition to power factor correction, a number of protec-
tion features have been built into the ML4841. These include
soft-start, PFC over-voltage protection, peak current limit-
ing, brown-out protection, duty cycle limit, and under-
voltage lockout.
Since the boost converter topology in the ML4841 PFC is of
the current-averaging type, no slope compensation is
required.
Power Factor Correction
PFC Section
Power factor correction makes a non-linear load look like a
resistive load to the AC line. For a resistor, the current drawn
from the line is in phase with and proportional to the line
voltage, so the power factor is unity (one). A common class
of non-linear load is the input of a most power supplies,
which use a bridge rectifier and capacitive input filter fed
from the line. The peak-charging effect which occurs on the
input filter capacitor in such a supply causes brief high-
amplitude pulses of current to flow from the power line,
rather than a sinusoidal current in phase with the line volt-
age. Such a supply presents a power factor to the line of less
than one (another way to state this is that it causes significant
current harmonics to appear at its input). If the input current
drawn by such a supply (or any other non-linear load) can be
made to follow the input voltage in instantaneous amplitude,
it will appear resistive to the AC line and a unity power factor
will be achieved.
Gain Modulator
Figure 1 shows a block diagram of the PFC section of the
ML4841. The gain modulator is the heart of the PFC, as it is
this circuit block which controls the response of the current
loop to line voltage waveform and frequency, rms line volt-
age, and PFC output voltage. There are three inputs to the
gain modulator. These are:
1. A current representing the instantaneous input voltage
(amplitude and waveshape) to the PFC. The rectified
AC input sine wave is converted to a proportional
current via a resistor and is then fed into the gain
modulator at IAC. Sampling current in this way
minimizes ground noise, as is required in high power
switching power conversion environments. The gain
modulator responds linearly to this current.
2. A voltage proportional to the long-term rms AC line
voltage, derived from the rectified line voltage after
scaling and filtering. This signal is presented to the gain
modulator at VRMS. The gain modulator’s output is
inversely proportional to VRMS2 (except at unusually low
values of VRMS where special gain contouring takes over
to limit power dissipation of the circuit components
under heavy brownout conditions). The relationship
between VRMS and gain is designated as K, and is
illustrated in the Typical Performance Characteristics.
To hold the input current draw of a device drawing power
from the AC line in phase with and proportional to the input
voltage, a way must be found to prevent that device from
loading the line except in proportion to the instantaneous line
voltage. The PFC section of the ML4841 uses a boost-mode
DC-DC converter to accomplish this. The input to the
converter is the full wave rectified AC line voltage. No
filtering is applied following the bridge rectifier, so the input
voltage to the boost converter ranges, at twice line frequency,
from zero volts to the peak value of the AC input and back to
zero. By forcing the boost converter to meet two simulta-
neous conditions, it is possible to ensure that the current
which the converter draws from the power line agrees with
the instantaneous line voltage. One of these conditions is that
3. The output of the voltage error amplifier, VEAO. The
gain modulator responds linearly to variations in this
voltage.
REV. 1.0.3 6/13/01
7
ML4841
PRODUCT SPECIFICATION
The output of the gain modulator is a current signal, in
the form of a full wave rectified sinusoid at twice the line
frequency. This current is applied to the virtual-ground
(negative) input of the current error amplifier. In this way the
gain modulator forms the reference for the current error
loop, and ultimately controls the instantaneous current draw
of the PFC from the power line. The general form for the
output of the gain modulator is:
V
REF
PFC
OUTPUT
16
1
IEAO
VEAO
VEA
V
FB
IAC × VEAO
IEA
15
-
--------------------------------
IGAINMOD
≅
× 1V
2
-
VRMS
+
+
-
2.5V
AC
+
I
2
4
3
More exactly, the output current of the gain modulator is
given by:
GAIN
MODULATOR
V
RMS
I
SENSE
(1)
IGAINMOD ≅ K × (VEAO – 1.5V) × IAC
-1
where K is in units of V .
Figure 2. Compensation Network Connections for the
Voltage and Current Error Amplifiers
Note that the output current of the gain modulator is limited
Cycle-By-Cycle Current Limiter
to ≅ 200µA.
The ISENSE pin, as well as being a part of the current feed-
back loop, is a direct input to the cycle-by-cycle current
limiter for the PFC section. Should the input voltage at this
pin ever be more negative than -1V, the output of the PFC
will be disabled until the protection flip-flop is reset by the
clock pulse at the start of the next PFC power cycle.
Current Error Amplifier
The current error amplifier’s output controls the PFC duty
cycle to keep the current through the boost inductor a linear
function of the line voltage. At the inverting input to the
current error amplifier, the output current of the gain modu-
lator is summed with a current which results from a negative
Overvoltage Protection
voltage being impressed upon the I
pin (current into
SENSE
The OVP comparator serves to protect the power circuit
from being subjected to excessive voltages if the load should
suddenly change. A resistor divider from the high voltage
I
≅ V
/3.5kΩ). The negative voltage on I
SENSE
SENSE SENSE
represents the sum of all currents flowing in the PFC circuit,
and is typically derived from a current sense resistor in series
with the negative terminal of the input bridge rectifier. In
higher power applications, two current transformers are
DC output of the PFC is fed to V . When the voltage on
FB
VFB exceeds 2.7V, the PFC output driver is shut down.
The PWM section will continue to operate. The OVP
comparator has 125mV of hysteresis, and the PFC will not
restart until the voltage at VFB drops below 2.58V. The VFB
should be set at a level where the active and passive external
power components and the ML4841 are within their safe
operating voltages, but not so low as to interfere with the
boost voltage regulation loop.
sometimes used, one to monitor the I of the boost
D
MOSFET(s) and one to monitor the I of the boost diode.
F
As stated above, the inverting input of the current error
amplifier is a virtual ground. Given this fact, and the
arrangement of the duty cycle modulator polarities internal
to the PFC, an increase in positive current from the gain
modulator will cause the output stage to increase its duty
cycle until the voltage on I
cancel this increased current. Similarly, if the gain modula-
tor’s output decreases, the output duty cycle will decrease, to
is adequately negative to
SENSE
Error Amplifier Compensation
The PWM loading of the PFC can be modeled as a negative
resistor; an increase in input voltage to the PWM causes a
decrease in the input current. This response dictates the
proper compensation of the two transconductance error
amplifiers. Figure 2 shows the types of compensation
networks most commonly used for the voltage and current
error amplifiers, along with their respective return points.
The current loop compensation is returned to VREF to
produce a soft-start characteristic on the PFC: as the
reference voltage comes up from zero volts, it creates a
differentiated voltage on IEAO which prevents the PFC from
immediately demanding a full duty cycle on its boost
converter.
achieve a less negative voltage on the I
pin.
SENSE
There is a modest degree of gain contouring applied to the
transfer characteristic of the current error amplifier, to
increase its speed of response to current-loop perturbations.
However, the boost inductor will usually be the dominant
factor in overall current loop response. Therefore, this
contouring is significantly less marked than that of the
voltage error amplifier. This is illustrated in the Typical
Performance Characteristics.
8
REV. 1.0.3 6/13/01
PRODUCT SPECIFICATION
ML4841
There are two major concerns when compensating the
voltage loop error amplifier; stability and transient response.
Optimizing interaction between transient response and
stability requires that the error amplifier’s open-loop cross-
over frequency should be 1/2 that of the line frequency, or
23Hz for a 47Hz line (lowest anticipated international power
frequency). The gain vs. input voltage of the ML4841’s
voltage error amplifier has a specially shaped nonlinearity
such that under steady-state operating conditions the
transconductance of the error amplifier is at a local
EXAMPLE:
For the application circuit shown in the data sheet, with the
oscillator running at:
1
fOSC = 200kHz =
---------------
tRAMP
tRAMP = 0.51 × RT × CT = 5 × 10–6
Solving for R x C yields 1 x 10-5. Selecting standard com-
ponents values, C = 390pF, and R = 24.9kΩ.
T
T
T
T
minimum. Rapid perturbations in line or load conditions
will cause the input to the voltage error amplifier (V ) to
FB
RAMP 1
deviate from its 2.5V (nominal) value. If this happens, the
transconductance of the voltage error amplifier will increase
significantly, as shown in the Typical Performance Charac-
teristics. This increases the gain-bandwidth product of the
voltage loop, resulting in a much more rapid voltage loop
response to such perturbations than would occur with a
conventional linear gain characteristic.
The ramp voltage on this pin serves as a reference to which
the PFC’s current error amp output is compared in order to
set the duty cycle of the PFC switch. The external ramp volt-
age is derived from a RC network similar to the oscillator’s.
The PWM’s oscillator sends a synchronous pulse every other
cycle to reset this ramp.
The ramp voltage should be limited to no more than the out-
put high voltage (6V) of the current error amplifier. The tim-
ing resistor value should be selected such that the capacitor
will not charge past this point before being reset. In order to
ensure the linearity of the PFC loop’s transfer function and
improve noise immunity, the charging resistor should be
The current amplifier compensation is similar to that of the
voltage error amplifier with the exception of the choice of
crossover frequency. The crossover frequency of the current
amplifier should be at least 10 times that of the voltage
amplifier, to prevent interaction with the voltage loop. It
should also be limited to less than 1/6th that of the switching
frequency, e.g. 16.7kHz for a 100kHz switching frequency.
connected to the 13.5V V rather than the 7.5V reference.
CC
This will keep the charging voltage across the timing cap in
the "linear" region of the charging curve.
For more information on compensating the current and volt-
age control loops, see Application Notes 33 and 34. Appli-
cation Note 16 also contains valuable information for the
design of this class of PFC.
The component value selection is similar to oscillator RC
component selection.
1
(6)
fOSC = --------------------------------------------------------------
t
CHARGE + tDISCHARGE
Oscillator (R /C )
T
T
The oscillator frequency is determined by the values Of R
T
and C , which determine the ramp and off-time of the
oscillator output clock:
T
The charge time of Ramp 1 is derived from the following
equations:
1
fOSC = ------------------------------------------------------
(2)
2
fOSC
t
RAMP + tDISCHARGE
tCHARGE = ------------
(7)
(8)
The ramp-charge time of the oscillator is derived from the
following equation:
V
CC – Ramp Valley
tCHARGE = CT × RT × In --------------------------------------------------
V
CC – Ramp Peak
V
REF – 1.25
(3)
-------------------------------
tRAMP = CT × RT × In
V
REF – 3.75
At V = 13.5V and assuming Ramp Peak = 5V to allow for
CC
component tolerances:
at V
REF
= 7.5V:
tCHARGE = 0.463 × RT × CT
(9)
tRAMP = CT × RT × 0.51
The capacitor value should remain small to keep the dis-
charge energy and the resulting discharge current through the
part small. A good value to use is the same value used in the
The discharge time of the oscillator may be determined
using:
PWM timing circuit (C ).
T
2.5V
5.1mA
(4)
(5)
-----------------
× CT = 490 × CT
tDISCHARGE
=
For the application circuit shown in the data sheet, using a
200kHz PWM and 390pF timing cap yields R :
T
The deadtime is so small (t
RAMP
operating frequency can typically be approximated by:
>> t
) that the
DEADTIME
1 × 10–5
(10)
RT = ------------------------------------------------------- = 56.2kΩ
(0.463)(390 × 10–12
)
1
fOSC = ---------------
tRAMP
REV. 1.0.3 6/13/01
9
ML4841
PRODUCT SPECIFICATION
Solving for the minimum value of C
:
SS
PWM SECTION
Pulse Width Modulator
50µA
---------------
1.25V
CSS = 5ms ×
= 200nF
The PWM section of the ML4841 is straightforward, but
there are several points which should be noted. Foremost
among these is its inherent synchronization to the PFC
section of the device, to which it also provides its basic
timing. The PWM operates in current-mode. In applications
utilizing current mode control, the PWM ramp (RAMP 2) is
usually derived directly from a current sensing resistor or
current transformer in the primary of the output stage, and is
thereby representative of the current flowing in the con-
V
BIAS
verter’s output stage. The DC I
comparator provides
LIMIT
V
CC
cycle-by-cycle current limiting and is connected to RAMP 2
internally. If the current sense signal exceeds the 1V thresh-
old, the PWM switch is disabled until the protection flip-flop
is rest by the clock pulse at the start of the next PWM power
cycle.
10nF
ceramic
1µF
ceramic
ML4841
GND
PWM Current Limit
The DC I
comparator is a cycle-by-cycle current lim-
LIMIT
Figure 3. External Component Connections to V
CC
iter for the PWM section. Should the input voltage at this pin
ever exceed 1V, the output of the PWM will be disabled until
the output flip-flop is reset by the clock pulse at the start of
the next PWM power cycle.
Generating V
CC
The ML4841 is a current-fed part. It has an internal shunt
voltage regulator, which is designed to regulate the voltage
internal to the part at 13.5V. This allows a low power dissi-
pation while at the same time delivering 10V of gate drive at
the PWM OUT and PFC OUT outputs. It is important to
limit the current through the part to avoid overheating or
destroying it. This can be easily done with a single resistor in
series with the Vcc pin, returned to a bias supply of typically
18V to 20V. The resistor’s value must be chosen to meet the
operating current requirement of the ML4841 itself (19mA
max) plus the current required by the two gate driver outputs.
V
OK Comparator
IN
IN
The V OK comparator monitors the DC output of the PFC
and inhibits the PWM if this voltage on V is less than its
FB
nominal 2.5V. Once this voltage reaches 2.5V, which
corresponds to the PFC output capacitor being charged to its
rated boost voltage, the soft-start commences.
PWM Control (RAMP 2)
The PWM section utilizes current mode control. RAMP 2
is generally used as the sampling point for a voltage
representing the current in the primary of the PWM’s output
transformer, derived either by a current sensing resistor or a
current transformer.
EXAMPLE:
With a V
of 20V, a V limit of 14.6V (max) and
CC
BIAS
driving a total gate charge of 100nC at 100kHz (1 IRF840
MOSFET and 2 IRF830 MOSFETs), the gate driver current
required is:
Soft Start
Start-up of the PWM is controlled by the selection of the
external capacitor at SS. A current source of 50µA supplies
the charging current for the capacitor, and start-up of the
PWM begins at 1.25V. Start-up delay can be programmed by
the following equation:
(12)
(13)
IGATEDRIVE = (100kHz × 45nC) + (200kHz × 52nC) =15mA
20V – 14.6V
RBIAS = -------------------------------------- = 160Ω
19mA + 15mA
50µA
To check the maximum dissipation in the ML4841, check the
---------------
×
CSS = tDELAY
(11)
1.25V
current at the minimum V (12.4V):
CC
20V – 12.4V
ICC = -------------------------------- = 47.5mA
160Ω
where C is the required soft start capacitance, and t
SS
is the desired start-up delay.
(14)
DELAY
It is important that the time constant of the PWM soft-start
allows the PFC time to generate sufficient output power for
the PWM section. The PWM start-up delay should be at least
5ms.
The maximum allowable I is 55mA, so this is an accept-
CC
able design.
10
REV. 1.0.3 6/13/01
PRODUCT SPECIFICATION
ML4841
The ML4841 should be locally bypassed with a 10nF and a
1µF ceramic capacitor. In most applications, an electrolytic
capacitor of between 100µF and 330µF is also required
across the part, both for filtering and as part of the start-up
bootstrap circuitry.
In the case of leading edge modulation, the switch is turned
OFF right at the leading edge of the system clock. When the
modulating ramp reaches the level of the error amplifier
output voltage, the switch will be turned ON. The effective
duty-cycle of the leading edge modulation is determined
during the OFF time of the switch. Figure 5 shows a leading
edge control scheme.
Leading/Trailing Modulation
Conventional Pulse Width Modulation (PWM) techniques
employ trailing edge modulation in which the switch will
turn on right after the trailing edge of the system clock.
The error amplifier output voltage is then compared with the
modulating ramp. When the modulating ramp reaches the
level of the error amplifier output voltage, the switch will be
turned OFF. When the switch is ON, the inductor current will
ramp up. The effective duty cycle of the trailing edge modu-
lation is determined during the ON time of the switch. Figure
4 shows a typical trailing edge control scheme.
One of the advantages of this control teccnique is that it
requires only one system clock. Switch 1 (SW1) turns off
and switch 2 (SW2) turns on at the same instant to minimize
the momentary “no-load” period, thus lowering ripple volt-
age generated by the switching action. With such synchro-
nized switching, the ripple voltage of the first stage is
reduced. Calculation and evaluation have shown that the
120Hz component of the PFC’s output ripple voltage can be
reduced by as much as 30% using this method.
SW2
SW1
I2
I3
I4
L1
I1
+
VIN
RL
DC
C1
RAMP
VEAO
REF
U3
EA
+
–
DFF
+
–
R
D
RAMP
CLK
Q
TIME
U1
U2
OSC
U4
VSW1
Q
CLK
TIME
Figure 4. Typical Trailing Edge Control Scheme
REV. 1.0.3 6/13/01
11
ML4841
PRODUCT SPECIFICATION
SW2
SW1
I2
I3
I4
L1
I1
+
VIN
RL
DC
C1
RAMP
U3
EA
VEAO
+
–
REF
VEAO
DFF
CMP
+
TIME
R
D
RAMP
CLK
Q
–
U1
OSC
U4
U2
VSW1
Q
CLK
TIME
Figure 5. Leading/Trailing Edge Control Scheme
12
REV. 1.0.3 6/13/01
PRODUCT SPECIFICATION
ML4841
Typical Applications
Figure 6 is the application circuit for a complete 100W
power factor corrected power supply, designed using the
methods and general topology suggested inApplication Note
33.
AC INPUT
85 TO 265VAC
F1
3.15A
C1
680nF
L1
3.1mH
D1
8A, 600V
Q2
IRF830
Q1
IRF840
R17
33Ω
C4
10nF
C5
100µF
R2A
453kΩ
C25
100nF
D5
600V
BR1
4A, 600V
T1
R1A
499kΩ
D7
15V
R30
4.7kΩ
L2
D11
R27
22kΩ
33µH
MBR2545CT
T2
R21
22Ω
R15
3Ω
12VDC
RTN
C24
1µF
R2B
453kΩ
D6
600V
C21
1800µF
C20
1µF
R28
160Ω
R24
1.2kΩ
C3
100nF
D3
50V
R1B
499kΩ
R14
33Ω
C22
4.7µF
C30
330µF
Q3
IRF830
C12
10µF
R23
1.5kΩ
R18
220Ω
D12
1A, 50V
R22
8.66kΩ
R7A
178kΩ
R3
75kΩ
D13
1A, 50V
R20
1.1Ω
C23
100nF
C7
220pF
R26
10kΩ
R19
220Ω
56.2kΩ
R25
2.26kΩ
R7B
178kΩ
C6
1nF
R12
27kΩ
TL431
C2
R4
470nF
13kΩ
IEAO
VEAO
C9
8.2nF
I
I
V
FB
AC
SENSE
C31
R11
1nF 750kΩ
V
R8
2.37kΩ
REF
C13
100nF
C14
1µF
C8
82nF
R5
300mΩ
1W
V
V
CC
RMS
SS
C15
10nF
C16
1µF
PFC OUT
PWM OUT
GND
C19
1µF
V
DC
RAMP 1
D8
1A, 20V
D10
1A, 20V
RAMP 2DC I
ML4841
LIMIT
390pF
C17
220pF
C18
390pF
R6
24.9kΩ
R10
6.2kΩ
C11
10nF
Figure 6. 100W Power Factor Corrected Power Supply.
REV. 1.0.3 6/13/01
13
ML4841
PRODUCT SPECIFICATION
Mechanical Dimensions inches (millimeters)
Package: P16
16-Pin PDIP
0.740 - 0.760
(18.79 - 19.31)
16
0.240 - 0.260 0.295 - 0.325
(6.09 - 6.61) (7.49 - 8.26)
PIN 1 ID
1
0.02 MIN
(0.50 MIN)
(4 PLACES)
0.055 - 0.065
(1.40 - 1.65)
0.100 BSC
(2.54 BSC)
0.015 MIN
(0.38 MIN)
0.170 MAX
(4.32 MAX)
SEATING PLANE
0.008 - 0.012
(0.20 - 0.31)
0.016 - 0.022
(0.40 - 0.56)
0° - 15°
0.125 MIN
(3.18 MIN)
14
REV. 1.0.3 6/13/01
ML4841
PRODUCT SPECIFICATION
Ordering Information
Part Number
Temperature Range
Package
16-Pin Plastic DIP (P16)
ML4841CP
0°C to 70°C
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO
ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME
ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
6/13/01 0.0m 003
Stock#DS30004841
© 2001 Fairchild Semiconductor Corporation
相关型号：
ML4841CP_NL
Power Factor Controller With Post Regulator, Current-mode, 0.5A, PDIP16, LEAD FREE, PLASTIC, DIP-16
FAIRCHILD
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