ML65244CKX [FAIRCHILD]
Bus Driver, 2-Func, 4-Bit, True Output, PDSO20;
| 型号： | ML65244CKX |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Bus Driver, 2-Func, 4-Bit, True Output, PDSO20 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总8页 (文件大小：118K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
August 1996
ML65244/ML65L244*
High Speed Dual Quad Buffer/Line Drivers
GENERAL DESCRIPTION
FEATURES
The ML65244 and ML65L244 are non-inverting dual quad
buffer/line drivers. The high operating frequency (50MHz
driving a 50pF load) and low propagation delay
(ML65244 – 1.7ns, ML65L244 – 2ns) make them ideal for
very high speed applications such as processor bus
buffering and cache and main memory control.
■ Low propagation delay — 1.7ns ML65244
2.0ns ML65L244
■ Fast Dual 4-bit TTL level buffer/line driver with tri-state
capability on the output (two 4-bit sections)
■ TTL compatible input and output levels
■ Schottky diode clamps on all inputs to handle
These buffers use a unique analog implementation to
eliminate the delays inherent in traditional digital designs.
Schottky clamps reduce under and overshoot, and special
output driver circuits limit ground bounce. The ML65244
and ML65L244 conform to the pinout and functionality of
the industry standard FCT244 and are intended for
applications where propagation delay is critical to the
system design.
undershoot and overshoot
■ Onboard schottky diodes minimize noise
■ Reduced output swing of 0 – 4.1 volts
■ Ground bounce controlled outputs, typically less
than 400mV
■ Industry standard FCT244 type pinout
■ Applications include high speed cache memory, main
Note: This part was previously numbered ML6582.
memory, processor bus buffering, and graphics cards
BLOCK DIAGRAM
*This Part Is Obsolete
V
B3
11
YAO
18
BO
17
YA1
16
B1
15
YA2
14
B2
13
YA3
12
CC
20
V
CC
19
1
2G
1G
9
10
2
3
4
5
6
7
8
YB3
GND
AO
YBO
A1
YB1
A2
YB2
A3
1
ML65244/ML65L244
PIN CONFIGURATION
20-Pin SOIC, QSOP
1G
A0
1
2
20
19
18
17
16
15
14
13
12
11
V
CC
2G
YB0
A1
3
YA0
B0
4
YB1
A2
5
YA1
B1
6
YB2
A3
7
YA2
B2
8
YB3
GND
9
YA3
B3
10
TOP VIEW
PIN DESCRIPTION
FUNCTION TABLE
NAME
Ai
I/O
I
DESCRIPTION
Data Bus A
1G/2G
Ai/Bi
X
YAi/YBi
H
L
L
Z
L
YAi
Bi
O
I
Data Bus A
Data Bus B
Data Bus B
L
H
H
YBi
1G
O
I
L = Logic Low
H = Logic High
X = Don’t Care
Z = High Impedance
Output Enable for data bus A
Output Enable for data bus B
Signal Ground
2G
I
GND
I
V
CC
I
+ 5V supply
ABSOLUTE MAXIMUM RATINGS
V
............................................................................... –0.3V to 7V
CC
DC Input voltage ................................ –0.3 to V + 0.3V
CC
AC Input voltage (< 20ns)........................................ –3.0V
DC Output voltage ............................. –0.3 to V + 0.3V
CC
Output sink current (per pin) ................................ 120mA
Storage temperature ................................ –65°C to 150°C
Junction temperature .............................................. 150°C
Thermal Impedance (θ )
JA
SOIC ............................................................... 96°C/W
QSOP ............................................................ 100°C/W
2
ML65244/ML65L244
ELECTRICAL CHARACTERISTICS
Unless otherwise stated, these specifications apply for: V = 5.0 ± 5%V, T = 0°C to 70°C (Note 1).
CC
A
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
AC ELECTRICAL CHARACTERISTICS (CLOAD = 50pF, RLOAD = 500Ω)
tPLH, tPHL Propagation delay Ai to YAi, Bi to YBi (Note 2)
ML65244
1.4
1.6
10
1.7
2.0
15
ns
ns
ns
ML65L244
tOE
tOD
CIN
Output enable time
1G, 2G to YAi/YBi
Output disable time
1G, 2G to YAi/YBi
10
ns
Input capacitance
8
pF
DC ELECTRICAL CHARACTERISTICS (CLOAD = 50pF, RLOAD = ∞)
VIH
VIL
IIH
Input high voltage
Input low voltage
Input high current
Logic HIGH
2.0
V
Logic LOW
0.8
1.5
0.5
3.5
1.0
5
V
Per pin, VIN = 3V
ML65244
ML65L244
ML65244
ML65L244
0.5
0.3
2.4
0.8
mA
mA
mA
mA
µA
mA
IIL
Input low current
Per pin, VIN = 0
IHI-Z
IOS
Three-state output current VCC = 5.25V, 0 < VIN < VCC
Short circuit current
VCC = 5.25V, VO = GND
(Note 3)
–60
2.4
–225
VIC
Input clamp voltage
Output high voltage
VCC = 4.75V, IIN = 18mA
–0.7
–1.2
0.6
V
V
VOH
VCC = 4.75V, IOH = 100µA
(Notes 4 & 5)
VOL
Output low voltage
VCC = 4.75V, IOL = 25mA
(Notes 4 & 5)
V
VOFF
VIN – VOUT per buffer
VCC = 4.75V (Note 4)
ML65244
0
0
100
200
55
200
300
80
mV
mV
mA
ML65L244
ICC
Quiescent Power
Supply Current
VCC = 5.25V, Freq = 0Hz,
Inputs/outputs open
Note 1: Limits are guaranteed by 100% testing, sampling or correlation with worst case test conditions.
Note 2: One line switching, see Figure 3, tPLH, tPHL versus CL.
Note 3: Not more than one output should be shorted for more than a second.
Note 4: This is a true analog buffer. In the linear region, the output tracks the input with an offset (VOFF). For VOH, VIN = 2.7V.
VOH MIN includes VOFF. For VOL, VIN = 0V, VOL MAX includes VOFF
Note 5: See Figure 2 for IOH versus VOH and IOL versus VOL data.
t , t ≤ 4ns
R
F
3V
INPUT
1.5V
1.5V
0V
3V
t
t
PLH
PHL
OUTPUT
1.5V
1.5V
0V
3
ML65244/ML65L244
CH1 1.00V
CH2 1.00V
10.0ns
CH1 1.00V
CH2 1.00V
10.0ns
ML65244
74FCT244
Figure 1. Ground Bounce Comparison, Four Outputs Switching into 50pF Loads.
+20
220
200
180
160
140
120
100
80
0
–20
–40
–60
–80
–100
–120
–140
–160
–180
–200
60
40
20
0
2.5
3.0
3.5
4.0
0.0
0.5
1.0
1.5
2.0
2.5
V (V)
OH
V
OL
(V)
Figure 2b. Typical V
Versus I
Figure 2a. Typical V Versus I
OH
OH
OL
OL
for One Buffer Output.
for One Buffer Output.
3.0
210
150pF
190
170
150
130
110
90
50pF
2.5
2.0
1.5
1.0
0.5
0.0
100pF
75pF
ML65L244
ML65244
30pF
70
50
30
50
75
100
150
10
20
30
40
50
60
70
80
90
LOAD CAPACITANCE (pF)
FREQUENCY (MHz)
Figure 4. I Versus Frequency for Various Load
Figure 3. Propagation Delay (t , t ) Versus Load
CC
PLH PHL
Capacitances, Four Outputs Switching.
Capacitance, One Output Switching.
4
ML65244/ML65L244
line drivers, but it is not true for the ML65244 and
ML65L244. This is because their sink and source current
capability depends on the voltage difference between the
output and the input. The ML65244 can sink or source
more than 100mA to a load when the load is switching
due to the fact that during the transition, the difference
FUNCTIONAL DESCRIPTION
The ML65244 and ML65L244 are very high speed non-
inverting buffer/line drivers with three-state outputs which
are ideally suited for bus-oriented applications. They
provide a low propagation delay by using an analog
design approach (a high speed unity gain buffer), as
compared to conventional digital approaches. The
ML65244 and ML65L244 follow the pinout and
between the input and output is large. I is only
OL
significant as a DC specification, and is 25mA.
functionality of the industry standard FCT244 series of
buffer/line drivers and are intended to replace them in
designs where the propagation delay is a critical part of
the system design considerations. The ML65244 and
ML65L244 are capable of driving load capacitances
several times larger than their input capacitance. They are
configured so that the Ai inputs go to the YAi outputs, with
the A side output enable controlled by 1G. Similarly, 2G
controls the Bi inputs which go to the YBi outputs.
ARCHITECTURAL DESCRIPTION
Until now, buffer/line drivers have been implemented in
CMOS logic and made to be TTL compatible by sizing the
input devices appropriately. In order to buffer large
capacitances with CMOS logic, it is necessary to cascade
an even number of inverters, each successive inverter
larger than the preceding, eventually leading to an inverter
that will drive the required load capacitance at the
required frequency. Each inverter stage represents an
additional delay in the gating process because in order for
a single gate to switch, the input must slew more than half
of the supply voltage. The best of these CMOS buffers has
managed to drive a 50pF load capacitance with a delay of
3.2ns. Micro Linear has produced a dual quad buffer/line
driver with a delay less than 1.7ns by using a unique
circuit architecture that does not require cascaded logic
gates. The ML65244 uses a feedback technique to
produce an output that follows the input. If the output
voltage is not close to the input, then the feedback
circuitry will source or sink enough current to the load
capacitance to correct the discrepancy.
These unity gain analog buffers achieve low propagation
delays by having the output follow the input with a small
offset. The output rise and fall times will closely match
those of the input waveform. All inputs and outputs have
Schottky clamp diodes to handle undershoot or overshoot
noise suppression in unterminated applications. All
outputs have ground bounce suppression (typically
< 400mV), high drive output capability with almost
immediate response to the input signal, and low
output skew.
The I current drive capability of a buffer/line driver is
OL
often interpreted as a measure of its ability to sink current
in a dynamic sense. This may be true for CMOS buffer/
VCC
R8
Q1
Q2
R7
R3
R4
R2
R1
IN
OUT
Q4
Q6
Q5
Q7
Q3
R5
R6
GND
Figure 5. One buffer cell of the ML65244
5
ML65244/ML65L244
The basic architecture of the ML65244 is shown in Figure
5. It is implemented on a 1.5µm BiCMOS process.
However, in this particular circuit, all of the active devices
TERMINATION
R7 in Figure 5 also acts as a termination resistor. This 75Ω
resistor is in series with the output and therefore helps
suppress noise caused by transmission line effects such as
reflections from mismatched impedances. System
designers using CMOS transceivers commonly have to use
external resistors in series with each transceiver output to
suppress this noise. Systems using the ML65244 or
ML65L244 may not have to use these external resistors.
are NPNs — the fastest devices available in the process.
In this circuit, there are two paths to the output. One path
sources current to the load capacitance when the signal is
asserted, and the other path sinks current from the output
when the signal is negated.
The assertion path is the emitter follower path consisting
of the level shift transistor Q1, the output transistor Q2,
and the bias resistor R8. It sources current to the output
through the 75Ω resistor R7 which is bypassed by another
NPN (not shown) during fast input transients. The
APPLICATIONS
There are a wide variety of needs for extremely fast buffers
in high speed processor system designs like Pentium,
PowerPC, Mips, Sparc, Alpha and other RISC processors.
These applications are either in the cache memory area or
the main memory (DRAM) area. In addition, fast buffers
find applications in high speed graphics and multimedia
applications. The high capacitive loading due to
multiplexed address lines on the system bus demand
external buffers to take up the excess drive current. The
needed current to skew the transitions between rise and
fall times must be done without adding excessive
propagation delay. The ML65244 and ML65L244 are
equipped with Schottky diodes to clean up ringing from
overshoot and undershoot caused by reflections in
unterminated board traces.
negation path is a current differencing op amp connected
in a follower configuration. The active components in this
amplifier are transistors Q3–Q7. R3–R6 are bias resistors,
and R1 and R2 are the feedback resistors. The key to
understanding the operation of the current differencing op
amp is to know that the currents in transistors Q3 and Q5
are the same at all times and that the voltages at the bases
of Q4 and Q6 are roughly the same. If the output is higher
than the input, then an error current will flow through R2.
This error current will flow into the base of Q6 and be
multiplied by β squared to the collector of Q7, closing the
loop. The larger the discrepancy between the output and
input, the larger the feedback current, and the harder Q7
sinks current from the load capacitor.
A number of MOSFETs are not shown in Figure 5. These
MOSFETs are used to three-state dormant buffers. For
instance, the feedback resistors R1 and R2 were
implemented as resistive transmission gates to ensure that
disabled buffers do not load the lines they are connected
to. Similarly, there is a PMOS in series with R8 that is
normally on but shuts off for disable. Other MOSFETs
have been included to ensure that disabled buffers
consume no power.
6
ML65244/ML65L244
PHYSICAL DIMENSIONS inches (millimeters)
Package: S20
20-Pin SOIC
0.498 - 0.512
(12.65 - 13.00)
20
0.291 - 0.301 0.398 - 0.412
(7.39 - 7.65) (10.11 - 10.47)
PIN 1 ID
1
0.024 - 0.034
(0.61 - 0.86)
(4 PLACES)
0.050 BSC
(1.27 BSC)
0.095 - 0.107
(2.41 - 2.72)
0º - 8º
0.012 - 0.020
(0.30 - 0.51)
0.022 - 0.042
(0.56 - 1.07)
0.007 - 0.015
(0.18 - 0.38)
0.090 - 0.094
(2.28 - 2.39)
0.005 - 0.013
(0.13 - 0.33)
SEATING PLANE
Package: K20
20-Pin QSOP
0.338 - 0.348
(8.58 - 8.84)
20
0.150 - 0.160 0.228 - 0.244
PIN 1 ID
(3.81 - 4.06)
(5.79 - 6.20)
1
0.050 - 0.055
0.025 BSC
(0.63 BSC)
(1.27 - 1.40)
(4 PLACES)
0.060 - 0.068
(1.52 - 1.73)
0º - 8º
0.008 - 0.012
(0.20 - 0.31) SEATING PLANE
0.015 - 0.035
(0.38 - 0.89)
0.006 - 0.010
(0.15 - 0.26)
0.055 - 0.061
(1.40 - 1.55)
0.004 - 0.010
(0.10 - 0.26)
7
ML65244/ML65L244
ORDERING INFORMATION
PART NUMBER
SPEED
TEMPERATURE RANGE
PACKAGE
ML65244CK
ML65244CS
1.7ns
1.7ns
0°C to 70°C
0°C to 70°C
20-Pin QSOP (K20)
20-Pin SOIC (S20)
ML65L244CK
ML65L244CS
2.0ns
2.0ns
0°C to 70°C
0°C to 70°C
20-Pin QSOP (K20) (Obsolete)
20-Pin SOIC (S20) (Obsolete)
Intel, Pentium, PCI are registered trademarks of Intel Corporation. Mips, Alpha and Sparc are registered trademarks of Silicon Graphics, DEC and
Sun Microsystems respectively.
© Micro Linear 1997
is a registered trademark of Micro Linear Corporation
Products described in this document may be covered by one or more of the following patents, U.S.: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940;
5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; Japan: 2598946; 2619299. Other patents are pending.
Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design.
2092 Concourse Drive
Micro Linear does not assume any liability arising out of the application or use of any product described herein,
San Jose, CA 95131
Tel: 408/433-5200
Fax: 408/432-0295
neither does it convey any license under its patent right nor the rights of others. The circuits contained in this
data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to
whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility
or liability for use of any application herein. The customer is urged to consult with appropriate legal counsel
before deciding on a particular application.
DS65244-01
8
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