MM54HC4040J [FAIRCHILD]
Binary Counter, HC/UH Series, Asynchronous, Negative Edge Triggered, 12-Bit, Up Direction, CMOS, CDIP16, DIP-16;
| 型号： | MM54HC4040J |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Binary Counter, HC/UH Series, Asynchronous, Negative Edge Triggered, 12-Bit, Up Direction, CMOS, CDIP16, DIP-16 CD 逻辑集成电路 触发器 |
| 文件： | 总8页 (文件大小：189K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
April 1998
MM74HC4020 • MM74HC4040
14-Stage Binary Counter • 12-Stage Binary Counter
These devices are pin equivalent to the CD4020 and
CD4040 respectively. All inputs are protected from damage
due to static discharge by protection diodes to VCC and
ground.
General Description
The
MM54HC4020/MM74HC4020,
MM54HC4040/
MM74HC4040, are high speed binary ripple carry counters.
These counters are implemented utilizing advanced
silicon-gate CMOS technology to achieve speed perfor-
mance similar to LS-TTL logic while retaining the low power
and high noise immunity of CMOS.
Features
n Typical propagation delay: 16 ns
n Wide operating voltage range: 2–6V
n Low input current: 1 µA maximum
n Low quiescent current: 80 µA maximum (74HC Series)
n Output drive capability: 10 LS-TTL loads
The ’HC4020 is a 14 stage counter and the ’HC4040 is a
12-stage counter. Both devices are incremented on the fall-
ing edge (negative transition) of the input clock, and all their
outputs are reset to a low level by applying a logical high on
their reset input.
Connection Diagrams
Dual-In-Line Packages
’HC4020
’HC4040
DS005216-3
DS005216-1
Order Number MM54HC4020/4040 or MM74HC4020/4040
© 1998 Fairchild Semiconductor Corporation
DS005216
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Absolute Maximum Ratings (Notes 2, 1)
Operating Conditions
Min
2
Max
6
Units
Supply Voltage (VCC
DC Input Voltage (VIN
DC Output Voltage (VOUT
Clamp Diode Current (ICD
DC Output Current, per pin (IOUT
DC VCC or GND Current, per pin (ICC
)
−0.5 to +7.0V
−1.5 to VCC+1.5V
−0.5 to VCC+0.5V
Supply Voltage (VCC
DC Input or Output Voltage
(VIN, VOUT
)
V
V
)
0
VCC
)
±
±
±
)
)
20 mA
25 mA
50 mA
Operating Temp. Range (TA)
MM74HC
)
−40
−55
+85
˚C
˚C
)
MM54HC
+125
Storage Temperature Range (TSTG
Power Dissipation (PD)
(Note 3)
)
−65˚C to +150˚C
Input Rise or Fall Times
=
(tr, tf)
VCC 2.0V
1000
500
ns
ns
ns
600 mW
500 mW
=
VCC 4.5V
S.O. Package only
=
VCC 6.0V
400
Lead Temperature (TL)
(Soldering 10 seconds)
260˚C
DC Electrical Characteristics (Note 4)
=
TA 25˚C
74HC
54HC
=
=
TA −40 to 85˚C
TA −55 to
Symbol
Parameter
Conditions
VCC
Units
125˚C
Typ
Guaranteed Limits
VIH
Minimum High Level Input
Voltage
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
V
V
V
VIL
Maximum Low Level Input
Voltage (Note 5)
0.5
0.5
0.5
1.35
1.8
1.35
1.8
1.35
1.8
=
VOH
Minimum High Level Output VIN VIH or VIL
Voltage |IOUT|≤20 µA
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
=
VIN VIH or VIL
|IOUT|≤4.0 mA
|IOUT|≤5.2 mA
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
=
Maximum Low Level Output VIN VIH or VIL
VOL
Voltage
|IOUT|≤20 µA
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
=
VIN VIH or VIL
|IOUT|≤4.0 mA
|IOUT|≤5.2 mA
4.5V
6.0V
6.0V
0.2
0.2
.26
.26
0.33
0.33
0.4
0.4
V
V
=
±
±
±
IIN
Maximum Input Current
VIN VCC or
0.1
1.0
1.0
µA
GND
=
ICC
Maximum Quiescent Supply VIN VCC or
6.0V
8.0
80
160
µA
GND
=
IOUT 0 µA
Current
Note 1: Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating — plastic “N” package: −12 mW/˚C from 65˚C to 85˚C; ceramic “J” package: −12 mW/˚C from 100˚C to 125˚C.
±
Note 4: For a power supply of 5V 10% the worst case output voltages (V , and V ) occur for HC at 4.5V. Thus the 4.5V values should be used when designing
OH OL
=
with this supply. Worst case V and V occur at V
5.5V and 4.5V respectively. (The V value at 5.5V is 3.85V.) The worst case leakage current (I , I , and
IH IN CC
IH IL CC
I
) occur for CMOS at the higher voltage and so the 6.0V values should be used.
OZ
Note 5:
V
limits are currently tested at 20% of V . The above V specification (30% of V ) will be implemented no later than Q1, CY’89.
CC IL CC
IL
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2
AC Electrical Characteristics
=
=
=
= =
VCC 5V, TA 25˚C, CL 15 pF, tr tf 6 ns
Symbol
fMAX
PHL, tPLH
Parameter
Conditions Typ Guaranteed Units
Limit
Maximum Operating
Frequency
50
30
MHz
t
Maximum Propagation
Delay Clock to Q
(Note 6)
17
35
ns
tPHL
tREM
tW
Maximum Propagation
Delay Reset to any Q
Minimum Reset
16
10
10
40
20
16
ns
ns
ns
Removal Time
Minimum Pulse Width
AC Electrical Characteristics
=
=
= =
VCC 2.0V to 6.0V, CL 50 pF, tr tf 6 ns (unless otherwise specified)
=
TA 25˚C
74HC
54HC
=
=
TA −40 to 85˚C
TA −55 to
Symbol
Parameter
Conditions
VCC
Units
125˚C
Typ
Guaranteed Limits
fMAX
Maximum Operating
Frequency
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
10
40
50
80
21
18
80
18
15
72
24
20
6
30
5
24
4
20
MHz
MHz
MHz
ns
35
28
24
t
PHL, tPLH
Maximum Propagation
Delay Clock to Q1
210
42
265
53
313
63
ns
36
45
53
ns
TPHL, tPLH
Maximum Propagation
Delay Between Stages
from Qn to Qn+1
125
25
156
31
188
38
ns
ns
21
26
31
ns
tPHL
Maximum Propagation
Delay Reset to any Q
(’4020 and ’4040)
Minimum Reset
240
48
302
60
358
72
ns
ns
41
51
61
ns
tREM
100
20
126
25
149
50
ns
Removal Time
ns
16
21
25
ns
tW
Minimum Pulse Width
90
100
20
120
24
ns
16
ns
14
18
20
ns
t
TLH, tTHL
Maximum
30
10
9
75
95
110
22
ns
Output Rise
15
19
ns
and Fall Time
Maximum Input Rise and
Fall Time
13
16
19
ns
tr, tf
1000
500
400
1000
500
400
1000
500
400
ns
ns
ns
CPD
CIN
Power Dissipation
Capacitance (Note 7)
Maximum Input
Capacitance
(per package)
55
5
pF
10
10
10
pF
=
=
5V.
Note 6: Typical Propagation delay time to any output can be calculated using: t
17+12(N–1) ns; where N is the number of the output, Q , at V
CC
P
W
2
=
=
C
PD CC
Note 7:
C
determines the no load dynamic power consumption, P
C
V
f+I
V
, and the no load dynamic current consumption, I
V
f+I
.
CC
PD
D
PD CC
CC CC
S
3
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Logic Diagrams
MM54HC4020/MM74HC4020
DS005216-5
MM54HC4040/MM74HC4040
DS005216-7
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4
Timing Diagram
5
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Physical Dimensions inches (millimeters) unless otherwise noted
Order Number MM54HC4020J, MM54HC4024J, MM54HC4040J,
MM74HC4020J, MM74HC4024J, or MM74HC4040J
Package J14A
Order Number MM54HC4020J, MM54HC4024J, MM54HC4040J,
MM74HC4020J, MM74HC4024J, or MM74HC4040J
Package J16A
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6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Order Number MM74HC4020N, MM74HC4024N or MM74HC4040N
Package N14A
Order Number MM74HC4020N, MM74HC4024N or MM74HC4040N
Package N16E
7
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CONDUCTOR CORPORATION. As used herein:
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tems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, and (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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Corporation
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Europe
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
相关型号：
MM54HC4040J/883
HC/UH SERIES, ASYN NEGATIVE EDGE TRIGGERED 12-BIT UP BINARY COUNTER, CDIP16, DIP-16
NSC
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