MM54HC86J [FAIRCHILD]
XOR Gate, HC/UH Series, 4-Func, 2-Input, CMOS, CDIP14, DIP-14;
| 型号： | MM54HC86J |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | XOR Gate, HC/UH Series, 4-Func, 2-Input, CMOS, CDIP14, DIP-14 栅 CD 逻辑集成电路 石英晶振 触发器 |
| 文件： | 总6页 (文件大小：96K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
April 1998
MM74HC86
Quad 2-Input Exclusive OR Gate
General Description
Features
n Typical propagation delay: 9 ns
n Wide operating voltage range: 2–6V
n Low input current: 1 µA maximum
This EXCLUSIVE OR gate utilizes advanced silicon-gate
CMOS technology to achieve operating speeds similar to
equivalent LS-TTL gates while maintaining the low power
consumption and high noise immunity characteristic of stan-
dard CMOS integrated circuits. These gates are fully buff-
ered and have a fanout of 10 LS-TTL loads. The MM54HC/
74HC logic family is functionally as well as pin out
compatible with the standard 54LS/74LS logic family. All in-
puts are protected from damage due to static discharge by
internal diode clamps to VCC and ground.
n Low quiescent current: 20 µA maximum (74 Series)
n Output drive capability: 10 LS-TTL loads
Connection Diagram
Dual-In-Line Package
DS005305-1
Top View
Order Number MM54HC86 or MM74HC86
Truth Table
Inputs
Outputs
A
L
B
L
Y
L
L
H
L
H
H
L
H
H
B
H
=
=
A B + AB
%
Y
A
© 1998 Fairchild Semiconductor Corporation
DS005305
www.fairchildsemi.com
Absolute Maximum Ratings (Notes 2, 1)
Operating Conditions
Min
2
Max
6
Units
Supply Voltage (VCC
DC Input Voltage (VIN
DC Output Voltage (VOUT
Clamp Diode Current (IIK, IOK
DC Output Current, per pin (IOUT
DC VCC or GND Current, per pin (ICC
)
−0.5 to +7.0V
−1.5 to VCC+1.5V
−0.5 to VCC+0.5V
Supply Voltage (VCC
DC Input or Output Voltage
(VIN, VOUT
)
V
V
)
0
VCC
)
±
±
±
)
)
20 mA
25 mA
50 mA
Operating Temp. Range (TA)
MM74HC
)
−40
+85
˚C
˚C
)
MM54HC
−55 +125
Storage Temperature Range (TSTG
Power Dissipation (PD)
(Note 3)
)
−65˚C to +150˚C
Input Rise or Fall Times
=
(tr, tf) VCC 2.0V
1000
500
ns
ns
ns
600 mW
500 mW
=
VCC 4.5V
S.O. Package only
=
VCC 6.0V
400
Lead Temperature (TL)
(Soldering 10 seconds)
260˚C
DC Electrical Characteristics (Note 4)
=
TA 25˚C
74HC
54HC
=
=
Symbol
Parameter
Conditions
VCC
TA −40 to 85˚C
TA −55 to 125˚C
Units
Typ
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
1.5
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
V
V
V
3.15
4.2
VIL
Maximum Low Level
0.5
0.5
0.5
Input Voltage
(Note 5)
1.35
1.8
1.35
1.8
1.35
1.8
=
VOH
Minimum High Level
Output Voltage
VIN VIH or VIL
|IOUT|≤20 µA
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
=
VIN VIH or VIL
|IOUT|≤4.0 mA
|IOUT|≤5.2 mA
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
=
VOL
Maximum Low Level
Output Voltage
VIN VIH or VIL
|IOUT|≤20 µA
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
=
VIN VIH or VIL
|IOUT|≤4.0 mA
|IOUT|≤5.2 mA
4.5V
6.0V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
=
±
±
±
1.0
IIN
Maximum Input
Current
VIN VCC or GND
0.1
1.0
µA
=
ICC
Maximum Quiescent
Supply Current
VIN VCC or GND
6.0V
2.0
20
40
µA
=
IOUT 0 µA
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating — plastic “N” package: −12 mW/˚C from 65˚C to 85˚C; ceramic “J” package: −12 mW/˚C from 100˚C to 125˚C.
±
Note 4: For a power supply of 5V 10% the worst case output voltages (V , and V ) occur for HC at 4.5V. Thus the 4.5V values should be used when designing
OH OL
=
with this supply. Worst case V and V occur at V
5.5V and 4.5V respectively. (The V value at 5.5V is 3.85V.) The worst case leakage current (I , I , and
IH IN CC
IH IL CC
I
) occur for CMOS at the higher voltage and so the 6.0V values should be used.
OZ
Note 5:
V
limits are currently tested at 20% of V . The above V specification (30% of V ) will be implemented no later than Q1, CY’89.
CC IL CC
IL
www.fairchildsemi.com
2
AC Electrical Characteristics
=
=
=
= =
VCC 5V, TA 25˚C, CL 15 pF, tr tf 6 ns
Symbol
Parameter
Conditions
Typ
Guaranteed
Limit
Units
tPHL, tPLH
Maximum Propagation
Delay
12
20
ns
AC Electrical Characteristics
=
=
= =
VCC 2.0V to 6.0V, CL 50 pF, tr tf 6 ns (unless otherwise specified)
=
TA 25˚C
74HC
54HC
=
=
Symbol
Parameter
Conditions
VCC
TA −40 to 85˚C
TA −55 to 125˚C
Units
Typ
Guaranteed Limits
tPHL, tPLH
Maximum Propagation
Delay
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
60
12
10
30
8
120
24
20
75
15
13
151
30
26
95
19
16
179
36
ns
ns
ns
ns
ns
ns
pF
30
t
TLH, tTHL
Maximum Output Rise
and Fall Time
110
22
7
19
CPD
CIN
Power Dissipation
Capacitance (Note 6)
Maximum Input
Capacitance
(per gate)
25
5
10
10
10
pF
2
=
=
C
PD CC
Note 6:
C
determines the no load dynamic power consumption, P
C
V
f+I
V
, and the no load dynamic current consumption, I
V
f+I
.
CC
PD
D
PD CC
CC CC
S
3
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4
Physical Dimensions inches (millimeters) unless otherwise noted
Cavity Dual-In Line Package (J)
Order Number MM54HC86J or MM74HC86J
Package J14A
Molded Dual-In Line Package (N)
Order Number MM74HC86N
Package N14A
5
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with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
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